[linux-2.6-block.git] / arch / arm64 / include / asm / kvm_asm.h

/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM_KVM_ASM_H__
#define __ARM_KVM_ASM_H__

#include <asm/virt.h>

/*
 * 0 is reserved as an invalid value.
 * Order *must* be kept in sync with the hyp switch code.
 */
#define	MPIDR_EL1	1	/* MultiProcessor Affinity Register */
#define	CSSELR_EL1	2	/* Cache Size Selection Register */
#define	SCTLR_EL1	3	/* System Control Register */
#define	ACTLR_EL1	4	/* Auxilliary Control Register */
#define	CPACR_EL1	5	/* Coprocessor Access Control */
#define	TTBR0_EL1	6	/* Translation Table Base Register 0 */
#define	TTBR1_EL1	7	/* Translation Table Base Register 1 */
#define	TCR_EL1		8	/* Translation Control Register */
#define	ESR_EL1		9	/* Exception Syndrome Register */
#define	AFSR0_EL1	10	/* Auxilary Fault Status Register 0 */
#define	AFSR1_EL1	11	/* Auxilary Fault Status Register 1 */
#define	FAR_EL1		12	/* Fault Address Register */
#define	MAIR_EL1	13	/* Memory Attribute Indirection Register */
#define	VBAR_EL1	14	/* Vector Base Address Register */
#define	CONTEXTIDR_EL1	15	/* Context ID Register */
#define	TPIDR_EL0	16	/* Thread ID, User R/W */
#define	TPIDRRO_EL0	17	/* Thread ID, User R/O */
#define	TPIDR_EL1	18	/* Thread ID, Privileged */
#define	AMAIR_EL1	19	/* Aux Memory Attribute Indirection Register */
#define	CNTKCTL_EL1	20	/* Timer Control Register (EL1) */
#define	PAR_EL1		21	/* Physical Address Register */
/* 32bit specific registers. Keep them at the end of the range */
#define	DACR32_EL2	22	/* Domain Access Control Register */
#define	IFSR32_EL2	23	/* Instruction Fault Status Register */
#define	FPEXC32_EL2	24	/* Floating-Point Exception Control Register */
#define	DBGVCR32_EL2	25	/* Debug Vector Catch Register */
#define	TEECR32_EL1	26	/* ThumbEE Configuration Register */
#define	TEEHBR32_EL1	27	/* ThumbEE Handler Base Register */
#define	NR_SYS_REGS	28

/* 32bit mapping */
#define c0_MPIDR	(MPIDR_EL1 * 2)	/* MultiProcessor ID Register */
#define c0_CSSELR	(CSSELR_EL1 * 2)/* Cache Size Selection Register */
#define c1_SCTLR	(SCTLR_EL1 * 2)	/* System Control Register */
#define c1_ACTLR	(ACTLR_EL1 * 2)	/* Auxiliary Control Register */
#define c1_CPACR	(CPACR_EL1 * 2)	/* Coprocessor Access Control */
#define c2_TTBR0	(TTBR0_EL1 * 2)	/* Translation Table Base Register 0 */
#define c2_TTBR0_high	(c2_TTBR0 + 1)	/* TTBR0 top 32 bits */
#define c2_TTBR1	(TTBR1_EL1 * 2)	/* Translation Table Base Register 1 */
#define c2_TTBR1_high	(c2_TTBR1 + 1)	/* TTBR1 top 32 bits */
#define c2_TTBCR	(TCR_EL1 * 2)	/* Translation Table Base Control R. */
#define c3_DACR		(DACR32_EL2 * 2)/* Domain Access Control Register */
#define c5_DFSR		(ESR_EL1 * 2)	/* Data Fault Status Register */
#define c5_IFSR		(IFSR32_EL2 * 2)/* Instruction Fault Status Register */
#define c5_ADFSR	(AFSR0_EL1 * 2)	/* Auxiliary Data Fault Status R */
#define c5_AIFSR	(AFSR1_EL1 * 2)	/* Auxiliary Instr Fault Status R */
#define c6_DFAR		(FAR_EL1 * 2)	/* Data Fault Address Register */
#define c6_IFAR		(c6_DFAR + 1)	/* Instruction Fault Address Register */
#define c7_PAR		(PAR_EL1 * 2)	/* Physical Address Register */
#define c7_PAR_high	(c7_PAR + 1)	/* PAR top 32 bits */
#define c10_PRRR	(MAIR_EL1 * 2)	/* Primary Region Remap Register */
#define c10_NMRR	(c10_PRRR + 1)	/* Normal Memory Remap Register */
#define c12_VBAR	(VBAR_EL1 * 2)	/* Vector Base Address Register */
#define c13_CID		(CONTEXTIDR_EL1 * 2)	/* Context ID Register */
#define c13_TID_URW	(TPIDR_EL0 * 2)	/* Thread ID, User R/W */
#define c13_TID_URO	(TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
#define c13_TID_PRIV	(TPIDR_EL1 * 2)	/* Thread ID, Privileged */
#define c10_AMAIR0	(AMAIR_EL1 * 2)	/* Aux Memory Attr Indirection Reg */
#define c10_AMAIR1	(c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL	(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
#define NR_CP15_REGS	(NR_SYS_REGS * 2)

#define ARM_EXCEPTION_IRQ	  0
#define ARM_EXCEPTION_TRAP	  1

#ifndef __ASSEMBLY__
struct kvm;
struct kvm_vcpu;

extern char __kvm_hyp_init[];
extern char __kvm_hyp_init_end[];

extern char __kvm_hyp_vector[];

#define	__kvm_hyp_code_start	__hyp_text_start
#define	__kvm_hyp_code_end	__hyp_text_end

extern void __kvm_flush_vm_context(void);
extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);

extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);

extern u64 __vgic_v3_get_ich_vtr_el2(void);

extern char __save_vgic_v2_state[];
extern char __restore_vgic_v2_state[];
extern char __save_vgic_v3_state[];
extern char __restore_vgic_v3_state[];

#endif

#endif /* __ARM_KVM_ASM_H__ */
Commit	Line	Data
fd9fc9f7 MZ	1	/*
	2	* Copyright (C) 2012,2013 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __ARM_KVM_ASM_H__
	19	#define __ARM_KVM_ASM_H__
	20
45451914 MZ	21	#include <asm/virt.h>
45451914 MZ	22
fd9fc9f7 MZ	23	/*
	24	* 0 is reserved as an invalid value.
	25	* Order must be kept in sync with the hyp switch code.
	26	*/
	27	#define MPIDR_EL1 1 /* MultiProcessor Affinity Register */
	28	#define CSSELR_EL1 2 /* Cache Size Selection Register */
	29	#define SCTLR_EL1 3 /* System Control Register */
	30	#define ACTLR_EL1 4 /* Auxilliary Control Register */
	31	#define CPACR_EL1 5 /* Coprocessor Access Control */
	32	#define TTBR0_EL1 6 /* Translation Table Base Register 0 */
	33	#define TTBR1_EL1 7 /* Translation Table Base Register 1 */
	34	#define TCR_EL1 8 /* Translation Control Register */
	35	#define ESR_EL1 9 /* Exception Syndrome Register */
	36	#define AFSR0_EL1 10 /* Auxilary Fault Status Register 0 */
	37	#define AFSR1_EL1 11 /* Auxilary Fault Status Register 1 */
	38	#define FAR_EL1 12 /* Fault Address Register */
	39	#define MAIR_EL1 13 /* Memory Attribute Indirection Register */
	40	#define VBAR_EL1 14 /* Vector Base Address Register */
	41	#define CONTEXTIDR_EL1 15 /* Context ID Register */
	42	#define TPIDR_EL0 16 /* Thread ID, User R/W */
	43	#define TPIDRRO_EL0 17 /* Thread ID, User R/O */
	44	#define TPIDR_EL1 18 /* Thread ID, Privileged */
	45	#define AMAIR_EL1 19 /* Aux Memory Attribute Indirection Register */
	46	#define CNTKCTL_EL1 20 /* Timer Control Register (EL1) */
1bbd8054	47	#define PAR_EL1 21 /* Physical Address Register */
40033a61	48	/* 32bit specific registers. Keep them at the end of the range */
1bbd8054 MZ	49	#define DACR32_EL2 22 /* Domain Access Control Register */
	50	#define IFSR32_EL2 23 /* Instruction Fault Status Register */
	51	#define FPEXC32_EL2 24 /* Floating-Point Exception Control Register */
	52	#define DBGVCR32_EL2 25 /* Debug Vector Catch Register */
	53	#define TEECR32_EL1 26 /* ThumbEE Configuration Register */
	54	#define TEEHBR32_EL1 27 /* ThumbEE Handler Base Register */
	55	#define NR_SYS_REGS 28
40033a61 MZ	56
	57	/* 32bit mapping */
	58	#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
	59	#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
	60	#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
	61	#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
	62	#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
	63	#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
	64	#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
	65	#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
	66	#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
	67	#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
	68	#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
	69	#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
	70	#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
	71	#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
	72	#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
	73	#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
	74	#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
1bbd8054 MZ	75	#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
1bbd8054 MZ	76	#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
40033a61 MZ	77	#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
	78	#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
	79	#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
	80	#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
	81	#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
	82	#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
	83	#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
4d44923b MZ	84	#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
4d44923b MZ	85	#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
40033a61 MZ	86	#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
40033a61 MZ	87	#define NR_CP15_REGS (NR_SYS_REGS * 2)
fd9fc9f7 MZ	88
	89	#define ARM_EXCEPTION_IRQ 0
	90	#define ARM_EXCEPTION_TRAP 1
	91
	92	#ifndef __ASSEMBLY__
	93	struct kvm;
	94	struct kvm_vcpu;
	95
	96	extern char __kvm_hyp_init[];
	97	extern char __kvm_hyp_init_end[];
	98
	99	extern char __kvm_hyp_vector[];
	100
45451914 MZ	101	#define __kvm_hyp_code_start __hyp_text_start
45451914 MZ	102	#define __kvm_hyp_code_end __hyp_text_end
fd9fc9f7 MZ	103
	104	extern void __kvm_flush_vm_context(void);
	105	extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
	106
	107	extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
1a9b1305	108
b2fb1c0d MZ	109	extern u64 __vgic_v3_get_ich_vtr_el2(void);
b2fb1c0d MZ	110
1a9b1305 MZ	111	extern char __save_vgic_v2_state[];
1a9b1305 MZ	112	extern char __restore_vgic_v2_state[];
754d3772 MZ	113	extern char __save_vgic_v3_state[];
754d3772 MZ	114	extern char __restore_vgic_v3_state[];
1a9b1305	115
fd9fc9f7 MZ	116	#endif
	117
	118	#endif /* __ARM_KVM_ASM_H__ */