[linux-2.6-block.git] / arch / arm64 / include / asm / insn.h

/*
 * Copyright (C) 2013 Huawei Ltd.
 * Author: Jiang Liu <liuj97@gmail.com>
 *
 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef	__ASM_INSN_H
#define	__ASM_INSN_H
#include <linux/types.h>

/* A64 instructions are always 32 bits. */
#define	AARCH64_INSN_SIZE		4

#ifndef __ASSEMBLY__
/*
 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
 * Section C3.1 "A64 instruction index by encoding":
 * AArch64 main encoding table
 *  Bit position
 *   28 27 26 25	Encoding Group
 *   0  0  -  -		Unallocated
 *   1  0  0  -		Data processing, immediate
 *   1  0  1  -		Branch, exception generation and system instructions
 *   -  1  -  0		Loads and stores
 *   -  1  0  1		Data processing - register
 *   0  1  1  1		Data processing - SIMD and floating point
 *   1  1  1  1		Data processing - SIMD and floating point
 * "-" means "don't care"
 */
enum aarch64_insn_encoding_class {
	AARCH64_INSN_CLS_UNKNOWN,	/* UNALLOCATED */
	AARCH64_INSN_CLS_DP_IMM,	/* Data processing - immediate */
	AARCH64_INSN_CLS_DP_REG,	/* Data processing - register */
	AARCH64_INSN_CLS_DP_FPSIMD,	/* Data processing - SIMD and FP */
	AARCH64_INSN_CLS_LDST,		/* Loads and stores */
	AARCH64_INSN_CLS_BR_SYS,	/* Branch, exception generation and
					 * system instructions */
};

enum aarch64_insn_hint_op {
	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
};

enum aarch64_insn_imm_type {
	AARCH64_INSN_IMM_ADR,
	AARCH64_INSN_IMM_26,
	AARCH64_INSN_IMM_19,
	AARCH64_INSN_IMM_16,
	AARCH64_INSN_IMM_14,
	AARCH64_INSN_IMM_12,
	AARCH64_INSN_IMM_9,
	AARCH64_INSN_IMM_7,
	AARCH64_INSN_IMM_6,
	AARCH64_INSN_IMM_S,
	AARCH64_INSN_IMM_R,
	AARCH64_INSN_IMM_MAX
};

enum aarch64_insn_register_type {
	AARCH64_INSN_REGTYPE_RT,
	AARCH64_INSN_REGTYPE_RN,
	AARCH64_INSN_REGTYPE_RT2,
	AARCH64_INSN_REGTYPE_RM,
	AARCH64_INSN_REGTYPE_RD,
	AARCH64_INSN_REGTYPE_RA,
};

enum aarch64_insn_register {
	AARCH64_INSN_REG_0  = 0,
	AARCH64_INSN_REG_1  = 1,
	AARCH64_INSN_REG_2  = 2,
	AARCH64_INSN_REG_3  = 3,
	AARCH64_INSN_REG_4  = 4,
	AARCH64_INSN_REG_5  = 5,
	AARCH64_INSN_REG_6  = 6,
	AARCH64_INSN_REG_7  = 7,
	AARCH64_INSN_REG_8  = 8,
	AARCH64_INSN_REG_9  = 9,
	AARCH64_INSN_REG_10 = 10,
	AARCH64_INSN_REG_11 = 11,
	AARCH64_INSN_REG_12 = 12,
	AARCH64_INSN_REG_13 = 13,
	AARCH64_INSN_REG_14 = 14,
	AARCH64_INSN_REG_15 = 15,
	AARCH64_INSN_REG_16 = 16,
	AARCH64_INSN_REG_17 = 17,
	AARCH64_INSN_REG_18 = 18,
	AARCH64_INSN_REG_19 = 19,
	AARCH64_INSN_REG_20 = 20,
	AARCH64_INSN_REG_21 = 21,
	AARCH64_INSN_REG_22 = 22,
	AARCH64_INSN_REG_23 = 23,
	AARCH64_INSN_REG_24 = 24,
	AARCH64_INSN_REG_25 = 25,
	AARCH64_INSN_REG_26 = 26,
	AARCH64_INSN_REG_27 = 27,
	AARCH64_INSN_REG_28 = 28,
	AARCH64_INSN_REG_29 = 29,
	AARCH64_INSN_REG_FP = 29, /* Frame pointer */
	AARCH64_INSN_REG_30 = 30,
	AARCH64_INSN_REG_LR = 30, /* Link register */
	AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
};

enum aarch64_insn_variant {
	AARCH64_INSN_VARIANT_32BIT,
	AARCH64_INSN_VARIANT_64BIT
};

enum aarch64_insn_condition {
	AARCH64_INSN_COND_EQ = 0x0, /* == */
	AARCH64_INSN_COND_NE = 0x1, /* != */
	AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
	AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
	AARCH64_INSN_COND_MI = 0x4, /* < 0 */
	AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
	AARCH64_INSN_COND_VS = 0x6, /* overflow */
	AARCH64_INSN_COND_VC = 0x7, /* no overflow */
	AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
	AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
	AARCH64_INSN_COND_GE = 0xa, /* signed >= */
	AARCH64_INSN_COND_LT = 0xb, /* signed < */
	AARCH64_INSN_COND_GT = 0xc, /* signed > */
	AARCH64_INSN_COND_LE = 0xd, /* signed <= */
	AARCH64_INSN_COND_AL = 0xe, /* always */
};

enum aarch64_insn_branch_type {
	AARCH64_INSN_BRANCH_NOLINK,
	AARCH64_INSN_BRANCH_LINK,
	AARCH64_INSN_BRANCH_RETURN,
	AARCH64_INSN_BRANCH_COMP_ZERO,
	AARCH64_INSN_BRANCH_COMP_NONZERO,
};

enum aarch64_insn_size_type {
	AARCH64_INSN_SIZE_8,
	AARCH64_INSN_SIZE_16,
	AARCH64_INSN_SIZE_32,
	AARCH64_INSN_SIZE_64,
};

enum aarch64_insn_ldst_type {
	AARCH64_INSN_LDST_LOAD_REG_OFFSET,
	AARCH64_INSN_LDST_STORE_REG_OFFSET,
	AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
	AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
	AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
	AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
};

enum aarch64_insn_adsb_type {
	AARCH64_INSN_ADSB_ADD,
	AARCH64_INSN_ADSB_SUB,
	AARCH64_INSN_ADSB_ADD_SETFLAGS,
	AARCH64_INSN_ADSB_SUB_SETFLAGS
};

enum aarch64_insn_movewide_type {
	AARCH64_INSN_MOVEWIDE_ZERO,
	AARCH64_INSN_MOVEWIDE_KEEP,
	AARCH64_INSN_MOVEWIDE_INVERSE
};

enum aarch64_insn_bitfield_type {
	AARCH64_INSN_BITFIELD_MOVE,
	AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
	AARCH64_INSN_BITFIELD_MOVE_SIGNED
};

enum aarch64_insn_data1_type {
	AARCH64_INSN_DATA1_REVERSE_16,
	AARCH64_INSN_DATA1_REVERSE_32,
	AARCH64_INSN_DATA1_REVERSE_64,
};

enum aarch64_insn_data2_type {
	AARCH64_INSN_DATA2_UDIV,
	AARCH64_INSN_DATA2_SDIV,
	AARCH64_INSN_DATA2_LSLV,
	AARCH64_INSN_DATA2_LSRV,
	AARCH64_INSN_DATA2_ASRV,
	AARCH64_INSN_DATA2_RORV,
};

enum aarch64_insn_data3_type {
	AARCH64_INSN_DATA3_MADD,
	AARCH64_INSN_DATA3_MSUB,
};

enum aarch64_insn_logic_type {
	AARCH64_INSN_LOGIC_AND,
	AARCH64_INSN_LOGIC_BIC,
	AARCH64_INSN_LOGIC_ORR,
	AARCH64_INSN_LOGIC_ORN,
	AARCH64_INSN_LOGIC_EOR,
	AARCH64_INSN_LOGIC_EON,
	AARCH64_INSN_LOGIC_AND_SETFLAGS,
	AARCH64_INSN_LOGIC_BIC_SETFLAGS
};

#define	__AARCH64_INSN_FUNCS(abbr, mask, val)	\
static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
{ return (code & (mask)) == (val); } \
static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
{ return (val); }

__AARCH64_INSN_FUNCS(str_reg,	0x3FE0EC00, 0x38206800)
__AARCH64_INSN_FUNCS(ldr_reg,	0x3FE0EC00, 0x38606800)
__AARCH64_INSN_FUNCS(stp_post,	0x7FC00000, 0x28800000)
__AARCH64_INSN_FUNCS(ldp_post,	0x7FC00000, 0x28C00000)
__AARCH64_INSN_FUNCS(stp_pre,	0x7FC00000, 0x29800000)
__AARCH64_INSN_FUNCS(ldp_pre,	0x7FC00000, 0x29C00000)
__AARCH64_INSN_FUNCS(add_imm,	0x7F000000, 0x11000000)
__AARCH64_INSN_FUNCS(adds_imm,	0x7F000000, 0x31000000)
__AARCH64_INSN_FUNCS(sub_imm,	0x7F000000, 0x51000000)
__AARCH64_INSN_FUNCS(subs_imm,	0x7F000000, 0x71000000)
__AARCH64_INSN_FUNCS(movn,	0x7F800000, 0x12800000)
__AARCH64_INSN_FUNCS(sbfm,	0x7F800000, 0x13000000)
__AARCH64_INSN_FUNCS(bfm,	0x7F800000, 0x33000000)
__AARCH64_INSN_FUNCS(movz,	0x7F800000, 0x52800000)
__AARCH64_INSN_FUNCS(ubfm,	0x7F800000, 0x53000000)
__AARCH64_INSN_FUNCS(movk,	0x7F800000, 0x72800000)
__AARCH64_INSN_FUNCS(add,	0x7F200000, 0x0B000000)
__AARCH64_INSN_FUNCS(adds,	0x7F200000, 0x2B000000)
__AARCH64_INSN_FUNCS(sub,	0x7F200000, 0x4B000000)
__AARCH64_INSN_FUNCS(subs,	0x7F200000, 0x6B000000)
__AARCH64_INSN_FUNCS(madd,	0x7FE08000, 0x1B000000)
__AARCH64_INSN_FUNCS(msub,	0x7FE08000, 0x1B008000)
__AARCH64_INSN_FUNCS(udiv,	0x7FE0FC00, 0x1AC00800)
__AARCH64_INSN_FUNCS(sdiv,	0x7FE0FC00, 0x1AC00C00)
__AARCH64_INSN_FUNCS(lslv,	0x7FE0FC00, 0x1AC02000)
__AARCH64_INSN_FUNCS(lsrv,	0x7FE0FC00, 0x1AC02400)
__AARCH64_INSN_FUNCS(asrv,	0x7FE0FC00, 0x1AC02800)
__AARCH64_INSN_FUNCS(rorv,	0x7FE0FC00, 0x1AC02C00)
__AARCH64_INSN_FUNCS(rev16,	0x7FFFFC00, 0x5AC00400)
__AARCH64_INSN_FUNCS(rev32,	0x7FFFFC00, 0x5AC00800)
__AARCH64_INSN_FUNCS(rev64,	0x7FFFFC00, 0x5AC00C00)
__AARCH64_INSN_FUNCS(and,	0x7F200000, 0x0A000000)
__AARCH64_INSN_FUNCS(bic,	0x7F200000, 0x0A200000)
__AARCH64_INSN_FUNCS(orr,	0x7F200000, 0x2A000000)
__AARCH64_INSN_FUNCS(orn,	0x7F200000, 0x2A200000)
__AARCH64_INSN_FUNCS(eor,	0x7F200000, 0x4A000000)
__AARCH64_INSN_FUNCS(eon,	0x7F200000, 0x4A200000)
__AARCH64_INSN_FUNCS(ands,	0x7F200000, 0x6A000000)
__AARCH64_INSN_FUNCS(bics,	0x7F200000, 0x6A200000)
__AARCH64_INSN_FUNCS(b,		0xFC000000, 0x14000000)
__AARCH64_INSN_FUNCS(bl,	0xFC000000, 0x94000000)
__AARCH64_INSN_FUNCS(cbz,	0xFE000000, 0x34000000)
__AARCH64_INSN_FUNCS(cbnz,	0xFE000000, 0x35000000)
__AARCH64_INSN_FUNCS(bcond,	0xFF000010, 0x54000000)
__AARCH64_INSN_FUNCS(svc,	0xFFE0001F, 0xD4000001)
__AARCH64_INSN_FUNCS(hvc,	0xFFE0001F, 0xD4000002)
__AARCH64_INSN_FUNCS(smc,	0xFFE0001F, 0xD4000003)
__AARCH64_INSN_FUNCS(brk,	0xFFE0001F, 0xD4200000)
__AARCH64_INSN_FUNCS(hint,	0xFFFFF01F, 0xD503201F)
__AARCH64_INSN_FUNCS(br,	0xFFFFFC1F, 0xD61F0000)
__AARCH64_INSN_FUNCS(blr,	0xFFFFFC1F, 0xD63F0000)
__AARCH64_INSN_FUNCS(ret,	0xFFFFFC1F, 0xD65F0000)

#undef	__AARCH64_INSN_FUNCS

bool aarch64_insn_is_nop(u32 insn);

int aarch64_insn_read(void *addr, u32 *insnp);
int aarch64_insn_write(void *addr, u32 insn);
enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
				  u32 insn, u64 imm);
u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
				enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_register reg,
				     enum aarch64_insn_variant variant,
				     enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_condition cond);
u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
u32 aarch64_insn_gen_nop(void);
u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
				enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
				    enum aarch64_insn_register base,
				    enum aarch64_insn_register offset,
				    enum aarch64_insn_size_type size,
				    enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
				     enum aarch64_insn_register reg2,
				     enum aarch64_insn_register base,
				     int offset,
				     enum aarch64_insn_variant variant,
				     enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
				 enum aarch64_insn_register src,
				 int imm, enum aarch64_insn_variant variant,
				 enum aarch64_insn_adsb_type type);
u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
			      enum aarch64_insn_register src,
			      int immr, int imms,
			      enum aarch64_insn_variant variant,
			      enum aarch64_insn_bitfield_type type);
u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
			      int imm, int shift,
			      enum aarch64_insn_variant variant,
			      enum aarch64_insn_movewide_type type);
u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
					 enum aarch64_insn_register src,
					 enum aarch64_insn_register reg,
					 int shift,
					 enum aarch64_insn_variant variant,
					 enum aarch64_insn_adsb_type type);
u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data1_type type);
u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_register reg,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data2_type type);
u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_register reg1,
			   enum aarch64_insn_register reg2,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data3_type type);
u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
					 enum aarch64_insn_register src,
					 enum aarch64_insn_register reg,
					 int shift,
					 enum aarch64_insn_variant variant,
					 enum aarch64_insn_logic_type type);

bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);

int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
#endif /* __ASSEMBLY__ */

#endif	/* __ASM_INSN_H */
Commit	Line	Data
b11a64a4 JL	1	/*
	2	* Copyright (C) 2013 Huawei Ltd.
	3	* Author: Jiang Liu <liuj97@gmail.com>
	4	*
617d2fbc ZSL	5	* Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
617d2fbc ZSL	6	*
b11a64a4 JL	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_INSN_H
	20	#define __ASM_INSN_H
	21	#include <linux/types.h>
	22
ae164807 JL	23	/* A64 instructions are always 32 bits. */
	24	#define AARCH64_INSN_SIZE 4
	25
26e9b83a	26	#ifndef __ASSEMBLY__
b11a64a4 JL	27	/*
	28	* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
	29	* Section C3.1 "A64 instruction index by encoding":
	30	* AArch64 main encoding table
	31	* Bit position
	32	* 28 27 26 25 Encoding Group
	33	* 0 0 - - Unallocated
	34	* 1 0 0 - Data processing, immediate
	35	* 1 0 1 - Branch, exception generation and system instructions
	36	* - 1 - 0 Loads and stores
	37	* - 1 0 1 Data processing - register
	38	* 0 1 1 1 Data processing - SIMD and floating point
	39	* 1 1 1 1 Data processing - SIMD and floating point
	40	* "-" means "don't care"
	41	*/
	42	enum aarch64_insn_encoding_class {
	43	AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
	44	AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
	45	AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
	46	AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
	47	AARCH64_INSN_CLS_LDST, /* Loads and stores */
	48	AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
	49	* system instructions */
	50	};
	51
	52	enum aarch64_insn_hint_op {
	53	AARCH64_INSN_HINT_NOP = 0x0 << 5,
	54	AARCH64_INSN_HINT_YIELD = 0x1 << 5,
	55	AARCH64_INSN_HINT_WFE = 0x2 << 5,
	56	AARCH64_INSN_HINT_WFI = 0x3 << 5,
	57	AARCH64_INSN_HINT_SEV = 0x4 << 5,
	58	AARCH64_INSN_HINT_SEVL = 0x5 << 5,
	59	};
	60
c84fced8 JL	61	enum aarch64_insn_imm_type {
	62	AARCH64_INSN_IMM_ADR,
	63	AARCH64_INSN_IMM_26,
	64	AARCH64_INSN_IMM_19,
	65	AARCH64_INSN_IMM_16,
	66	AARCH64_INSN_IMM_14,
	67	AARCH64_INSN_IMM_12,
	68	AARCH64_INSN_IMM_9,
1bba567d	69	AARCH64_INSN_IMM_7,
5fdc639a	70	AARCH64_INSN_IMM_6,
4a89d2c9 ZSL	71	AARCH64_INSN_IMM_S,
4a89d2c9 ZSL	72	AARCH64_INSN_IMM_R,
c84fced8 JL	73	AARCH64_INSN_IMM_MAX
	74	};
	75
617d2fbc ZSL	76	enum aarch64_insn_register_type {
617d2fbc ZSL	77	AARCH64_INSN_REGTYPE_RT,
c0cafbae	78	AARCH64_INSN_REGTYPE_RN,
1bba567d	79	AARCH64_INSN_REGTYPE_RT2,
17cac179	80	AARCH64_INSN_REGTYPE_RM,
9951a157	81	AARCH64_INSN_REGTYPE_RD,
27f95ba5	82	AARCH64_INSN_REGTYPE_RA,
617d2fbc ZSL	83	};
	84
	85	enum aarch64_insn_register {
	86	AARCH64_INSN_REG_0 = 0,
	87	AARCH64_INSN_REG_1 = 1,
	88	AARCH64_INSN_REG_2 = 2,
	89	AARCH64_INSN_REG_3 = 3,
	90	AARCH64_INSN_REG_4 = 4,
	91	AARCH64_INSN_REG_5 = 5,
	92	AARCH64_INSN_REG_6 = 6,
	93	AARCH64_INSN_REG_7 = 7,
	94	AARCH64_INSN_REG_8 = 8,
	95	AARCH64_INSN_REG_9 = 9,
	96	AARCH64_INSN_REG_10 = 10,
	97	AARCH64_INSN_REG_11 = 11,
	98	AARCH64_INSN_REG_12 = 12,
	99	AARCH64_INSN_REG_13 = 13,
	100	AARCH64_INSN_REG_14 = 14,
	101	AARCH64_INSN_REG_15 = 15,
	102	AARCH64_INSN_REG_16 = 16,
	103	AARCH64_INSN_REG_17 = 17,
	104	AARCH64_INSN_REG_18 = 18,
	105	AARCH64_INSN_REG_19 = 19,
	106	AARCH64_INSN_REG_20 = 20,
	107	AARCH64_INSN_REG_21 = 21,
	108	AARCH64_INSN_REG_22 = 22,
	109	AARCH64_INSN_REG_23 = 23,
	110	AARCH64_INSN_REG_24 = 24,
	111	AARCH64_INSN_REG_25 = 25,
	112	AARCH64_INSN_REG_26 = 26,
	113	AARCH64_INSN_REG_27 = 27,
	114	AARCH64_INSN_REG_28 = 28,
	115	AARCH64_INSN_REG_29 = 29,
	116	AARCH64_INSN_REG_FP = 29, /* Frame pointer */
	117	AARCH64_INSN_REG_30 = 30,
	118	AARCH64_INSN_REG_LR = 30, /* Link register */
	119	AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
	120	AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
	121	};
	122
	123	enum aarch64_insn_variant {
	124	AARCH64_INSN_VARIANT_32BIT,
	125	AARCH64_INSN_VARIANT_64BIT
	126	};
	127
345e0d35 ZSL	128	enum aarch64_insn_condition {
	129	AARCH64_INSN_COND_EQ = 0x0, /* == */
	130	AARCH64_INSN_COND_NE = 0x1, /* != */
	131	AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
	132	AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
	133	AARCH64_INSN_COND_MI = 0x4, /* < 0 */
	134	AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
	135	AARCH64_INSN_COND_VS = 0x6, /* overflow */
	136	AARCH64_INSN_COND_VC = 0x7, /* no overflow */
	137	AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
	138	AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
	139	AARCH64_INSN_COND_GE = 0xa, /* signed >= */
	140	AARCH64_INSN_COND_LT = 0xb, /* signed < */
	141	AARCH64_INSN_COND_GT = 0xc, /* signed > */
	142	AARCH64_INSN_COND_LE = 0xd, /* signed <= */
	143	AARCH64_INSN_COND_AL = 0xe, /* always */
	144	};
	145
5c5bf25d JL	146	enum aarch64_insn_branch_type {
	147	AARCH64_INSN_BRANCH_NOLINK,
	148	AARCH64_INSN_BRANCH_LINK,
c0cafbae	149	AARCH64_INSN_BRANCH_RETURN,
617d2fbc ZSL	150	AARCH64_INSN_BRANCH_COMP_ZERO,
617d2fbc ZSL	151	AARCH64_INSN_BRANCH_COMP_NONZERO,
5c5bf25d JL	152	};
5c5bf25d JL	153
17cac179 ZSL	154	enum aarch64_insn_size_type {
	155	AARCH64_INSN_SIZE_8,
	156	AARCH64_INSN_SIZE_16,
	157	AARCH64_INSN_SIZE_32,
	158	AARCH64_INSN_SIZE_64,
	159	};
	160
	161	enum aarch64_insn_ldst_type {
	162	AARCH64_INSN_LDST_LOAD_REG_OFFSET,
	163	AARCH64_INSN_LDST_STORE_REG_OFFSET,
1bba567d ZSL	164	AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
	165	AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
	166	AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
	167	AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
17cac179 ZSL	168	};
17cac179 ZSL	169
9951a157 ZSL	170	enum aarch64_insn_adsb_type {
	171	AARCH64_INSN_ADSB_ADD,
	172	AARCH64_INSN_ADSB_SUB,
	173	AARCH64_INSN_ADSB_ADD_SETFLAGS,
	174	AARCH64_INSN_ADSB_SUB_SETFLAGS
	175	};
	176
6098f2d5 ZSL	177	enum aarch64_insn_movewide_type {
	178	AARCH64_INSN_MOVEWIDE_ZERO,
	179	AARCH64_INSN_MOVEWIDE_KEEP,
	180	AARCH64_INSN_MOVEWIDE_INVERSE
	181	};
	182
4a89d2c9 ZSL	183	enum aarch64_insn_bitfield_type {
	184	AARCH64_INSN_BITFIELD_MOVE,
	185	AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
	186	AARCH64_INSN_BITFIELD_MOVE_SIGNED
	187	};
	188
546dd36b ZSL	189	enum aarch64_insn_data1_type {
	190	AARCH64_INSN_DATA1_REVERSE_16,
	191	AARCH64_INSN_DATA1_REVERSE_32,
	192	AARCH64_INSN_DATA1_REVERSE_64,
	193	};
	194
64810639 ZSL	195	enum aarch64_insn_data2_type {
	196	AARCH64_INSN_DATA2_UDIV,
	197	AARCH64_INSN_DATA2_SDIV,
	198	AARCH64_INSN_DATA2_LSLV,
	199	AARCH64_INSN_DATA2_LSRV,
	200	AARCH64_INSN_DATA2_ASRV,
	201	AARCH64_INSN_DATA2_RORV,
	202	};
	203
27f95ba5 ZSL	204	enum aarch64_insn_data3_type {
	205	AARCH64_INSN_DATA3_MADD,
	206	AARCH64_INSN_DATA3_MSUB,
	207	};
	208
5e6e15a2 ZSL	209	enum aarch64_insn_logic_type {
	210	AARCH64_INSN_LOGIC_AND,
	211	AARCH64_INSN_LOGIC_BIC,
	212	AARCH64_INSN_LOGIC_ORR,
	213	AARCH64_INSN_LOGIC_ORN,
	214	AARCH64_INSN_LOGIC_EOR,
	215	AARCH64_INSN_LOGIC_EON,
	216	AARCH64_INSN_LOGIC_AND_SETFLAGS,
	217	AARCH64_INSN_LOGIC_BIC_SETFLAGS
	218	};
	219
b11a64a4 JL	220	#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
	221	static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
	222	{ return (code & (mask)) == (val); } \
	223	static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
	224	{ return (val); }
	225
17cac179 ZSL	226	__AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
17cac179 ZSL	227	__AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
1bba567d ZSL	228	__AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
	229	__AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
	230	__AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
	231	__AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
9951a157 ZSL	232	__AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
	233	__AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
	234	__AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
	235	__AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
6098f2d5	236	__AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
4a89d2c9 ZSL	237	__AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
4a89d2c9 ZSL	238	__AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
6098f2d5	239	__AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
4a89d2c9	240	__AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
6098f2d5	241	__AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
5fdc639a ZSL	242	__AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
	243	__AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
	244	__AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
	245	__AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
27f95ba5 ZSL	246	__AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
27f95ba5 ZSL	247	__AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
64810639 ZSL	248	__AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
	249	__AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
	250	__AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
	251	__AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
	252	__AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
	253	__AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
546dd36b ZSL	254	__AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
	255	__AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
	256	__AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
5e6e15a2 ZSL	257	__AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
	258	__AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
	259	__AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
	260	__AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
	261	__AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
	262	__AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
	263	__AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
	264	__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
b11a64a4 JL	265	__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
b11a64a4 JL	266	__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
617d2fbc ZSL	267	__AARCH64_INSN_FUNCS(cbz, 0xFE000000, 0x34000000)
617d2fbc ZSL	268	__AARCH64_INSN_FUNCS(cbnz, 0xFE000000, 0x35000000)
345e0d35	269	__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
b11a64a4 JL	270	__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
	271	__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
	272	__AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
	273	__AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
	274	__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
c0cafbae ZSL	275	__AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
	276	__AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
	277	__AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
b11a64a4 JL	278
	279	#undef __AARCH64_INSN_FUNCS
	280
	281	bool aarch64_insn_is_nop(u32 insn);
	282
ae164807 JL	283	int aarch64_insn_read(void addr, u32 insnp);
ae164807 JL	284	int aarch64_insn_write(void *addr, u32 insn);
b11a64a4	285	enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
c84fced8 JL	286	u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
c84fced8 JL	287	u32 insn, u64 imm);
5c5bf25d JL	288	u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
5c5bf25d JL	289	enum aarch64_insn_branch_type type);
617d2fbc ZSL	290	u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
	291	enum aarch64_insn_register reg,
	292	enum aarch64_insn_variant variant,
	293	enum aarch64_insn_branch_type type);
345e0d35 ZSL	294	u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
345e0d35 ZSL	295	enum aarch64_insn_condition cond);
5c5bf25d JL	296	u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
5c5bf25d JL	297	u32 aarch64_insn_gen_nop(void);
c0cafbae ZSL	298	u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
c0cafbae ZSL	299	enum aarch64_insn_branch_type type);
17cac179 ZSL	300	u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
	301	enum aarch64_insn_register base,
	302	enum aarch64_insn_register offset,
	303	enum aarch64_insn_size_type size,
	304	enum aarch64_insn_ldst_type type);
1bba567d ZSL	305	u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
	306	enum aarch64_insn_register reg2,
	307	enum aarch64_insn_register base,
	308	int offset,
	309	enum aarch64_insn_variant variant,
	310	enum aarch64_insn_ldst_type type);
9951a157 ZSL	311	u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
	312	enum aarch64_insn_register src,
	313	int imm, enum aarch64_insn_variant variant,
	314	enum aarch64_insn_adsb_type type);
4a89d2c9 ZSL	315	u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
	316	enum aarch64_insn_register src,
	317	int immr, int imms,
	318	enum aarch64_insn_variant variant,
	319	enum aarch64_insn_bitfield_type type);
6098f2d5 ZSL	320	u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
	321	int imm, int shift,
	322	enum aarch64_insn_variant variant,
	323	enum aarch64_insn_movewide_type type);
5fdc639a ZSL	324	u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
	325	enum aarch64_insn_register src,
	326	enum aarch64_insn_register reg,
	327	int shift,
	328	enum aarch64_insn_variant variant,
	329	enum aarch64_insn_adsb_type type);
546dd36b ZSL	330	u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
	331	enum aarch64_insn_register src,
	332	enum aarch64_insn_variant variant,
	333	enum aarch64_insn_data1_type type);
64810639 ZSL	334	u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
	335	enum aarch64_insn_register src,
	336	enum aarch64_insn_register reg,
	337	enum aarch64_insn_variant variant,
	338	enum aarch64_insn_data2_type type);
27f95ba5 ZSL	339	u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
	340	enum aarch64_insn_register src,
	341	enum aarch64_insn_register reg1,
	342	enum aarch64_insn_register reg2,
	343	enum aarch64_insn_variant variant,
	344	enum aarch64_insn_data3_type type);
5e6e15a2 ZSL	345	u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
	346	enum aarch64_insn_register src,
	347	enum aarch64_insn_register reg,
	348	int shift,
	349	enum aarch64_insn_variant variant,
	350	enum aarch64_insn_logic_type type);
5c5bf25d	351
b11a64a4 JL	352	bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
b11a64a4 JL	353
ae164807 JL	354	int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
	355	int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
	356	int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
26e9b83a	357	#endif /* __ASSEMBLY__ */
ae164807	358
b11a64a4	359	#endif /* __ASM_INSN_H */