[linux-2.6-block.git] / arch / arm64 / include / asm / hw_breakpoint.h

/*
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_HW_BREAKPOINT_H
#define __ASM_HW_BREAKPOINT_H

#include <asm/cputype.h>
#include <asm/cpufeature.h>
#include <asm/sysreg.h>
#include <asm/virt.h>

#ifdef __KERNEL__

struct arch_hw_breakpoint_ctrl {
	u32 __reserved	: 19,
	len		: 8,
	type		: 2,
	privilege	: 2,
	enabled		: 1;
};

struct arch_hw_breakpoint {
	u64 address;
	u64 trigger;
	struct arch_hw_breakpoint_ctrl ctrl;
};

/* Privilege Levels */
#define AARCH64_BREAKPOINT_EL1	1
#define AARCH64_BREAKPOINT_EL0	2

#define DBG_HMC_HYP		(1 << 13)

static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
{
	u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
		ctrl.enabled;

	if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
		val |= DBG_HMC_HYP;

	return val;
}

static inline void decode_ctrl_reg(u32 reg,
				   struct arch_hw_breakpoint_ctrl *ctrl)
{
	ctrl->enabled	= reg & 0x1;
	reg >>= 1;
	ctrl->privilege	= reg & 0x3;
	reg >>= 2;
	ctrl->type	= reg & 0x3;
	reg >>= 2;
	ctrl->len	= reg & 0xff;
}

/* Breakpoint */
#define ARM_BREAKPOINT_EXECUTE	0

/* Watchpoints */
#define ARM_BREAKPOINT_LOAD	1
#define ARM_BREAKPOINT_STORE	2
#define AARCH64_ESR_ACCESS_MASK	(1 << 6)

/* Lengths */
#define ARM_BREAKPOINT_LEN_1	0x1
#define ARM_BREAKPOINT_LEN_2	0x3
#define ARM_BREAKPOINT_LEN_3	0x7
#define ARM_BREAKPOINT_LEN_4	0xf
#define ARM_BREAKPOINT_LEN_5	0x1f
#define ARM_BREAKPOINT_LEN_6	0x3f
#define ARM_BREAKPOINT_LEN_7	0x7f
#define ARM_BREAKPOINT_LEN_8	0xff

/* Kernel stepping */
#define ARM_KERNEL_STEP_NONE	0
#define ARM_KERNEL_STEP_ACTIVE	1
#define ARM_KERNEL_STEP_SUSPEND	2

/*
 * Limits.
 * Changing these will require modifications to the register accessors.
 */
#define ARM_MAX_BRP		16
#define ARM_MAX_WRP		16

/* Virtual debug register bases. */
#define AARCH64_DBG_REG_BVR	0
#define AARCH64_DBG_REG_BCR	(AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
#define AARCH64_DBG_REG_WVR	(AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
#define AARCH64_DBG_REG_WCR	(AARCH64_DBG_REG_WVR + ARM_MAX_WRP)

/* Debug register names. */
#define AARCH64_DBG_REG_NAME_BVR	bvr
#define AARCH64_DBG_REG_NAME_BCR	bcr
#define AARCH64_DBG_REG_NAME_WVR	wvr
#define AARCH64_DBG_REG_NAME_WCR	wcr

/* Accessor macros for the debug registers. */
#define AARCH64_DBG_READ(N, REG, VAL) do {\
	VAL = read_sysreg(dbg##REG##N##_el1);\
} while (0)

#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
	write_sysreg(VAL, dbg##REG##N##_el1);\
} while (0)

struct task_struct;
struct notifier_block;
struct perf_event_attr;
struct perf_event;
struct pmu;

extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
				  int *gen_len, int *gen_type, int *offset);
extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
extern int hw_breakpoint_arch_parse(struct perf_event *bp,
				    const struct perf_event_attr *attr,
				    struct arch_hw_breakpoint *hw);
#define hw_breakpoint_arch_parse hw_breakpoint_arch_parse
extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
					   unsigned long val, void *data);

extern int arch_install_hw_breakpoint(struct perf_event *bp);
extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
extern void hw_breakpoint_pmu_read(struct perf_event *bp);
extern int hw_breakpoint_slots(int type);

#ifdef CONFIG_HAVE_HW_BREAKPOINT
extern void hw_breakpoint_thread_switch(struct task_struct *next);
extern void ptrace_hw_copy_thread(struct task_struct *task);
#else
static inline void hw_breakpoint_thread_switch(struct task_struct *next)
{
}
static inline void ptrace_hw_copy_thread(struct task_struct *task)
{
}
#endif

/* Determine number of BRP registers available. */
static inline int get_num_brps(void)
{
	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
	return 1 +
		cpuid_feature_extract_unsigned_field(dfr0,
						ID_AA64DFR0_BRPS_SHIFT);
}

/* Determine number of WRP registers available. */
static inline int get_num_wrps(void)
{
	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
	return 1 +
		cpuid_feature_extract_unsigned_field(dfr0,
						ID_AA64DFR0_WRPS_SHIFT);
}

#endif	/* __KERNEL__ */
#endif	/* __ASM_BREAKPOINT_H */
Commit	Line	Data
478fcb2c WD	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __ASM_HW_BREAKPOINT_H
	17	#define __ASM_HW_BREAKPOINT_H
	18
834bf887	19	#include <asm/cputype.h>
3085bb01	20	#include <asm/cpufeature.h>
adf75899	21	#include <asm/sysreg.h>
ae7e27fe	22	#include <asm/virt.h>
834bf887	23
478fcb2c WD	24	#ifdef __KERNEL__
	25
	26	struct arch_hw_breakpoint_ctrl {
	27	u32 __reserved : 19,
	28	len : 8,
	29	type : 2,
	30	privilege : 2,
	31	enabled : 1;
	32	};
	33
	34	struct arch_hw_breakpoint {
	35	u64 address;
	36	u64 trigger;
	37	struct arch_hw_breakpoint_ctrl ctrl;
	38	};
	39
ae7e27fe MZ	40	/* Privilege Levels */
	41	#define AARCH64_BREAKPOINT_EL1 1
	42	#define AARCH64_BREAKPOINT_EL0 2
	43
	44	#define DBG_HMC_HYP (1 << 13)
	45
478fcb2c WD	46	static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
478fcb2c WD	47	{
ae7e27fe	48	u32 val = (ctrl.len << 5) \| (ctrl.type << 3) \| (ctrl.privilege << 1) \|
478fcb2c	49	ctrl.enabled;
ae7e27fe MZ	50
	51	if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
	52	val \|= DBG_HMC_HYP;
	53
	54	return val;
478fcb2c WD	55	}
	56
	57	static inline void decode_ctrl_reg(u32 reg,
	58	struct arch_hw_breakpoint_ctrl *ctrl)
	59	{
	60	ctrl->enabled = reg & 0x1;
	61	reg >>= 1;
	62	ctrl->privilege = reg & 0x3;
	63	reg >>= 2;
	64	ctrl->type = reg & 0x3;
	65	reg >>= 2;
	66	ctrl->len = reg & 0xff;
	67	}
	68
	69	/* Breakpoint */
	70	#define ARM_BREAKPOINT_EXECUTE 0
	71
	72	/* Watchpoints */
	73	#define ARM_BREAKPOINT_LOAD 1
	74	#define ARM_BREAKPOINT_STORE 2
	75	#define AARCH64_ESR_ACCESS_MASK (1 << 6)
	76
478fcb2c WD	77	/* Lengths */
	78	#define ARM_BREAKPOINT_LEN_1 0x1
	79	#define ARM_BREAKPOINT_LEN_2 0x3
0ddb8e0b	80	#define ARM_BREAKPOINT_LEN_3 0x7
478fcb2c	81	#define ARM_BREAKPOINT_LEN_4 0xf
0ddb8e0b PA	82	#define ARM_BREAKPOINT_LEN_5 0x1f
	83	#define ARM_BREAKPOINT_LEN_6 0x3f
	84	#define ARM_BREAKPOINT_LEN_7 0x7f
478fcb2c WD	85	#define ARM_BREAKPOINT_LEN_8 0xff
	86
	87	/* Kernel stepping */
	88	#define ARM_KERNEL_STEP_NONE 0
	89	#define ARM_KERNEL_STEP_ACTIVE 1
	90	#define ARM_KERNEL_STEP_SUSPEND 2
	91
	92	/*
	93	* Limits.
	94	* Changing these will require modifications to the register accessors.
	95	*/
	96	#define ARM_MAX_BRP 16
	97	#define ARM_MAX_WRP 16
478fcb2c WD	98
	99	/* Virtual debug register bases. */
	100	#define AARCH64_DBG_REG_BVR 0
	101	#define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
	102	#define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
	103	#define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
	104
	105	/* Debug register names. */
adf75899 MR	106	#define AARCH64_DBG_REG_NAME_BVR bvr
	107	#define AARCH64_DBG_REG_NAME_BCR bcr
	108	#define AARCH64_DBG_REG_NAME_WVR wvr
	109	#define AARCH64_DBG_REG_NAME_WCR wcr
478fcb2c WD	110
	111	/* Accessor macros for the debug registers. */
	112	#define AARCH64_DBG_READ(N, REG, VAL) do {\
adf75899	113	VAL = read_sysreg(dbg##REG##N##_el1);\
478fcb2c WD	114	} while (0)
	115
	116	#define AARCH64_DBG_WRITE(N, REG, VAL) do {\
adf75899	117	write_sysreg(VAL, dbg##REG##N##_el1);\
478fcb2c WD	118	} while (0)
	119
	120	struct task_struct;
	121	struct notifier_block;
8c449753	122	struct perf_event_attr;
478fcb2c WD	123	struct perf_event;
	124	struct pmu;
	125
	126	extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
b08fb180	127	int gen_len, int gen_type, int *offset);
8e983ff9	128	extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
8c449753 FW	129	extern int hw_breakpoint_arch_parse(struct perf_event *bp,
	130	const struct perf_event_attr *attr,
	131	struct arch_hw_breakpoint *hw);
	132	#define hw_breakpoint_arch_parse hw_breakpoint_arch_parse
478fcb2c WD	133	extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
	134	unsigned long val, void *data);
	135
	136	extern int arch_install_hw_breakpoint(struct perf_event *bp);
	137	extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
	138	extern void hw_breakpoint_pmu_read(struct perf_event *bp);
	139	extern int hw_breakpoint_slots(int type);
	140
	141	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	142	extern void hw_breakpoint_thread_switch(struct task_struct *next);
	143	extern void ptrace_hw_copy_thread(struct task_struct *task);
	144	#else
	145	static inline void hw_breakpoint_thread_switch(struct task_struct *next)
	146	{
	147	}
	148	static inline void ptrace_hw_copy_thread(struct task_struct *task)
	149	{
	150	}
	151	#endif
	152
834bf887 AB	153	/* Determine number of BRP registers available. */
	154	static inline int get_num_brps(void)
	155	{
46823dd1	156	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
3085bb01	157	return 1 +
1944bf8e	158	cpuid_feature_extract_unsigned_field(dfr0,
3085bb01	159	ID_AA64DFR0_BRPS_SHIFT);
834bf887 AB	160	}
	161
	162	/* Determine number of WRP registers available. */
	163	static inline int get_num_wrps(void)
	164	{
46823dd1	165	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
3085bb01	166	return 1 +
1944bf8e	167	cpuid_feature_extract_unsigned_field(dfr0,
3085bb01	168	ID_AA64DFR0_WRPS_SHIFT);
834bf887 AB	169	}
834bf887 AB	170
478fcb2c WD	171	#endif /* __KERNEL__ */
478fcb2c WD	172	#endif /* __ASM_BREAKPOINT_H */