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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
f1a0c4aa CM |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
f1a0c4aa CM |
4 | */ |
5 | #ifndef __ASM_CACHE_H | |
6 | #define __ASM_CACHE_H | |
7 | ||
02f7760e WD |
8 | #include <asm/cputype.h> |
9 | ||
10 | #define CTR_L1IP_SHIFT 14 | |
11 | #define CTR_L1IP_MASK 3 | |
6ae4b6e0 | 12 | #define CTR_DMINLINE_SHIFT 16 |
4c4a39dd | 13 | #define CTR_IMINLINE_SHIFT 0 |
ee9d90be | 14 | #define CTR_IMINLINE_MASK 0xf |
6ae4b6e0 | 15 | #define CTR_ERG_SHIFT 20 |
02f7760e WD |
16 | #define CTR_CWG_SHIFT 24 |
17 | #define CTR_CWG_MASK 15 | |
6ae4b6e0 SD |
18 | #define CTR_IDC_SHIFT 28 |
19 | #define CTR_DIC_SHIFT 29 | |
02f7760e | 20 | |
4c4a39dd | 21 | #define CTR_CACHE_MINLINE_MASK \ |
ee9d90be | 22 | (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT) |
4c4a39dd | 23 | |
02f7760e WD |
24 | #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) |
25 | ||
dda288d7 | 26 | #define ICACHE_POLICY_VPIPT 0 |
02f7760e WD |
27 | #define ICACHE_POLICY_VIPT 2 |
28 | #define ICACHE_POLICY_PIPT 3 | |
a41dc0e8 | 29 | |
d93277b9 | 30 | #define L1_CACHE_SHIFT (6) |
f1a0c4aa CM |
31 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
32 | ||
1602df02 SP |
33 | |
34 | #define CLIDR_LOUU_SHIFT 27 | |
35 | #define CLIDR_LOC_SHIFT 24 | |
36 | #define CLIDR_LOUIS_SHIFT 21 | |
37 | ||
38 | #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7) | |
39 | #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) | |
40 | #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) | |
41 | ||
f1a0c4aa CM |
42 | /* |
43 | * Memory returned by kmalloc() may be used for DMA, so we must make | |
44 | * sure that all such allocations are cache aligned. Otherwise, | |
45 | * unrelated code may cause parts of the buffer to be read into the | |
46 | * cache before the transfer is done, causing old data to be seen by | |
47 | * the CPU. | |
48 | */ | |
ebc7e21e | 49 | #define ARCH_DMA_MINALIGN (128) |
a41dc0e8 | 50 | |
eb214f2d AK |
51 | #ifdef CONFIG_KASAN_SW_TAGS |
52 | #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT) | |
eb214f2d AK |
53 | #endif |
54 | ||
a41dc0e8 CM |
55 | #ifndef __ASSEMBLY__ |
56 | ||
02f7760e WD |
57 | #include <linux/bitops.h> |
58 | ||
59 | #define ICACHEF_ALIASING 0 | |
dda288d7 | 60 | #define ICACHEF_VPIPT 1 |
02f7760e WD |
61 | extern unsigned long __icache_flags; |
62 | ||
63 | /* | |
64 | * Whilst the D-side always behaves as PIPT on AArch64, aliasing is | |
65 | * permitted in the I-cache. | |
66 | */ | |
67 | static inline int icache_is_aliasing(void) | |
68 | { | |
69 | return test_bit(ICACHEF_ALIASING, &__icache_flags); | |
70 | } | |
71 | ||
dda288d7 WD |
72 | static inline int icache_is_vpipt(void) |
73 | { | |
74 | return test_bit(ICACHEF_VPIPT, &__icache_flags); | |
75 | } | |
76 | ||
02f7760e WD |
77 | static inline u32 cache_type_cwg(void) |
78 | { | |
79 | return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; | |
80 | } | |
81 | ||
80d83812 | 82 | #define __read_mostly __section(.data..read_mostly) |
e4f88d83 | 83 | |
8f5c9037 | 84 | static inline int cache_line_size_of_cpu(void) |
a41dc0e8 CM |
85 | { |
86 | u32 cwg = cache_type_cwg(); | |
8f5c9037 | 87 | |
ebc7e21e | 88 | return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; |
a41dc0e8 CM |
89 | } |
90 | ||
7b8c87b2 | 91 | int cache_line_size(void); |
a41dc0e8 | 92 | |
1602df02 SP |
93 | /* |
94 | * Read the effective value of CTR_EL0. | |
95 | * | |
96 | * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a), | |
97 | * section D10.2.33 "CTR_EL0, Cache Type Register" : | |
98 | * | |
99 | * CTR_EL0.IDC reports the data cache clean requirements for | |
100 | * instruction to data coherence. | |
101 | * | |
102 | * 0 - dcache clean to PoU is required unless : | |
103 | * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0) | |
104 | * 1 - dcache clean to PoU is not required for i-to-d coherence. | |
105 | * | |
106 | * This routine provides the CTR_EL0 with the IDC field updated to the | |
107 | * effective state. | |
108 | */ | |
109 | static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void) | |
110 | { | |
111 | u32 ctr = read_cpuid_cachetype(); | |
112 | ||
113 | if (!(ctr & BIT(CTR_IDC_SHIFT))) { | |
114 | u64 clidr = read_sysreg(clidr_el1); | |
115 | ||
116 | if (CLIDR_LOC(clidr) == 0 || | |
117 | (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0)) | |
118 | ctr |= BIT(CTR_IDC_SHIFT); | |
119 | } | |
120 | ||
121 | return ctr; | |
122 | } | |
123 | ||
a41dc0e8 | 124 | #endif /* __ASSEMBLY__ */ |
f1a0c4aa CM |
125 | |
126 | #endif |