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1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * dts file for Xilinx ZynqMP ZC1275 | |
4 | * | |
9d648af4 | 5 | * (C) Copyright 2017 - 2021, Xilinx, Inc. |
d665c743 | 6 | * |
4e4ddd3d MS |
7 | * Michal Simek <michal.simek@amd.com> |
8 | * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> | |
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9 | */ |
10 | ||
11 | /dts-v1/; | |
12 | ||
13 | #include "zynqmp.dtsi" | |
9c8a47b4 | 14 | #include "zynqmp-clk-ccf.dtsi" |
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15 | |
16 | / { | |
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17 | model = "ZynqMP ZCU1275 RevA"; |
18 | compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; | |
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19 | |
20 | aliases { | |
21 | serial0 = &uart0; | |
22 | serial1 = &dcc; | |
9d648af4 | 23 | spi0 = &qspi; |
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24 | }; |
25 | ||
26 | chosen { | |
27 | bootargs = "earlycon"; | |
28 | stdout-path = "serial0:115200n8"; | |
29 | }; | |
30 | ||
31 | memory@0 { | |
32 | device_type = "memory"; | |
33 | reg = <0x0 0x0 0x0 0x80000000>; | |
34 | }; | |
35 | }; | |
36 | ||
37 | &dcc { | |
38 | status = "okay"; | |
39 | }; | |
40 | ||
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41 | &gpio { |
42 | status = "okay"; | |
43 | }; | |
44 | ||
45 | &qspi { | |
46 | status = "okay"; | |
47 | flash@0 { | |
48 | compatible = "m25p80", "jedec,spi-nor"; | |
49 | reg = <0x0>; | |
50 | spi-tx-bus-width = <1>; | |
51 | spi-rx-bus-width = <4>; | |
52 | spi-max-frequency = <108000000>; | |
53 | }; | |
54 | }; | |
55 | ||
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56 | &uart0 { |
57 | status = "okay"; | |
58 | }; |