[linux-2.6-block.git] / arch / arm64 / boot / dts / xilinx / zynqmp-zcu111-revA.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP ZCU111
 *
 * (C) Copyright 2017 - 2022, Xilinx, Inc.
 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

/dts-v1/;

#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>

/ {
	model = "ZynqMP ZCU111 RevA";
	compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";

	aliases {
		ethernet0 = &gem3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		mmc0 = &sdhci1;
		nvmem0 = &eeprom;
		rtc0 = &rtc;
		serial0 = &uart0;
		serial1 = &dcc;
		spi0 = &qspi;
		usb0 = &usb0;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
		/* Another 4GB connected to PL */
	};

	gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		switch-19 {
			label = "sw19";
			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_DOWN>;
			wakeup-source;
			autorepeat;
		};
	};

	leds {
		compatible = "gpio-leds";
		heartbeat-led {
			label = "heartbeat";
			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
		};
	};

	ina226-u67 {
		compatible = "iio-hwmon";
		io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
	};
	ina226-u59 {
		compatible = "iio-hwmon";
		io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
	};
	ina226-u61 {
		compatible = "iio-hwmon";
		io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
	};
	ina226-u60 {
		compatible = "iio-hwmon";
		io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
	};
	ina226-u64 {
		compatible = "iio-hwmon";
		io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
	};
	ina226-u69 {
		compatible = "iio-hwmon";
		io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
	};
	ina226-u66 {
		compatible = "iio-hwmon";
		io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
	};
	ina226-u65 {
		compatible = "iio-hwmon";
		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
	};
	ina226-u63 {
		compatible = "iio-hwmon";
		io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
	};
	ina226-u3 {
		compatible = "iio-hwmon";
		io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
	};
	ina226-u71 {
		compatible = "iio-hwmon";
		io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
	};
	ina226-u77 {
		compatible = "iio-hwmon";
		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
	};
	ina226-u73 {
		compatible = "iio-hwmon";
		io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
	};
	ina226-u79 {
		compatible = "iio-hwmon";
		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
	};

	/* 48MHz reference crystal */
	ref48: ref48M {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <48000000>;
	};
};

&dcc {
	status = "okay";
};

&fpd_dma_chan1 {
	status = "okay";
};

&fpd_dma_chan2 {
	status = "okay";
};

&fpd_dma_chan3 {
	status = "okay";
};

&fpd_dma_chan4 {
	status = "okay";
};

&fpd_dma_chan5 {
	status = "okay";
};

&fpd_dma_chan6 {
	status = "okay";
};

&fpd_dma_chan7 {
	status = "okay";
};

&fpd_dma_chan8 {
	status = "okay";
};

&gem3 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "rgmii-id";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gem3_default>;
	mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@c {
			#phy-cells = <1>;
			compatible = "ethernet-phy-id2000.a231";
			reg = <0xc>;
			ti,rx-internal-delay = <0x8>;
			ti,tx-internal-delay = <0xa>;
			ti,fifo-depth = <0x1>;
			ti,dp83867-rxctrl-strap-quirk;
			reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
		};
	};
};

&gpio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio_default>;
};

&gpu {
	status = "okay";
};

&i2c0 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c0_default>;
	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;

	tca6416_u22: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller; /* interrupt not connected */
		#gpio-cells = <2>;
		/*
		 * IRQ not connected
		 * Lines:
		 * 0 - MAX6643_OT_B
		 * 1 - MAX6643_FANFAIL_B
		 * 2 - MIO26_PMU_INPUT_LS
		 * 4 - SFP_SI5382_INT_ALM
		 * 5 - IIC_MUX_RESET_B
		 * 6 - GEM3_EXP_RESET_B
		 * 10 - FMCP_HSPC_PRSNT_M2C_B
		 * 11 - CLK_SPI_MUX_SEL0
		 * 12 - CLK_SPI_MUX_SEL1
		 * 16 - IRPS5401_ALERT_B
		 * 17 - INA226_PMBUS_ALERT
		 * 3, 7, 13-15 - not connected
		 */
	};

	i2c-mux@75 { /* u23 */
		compatible = "nxp,pca9544";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x75>;
		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* PS_PMBUS */
			/* PMBUS_ALERT done via pca9544 */
			u67: ina226@40 { /* u67 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u67";
				reg = <0x40>;
				shunt-resistor = <2000>;
			};
			u59: ina226@41 { /* u59 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u59";
				reg = <0x41>;
				shunt-resistor = <5000>;
			};
			u61: ina226@42 { /* u61 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u61";
				reg = <0x42>;
				shunt-resistor = <5000>;
			};
			u60: ina226@43 { /* u60 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u60";
				reg = <0x43>;
				shunt-resistor = <5000>;
			};
			u64: ina226@45 { /* u64 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u64";
				reg = <0x45>;
				shunt-resistor = <5000>;
			};
			u69: ina226@46 { /* u69 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u69";
				reg = <0x46>;
				shunt-resistor = <2000>;
			};
			u66: ina226@47 { /* u66 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u66";
				reg = <0x47>;
				shunt-resistor = <5000>;
			};
			u65: ina226@48 { /* u65 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u65";
				reg = <0x48>;
				shunt-resistor = <5000>;
			};
			u63: ina226@49 { /* u63 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u63";
				reg = <0x49>;
				shunt-resistor = <5000>;
			};
			u3: ina226@4a { /* u3 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u3";
				reg = <0x4a>;
				shunt-resistor = <5000>;
			};
			u71: ina226@4b { /* u71 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u71";
				reg = <0x4b>;
				shunt-resistor = <5000>;
			};
			u77: ina226@4c { /* u77 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u77";
				reg = <0x4c>;
				shunt-resistor = <5000>;
			};
			u73: ina226@4d { /* u73 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u73";
				reg = <0x4d>;
				shunt-resistor = <5000>;
			};
			u79: ina226@4e { /* u79 */
				compatible = "ti,ina226";
				#io-channel-cells = <1>;
				label = "ina226-u79";
				reg = <0x4e>;
				shunt-resistor = <5000>;
			};
		};
		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* NC */
		};
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
				compatible = "infineon,irps5401";
				reg = <0x43>;
			};
			irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
				compatible = "infineon,irps5401";
				reg = <0x44>;
			};
			irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
				compatible = "infineon,irps5401";
				reg = <0x45>;
			};
			/* u68 IR38064 +0 */
			/* u70 IR38060 +1 */
			/* u74 IR38060 +2 */
			/* u75 IR38060 +6 */
			/* J19 header too */

		};
		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			/* SYSMON */
		};
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c1_default>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;

	i2c-mux@74 { /* u26 */
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;
		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/*
			 * IIC_EEPROM 1kB memory which uses 256B blocks
			 * where every block has different address.
			 *    0 - 256B address 0x54
			 * 256B - 512B address 0x55
			 * 512B - 768B address 0x56
			 * 768B - 1024B address 0x57
			 */
			eeprom: eeprom@54 { /* u88 */
				compatible = "atmel,24c08";
				reg = <0x54>;
			};
		};
		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			si5341: clock-generator@36 { /* SI5341 - u46 */
				compatible = "silabs,si5341";
				reg = <0x36>;
				#clock-cells = <2>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&ref48>;
				clock-names = "xtal";
				clock-output-names = "si5341";

				si5341_0: out@0 {
					/* refclk0 for PS-GT, used for DP */
					reg = <0>;
					always-on;
				};
				si5341_2: out@2 {
					/* refclk2 for PS-GT, used for USB3 */
					reg = <2>;
					always-on;
				};
				si5341_3: out@3 {
					/* refclk3 for PS-GT, used for SATA */
					reg = <3>;
					always-on;
				};
				si5341_5: out@5 {
					/* refclk5 PL CLK100 */
					reg = <5>;
					always-on;
				};
				si5341_6: out@6 {
					/* refclk6 PL CLK125 */
					reg = <6>;
					always-on;
				};
				si5341_9: out@9 {
					/* refclk9 used for PS_REF_CLK 33.3 MHz */
					reg = <9>;
					always-on;
				};
			};
		};
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			si570_1: clock-generator@5d { /* USER SI570 - u47 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>;
				temperature-stability = <50>;
				factory-fout = <300000000>;
				clock-frequency = <300000000>;
				clock-output-names = "si570_user";
			};
		};
		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
				#clock-cells = <0>;
				compatible = "silabs,si570";
				reg = <0x5d>;
				temperature-stability = <50>;
				factory-fout = <156250000>;
				clock-frequency = <156250000>;
				clock-output-names = "si570_mgt";
			};
		};
		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			/* SI5382 - u48 */
		};
		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
				sc18is603@2f { /* sc18is602 - u93 */
					compatible = "nxp,sc18is603";
					reg = <0x2f>;
					/* 4 gpios for CS not handled by driver */
					/*
					 * USB2ANY cable or
					 * LMK04208 - u90 or
					 * LMX2594 - u102 or
					 * LMX2594 - u103 or
					 * LMX2594 - u104
					 */
				};
		};
		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			/* FMC connector */
		};
		/* 7 NC */
	};

	i2c-mux@75 {
		compatible = "nxp,pca9548"; /* u27 */
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x75>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* FMCP_HSPC_IIC */
		};
		i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* NC */
		};
		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			/* SYSMON */
		};
		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			/* DDR4 SODIMM */
		};
		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			/* SFP3 */
		};
		i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;
			/* SFP2 */
		};
		i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <6>;
			/* SFP1 */
		};
		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
			/* SFP0 */
		};
	};
};

&pinctrl0 {
	status = "okay";
	pinctrl_i2c0_default: i2c0-default {
		mux {
			groups = "i2c0_3_grp";
			function = "i2c0";
		};

		conf {
			groups = "i2c0_3_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c0_gpio: i2c0-gpio {
		mux {
			groups = "gpio0_14_grp", "gpio0_15_grp";
			function = "gpio0";
		};

		conf {
			groups = "gpio0_14_grp", "gpio0_15_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c1_default: i2c1-default {
		mux {
			groups = "i2c1_4_grp";
			function = "i2c1";
		};

		conf {
			groups = "i2c1_4_grp";
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_i2c1_gpio: i2c1-gpio {
		mux {
			groups = "gpio0_16_grp", "gpio0_17_grp";
			function = "gpio0";
		};

		conf {
			groups = "gpio0_16_grp", "gpio0_17_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_uart0_default: uart0-default {
		mux {
			groups = "uart0_4_grp";
			function = "uart0";
		};

		conf {
			groups = "uart0_4_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO18";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO19";
			bias-disable;
		};
	};

	pinctrl_usb0_default: usb0-default {
		mux {
			groups = "usb0_0_grp";
			function = "usb0";
		};

		conf {
			groups = "usb0_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO52", "MIO53", "MIO55";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
			       "MIO60", "MIO61", "MIO62", "MIO63";
			bias-disable;
		};
	};

	pinctrl_gem3_default: gem3-default {
		mux {
			function = "ethernet3";
			groups = "ethernet3_0_grp";
		};

		conf {
			groups = "ethernet3_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		conf-rx {
			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
									"MIO75";
			bias-high-impedance;
			low-power-disable;
		};

		conf-tx {
			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
									"MIO69";
			bias-disable;
			low-power-enable;
		};

		mux-mdio {
			function = "mdio3";
			groups = "mdio3_0_grp";
		};

		conf-mdio {
			groups = "mdio3_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
			bias-disable;
		};
	};

	pinctrl_sdhci1_default: sdhci1-default {
		mux {
			groups = "sdio1_0_grp";
			function = "sdio1";
		};

		conf {
			groups = "sdio1_0_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
			bias-disable;
		};

		mux-cd {
			groups = "sdio1_cd_0_grp";
			function = "sdio1_cd";
		};

		conf-cd {
			groups = "sdio1_cd_0_grp";
			bias-high-impedance;
			bias-pull-up;
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};
	};

	pinctrl_gpio_default: gpio-default {
		mux {
			function = "gpio0";
			groups = "gpio0_22_grp", "gpio0_23_grp";
		};

		conf {
			groups = "gpio0_22_grp", "gpio0_23_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		mux-msp {
			function = "gpio0";
			groups = "gpio0_13_grp", "gpio0_38_grp";
		};

		conf-msp {
			groups = "gpio0_13_grp", "gpio0_38_grp";
			slew-rate = <SLEW_RATE_SLOW>;
			power-source = <IO_STANDARD_LVCMOS18>;
		};

		conf-pull-up {
			pins = "MIO22";
			bias-pull-up;
		};

		conf-pull-none {
			pins = "MIO13", "MIO23", "MIO38";
			bias-disable;
		};
	};
};

&psgtr {
	status = "okay";
	/* nc, dp, usb3, sata */
	clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
	clock-names = "ref1", "ref2", "ref3";
};

&qspi {
	status = "okay";
	flash@0 {
		compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
		spi-max-frequency = <108000000>; /* Based on DC1 spec */
	};
};

&rtc {
	status = "okay";
};

&sata {
	status = "okay";
	/* SATA OOB timing settings */
	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	phy-names = "sata-phy";
	phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};

/* SD1 with level shifter */
&sdhci1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdhci1_default>;
	disable-wp;
	/*
	 * This property should be removed for supporting UHS mode
	 */
	no-1-8-v;
	xlnx,mio-bank = <1>;
};

&uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0_default>;
};

/* ULPI SMSC USB3320 */
&usb0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0_default>;
	phy-names = "usb3-phy";
	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};

&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	snps,usb3_lpm_capable;
	maximum-speed = "super-speed";
};

&zynqmp_dpdma {
	status = "okay";
};

&zynqmp_dpsub {
	status = "okay";
	phy-names = "dp-phy0", "dp-phy1";
	phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
	       <&psgtr 0 PHY_TYPE_DP 1 1>;
};
Commit	Line	Data
b8aee022 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* dts file for Xilinx ZynqMP ZCU111
	4	*
c720a1f5 MS	5	* (C) Copyright 2017 - 2022, Xilinx, Inc.
c720a1f5 MS	6	* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
b8aee022	7	*
4e4ddd3d	8	* Michal Simek <michal.simek@amd.com>
b8aee022 MS	9	*/
	10
	11	/dts-v1/;
	12
	13	#include "zynqmp.dtsi"
9c8a47b4	14	#include "zynqmp-clk-ccf.dtsi"
b8aee022 MS	15	#include <dt-bindings/input/input.h>
b8aee022 MS	16	#include <dt-bindings/gpio/gpio.h>
c821045f	17	#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
51733f16	18	#include <dt-bindings/phy/phy.h>
b8aee022 MS	19
	20	/ {
	21	model = "ZynqMP ZCU111 RevA";
	22	compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
	23
	24	aliases {
	25	ethernet0 = &gem3;
	26	i2c0 = &i2c0;
	27	i2c1 = &i2c1;
	28	mmc0 = &sdhci1;
d65ec93f	29	nvmem0 = &eeprom;
b8aee022 MS	30	rtc0 = &rtc;
	31	serial0 = &uart0;
	32	serial1 = &dcc;
56e54601	33	spi0 = &qspi;
b61c4ff9	34	usb0 = &usb0;
b8aee022 MS	35	};
	36
	37	chosen {
	38	bootargs = "earlycon";
	39	stdout-path = "serial0:115200n8";
	40	};
	41
	42	memory@0 {
	43	device_type = "memory";
	44	reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
	45	/* Another 4GB connected to PL */
	46	};
	47
	48	gpio-keys {
	49	compatible = "gpio-keys";
b8aee022	50	autorepeat;
228e8a88	51	switch-19 {
b8aee022 MS	52	label = "sw19";
	53	gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
	54	linux,code = <KEY_DOWN>;
1696acf4	55	wakeup-source;
b8aee022 MS	56	autorepeat;
	57	};
	58	};
	59
	60	leds {
	61	compatible = "gpio-leds";
d1d4445a	62	heartbeat-led {
b8aee022 MS	63	label = "heartbeat";
	64	gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
	65	linux,default-trigger = "heartbeat";
	66	};
	67	};
2fe83978 MS	68
	69	ina226-u67 {
	70	compatible = "iio-hwmon";
	71	io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
	72	};
	73	ina226-u59 {
	74	compatible = "iio-hwmon";
	75	io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
	76	};
	77	ina226-u61 {
	78	compatible = "iio-hwmon";
	79	io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
	80	};
	81	ina226-u60 {
	82	compatible = "iio-hwmon";
	83	io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
	84	};
	85	ina226-u64 {
	86	compatible = "iio-hwmon";
	87	io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
	88	};
	89	ina226-u69 {
	90	compatible = "iio-hwmon";
	91	io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
	92	};
	93	ina226-u66 {
	94	compatible = "iio-hwmon";
	95	io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
	96	};
	97	ina226-u65 {
	98	compatible = "iio-hwmon";
	99	io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
	100	};
	101	ina226-u63 {
	102	compatible = "iio-hwmon";
	103	io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
	104	};
	105	ina226-u3 {
	106	compatible = "iio-hwmon";
	107	io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
	108	};
	109	ina226-u71 {
	110	compatible = "iio-hwmon";
	111	io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
	112	};
	113	ina226-u77 {
	114	compatible = "iio-hwmon";
	115	io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
	116	};
	117	ina226-u73 {
	118	compatible = "iio-hwmon";
	119	io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
	120	};
	121	ina226-u79 {
	122	compatible = "iio-hwmon";
	123	io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
	124	};
928a5747 MS	125
	126	/* 48MHz reference crystal */
	127	ref48: ref48M {
	128	compatible = "fixed-clock";
	129	#clock-cells = <0>;
	130	clock-frequency = <48000000>;
	131	};
b8aee022 MS	132	};
	133
	134	&dcc {
	135	status = "okay";
	136	};
	137
	138	&fpd_dma_chan1 {
	139	status = "okay";
	140	};
	141
	142	&fpd_dma_chan2 {
	143	status = "okay";
	144	};
	145
	146	&fpd_dma_chan3 {
	147	status = "okay";
	148	};
	149
	150	&fpd_dma_chan4 {
	151	status = "okay";
	152	};
	153
	154	&fpd_dma_chan5 {
	155	status = "okay";
	156	};
	157
	158	&fpd_dma_chan6 {
	159	status = "okay";
	160	};
	161
	162	&fpd_dma_chan7 {
	163	status = "okay";
	164	};
	165
	166	&fpd_dma_chan8 {
	167	status = "okay";
	168	};
	169
	170	&gem3 {
	171	status = "okay";
	172	phy-handle = <&phy0>;
	173	phy-mode = "rgmii-id";
c821045f MS	174	pinctrl-names = "default";
c821045f MS	175	pinctrl-0 = <&pinctrl_gem3_default>;
c720a1f5 MS	176	mdio: mdio {
	177	#address-cells = <1>;
	178	#size-cells = <0>;
	179	phy0: ethernet-phy@c {
	180	#phy-cells = <1>;
	181	compatible = "ethernet-phy-id2000.a231";
	182	reg = <0xc>;
	183	ti,rx-internal-delay = <0x8>;
	184	ti,tx-internal-delay = <0xa>;
	185	ti,fifo-depth = <0x1>;
	186	ti,dp83867-rxctrl-strap-quirk;
	187	reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>;
	188	};
b8aee022 MS	189	};
	190	};
	191
	192	&gpio {
	193	status = "okay";
c821045f MS	194	pinctrl-names = "default";
c821045f MS	195	pinctrl-0 = <&pinctrl_gpio_default>;
b8aee022 MS	196	};
b8aee022 MS	197
37e78949 PG	198	&gpu {
	199	status = "okay";
	200	};
	201
b8aee022 MS	202	&i2c0 {
	203	status = "okay";
	204	clock-frequency = <400000>;
c821045f MS	205	pinctrl-names = "default", "gpio";
	206	pinctrl-0 = <&pinctrl_i2c0_default>;
	207	pinctrl-1 = <&pinctrl_i2c0_gpio>;
	208	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
	209	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
b8aee022 MS	210
	211	tca6416_u22: gpio@20 {
	212	compatible = "ti,tca6416";
	213	reg = <0x20>;
	214	gpio-controller; /* interrupt not connected */
	215	#gpio-cells = <2>;
	216	/*
	217	* IRQ not connected
	218	* Lines:
	219	* 0 - MAX6643_OT_B
	220	* 1 - MAX6643_FANFAIL_B
	221	* 2 - MIO26_PMU_INPUT_LS
	222	* 4 - SFP_SI5382_INT_ALM
	223	* 5 - IIC_MUX_RESET_B
	224	* 6 - GEM3_EXP_RESET_B
	225	* 10 - FMCP_HSPC_PRSNT_M2C_B
	226	* 11 - CLK_SPI_MUX_SEL0
	227	* 12 - CLK_SPI_MUX_SEL1
	228	* 16 - IRPS5401_ALERT_B
	229	* 17 - INA226_PMBUS_ALERT
	230	* 3, 7, 13-15 - not connected
	231	*/
	232	};
	233
	234	i2c-mux@75 { /* u23 */
	235	compatible = "nxp,pca9544";
	236	#address-cells = <1>;
	237	#size-cells = <0>;
	238	reg = <0x75>;
	239	i2c@0 {
	240	#address-cells = <1>;
	241	#size-cells = <0>;
	242	reg = <0>;
	243	/* PS_PMBUS */
	244	/* PMBUS_ALERT done via pca9544 */
2fe83978	245	u67: ina226@40 { /* u67 */
b8aee022	246	compatible = "ti,ina226";
2fe83978	247	#io-channel-cells = <1>;
9529be14	248	label = "ina226-u67";
b8aee022 MS	249	reg = <0x40>;
	250	shunt-resistor = <2000>;
	251	};
2fe83978	252	u59: ina226@41 { /* u59 */
b8aee022	253	compatible = "ti,ina226";
2fe83978	254	#io-channel-cells = <1>;
9529be14	255	label = "ina226-u59";
b8aee022 MS	256	reg = <0x41>;
	257	shunt-resistor = <5000>;
	258	};
2fe83978	259	u61: ina226@42 { /* u61 */
b8aee022	260	compatible = "ti,ina226";
2fe83978	261	#io-channel-cells = <1>;
9529be14	262	label = "ina226-u61";
b8aee022 MS	263	reg = <0x42>;
	264	shunt-resistor = <5000>;
	265	};
2fe83978	266	u60: ina226@43 { /* u60 */
b8aee022	267	compatible = "ti,ina226";
2fe83978	268	#io-channel-cells = <1>;
9529be14	269	label = "ina226-u60";
b8aee022 MS	270	reg = <0x43>;
	271	shunt-resistor = <5000>;
	272	};
2fe83978	273	u64: ina226@45 { /* u64 */
b8aee022	274	compatible = "ti,ina226";
2fe83978	275	#io-channel-cells = <1>;
9529be14	276	label = "ina226-u64";
b8aee022 MS	277	reg = <0x45>;
	278	shunt-resistor = <5000>;
	279	};
2fe83978	280	u69: ina226@46 { /* u69 */
b8aee022	281	compatible = "ti,ina226";
2fe83978	282	#io-channel-cells = <1>;
9529be14	283	label = "ina226-u69";
b8aee022 MS	284	reg = <0x46>;
	285	shunt-resistor = <2000>;
	286	};
2fe83978	287	u66: ina226@47 { /* u66 */
b8aee022	288	compatible = "ti,ina226";
2fe83978	289	#io-channel-cells = <1>;
9529be14	290	label = "ina226-u66";
b8aee022 MS	291	reg = <0x47>;
	292	shunt-resistor = <5000>;
	293	};
2fe83978	294	u65: ina226@48 { /* u65 */
b8aee022	295	compatible = "ti,ina226";
2fe83978	296	#io-channel-cells = <1>;
9529be14	297	label = "ina226-u65";
b8aee022 MS	298	reg = <0x48>;
	299	shunt-resistor = <5000>;
	300	};
2fe83978	301	u63: ina226@49 { /* u63 */
b8aee022	302	compatible = "ti,ina226";
2fe83978	303	#io-channel-cells = <1>;
9529be14	304	label = "ina226-u63";
b8aee022 MS	305	reg = <0x49>;
	306	shunt-resistor = <5000>;
	307	};
2fe83978	308	u3: ina226@4a { /* u3 */
b8aee022	309	compatible = "ti,ina226";
2fe83978	310	#io-channel-cells = <1>;
9529be14	311	label = "ina226-u3";
b8aee022 MS	312	reg = <0x4a>;
	313	shunt-resistor = <5000>;
	314	};
2fe83978	315	u71: ina226@4b { /* u71 */
b8aee022	316	compatible = "ti,ina226";
2fe83978	317	#io-channel-cells = <1>;
9529be14	318	label = "ina226-u71";
b8aee022 MS	319	reg = <0x4b>;
	320	shunt-resistor = <5000>;
	321	};
2fe83978	322	u77: ina226@4c { /* u77 */
b8aee022	323	compatible = "ti,ina226";
2fe83978	324	#io-channel-cells = <1>;
9529be14	325	label = "ina226-u77";
b8aee022 MS	326	reg = <0x4c>;
	327	shunt-resistor = <5000>;
	328	};
2fe83978	329	u73: ina226@4d { /* u73 */
b8aee022	330	compatible = "ti,ina226";
2fe83978	331	#io-channel-cells = <1>;
9529be14	332	label = "ina226-u73";
b8aee022 MS	333	reg = <0x4d>;
	334	shunt-resistor = <5000>;
	335	};
2fe83978	336	u79: ina226@4e { /* u79 */
b8aee022	337	compatible = "ti,ina226";
2fe83978	338	#io-channel-cells = <1>;
9529be14	339	label = "ina226-u79";
b8aee022 MS	340	reg = <0x4e>;
	341	shunt-resistor = <5000>;
	342	};
	343	};
	344	i2c@1 {
	345	#address-cells = <1>;
	346	#size-cells = <0>;
	347	reg = <1>;
	348	/* NC */
	349	};
	350	i2c@2 {
	351	#address-cells = <1>;
	352	#size-cells = <0>;
	353	reg = <2>;
d8e4bc0b MS	354	irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
d8e4bc0b MS	355	compatible = "infineon,irps5401";
b8aee022 MS	356	reg = <0x43>;
b8aee022 MS	357	};
d8e4bc0b MS	358	irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
d8e4bc0b MS	359	compatible = "infineon,irps5401";
b8aee022 MS	360	reg = <0x44>;
b8aee022 MS	361	};
d8e4bc0b MS	362	irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
d8e4bc0b MS	363	compatible = "infineon,irps5401";
b8aee022 MS	364	reg = <0x45>;
	365	};
	366	/* u68 IR38064 +0 */
	367	/* u70 IR38060 +1 */
	368	/* u74 IR38060 +2 */
	369	/* u75 IR38060 +6 */
	370	/* J19 header too */
	371
	372	};
	373	i2c@3 {
	374	#address-cells = <1>;
	375	#size-cells = <0>;
	376	reg = <3>;
	377	/* SYSMON */
	378	};
	379	};
	380	};
	381
	382	&i2c1 {
	383	status = "okay";
	384	clock-frequency = <400000>;
c821045f MS	385	pinctrl-names = "default", "gpio";
	386	pinctrl-0 = <&pinctrl_i2c1_default>;
	387	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	388	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
	389	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
b8aee022 MS	390
	391	i2c-mux@74 { /* u26 */
	392	compatible = "nxp,pca9548";
	393	#address-cells = <1>;
	394	#size-cells = <0>;
	395	reg = <0x74>;
	396	i2c@0 {
	397	#address-cells = <1>;
	398	#size-cells = <0>;
	399	reg = <0>;
	400	/*
	401	* IIC_EEPROM 1kB memory which uses 256B blocks
	402	* where every block has different address.
	403	* 0 - 256B address 0x54
	404	* 256B - 512B address 0x55
	405	* 512B - 768B address 0x56
	406	* 768B - 1024B address 0x57
	407	*/
	408	eeprom: eeprom@54 { /* u88 */
	409	compatible = "atmel,24c08";
	410	reg = <0x54>;
	411	};
	412	};
	413	i2c@1 {
	414	#address-cells = <1>;
	415	#size-cells = <0>;
	416	reg = <1>;
	417	si5341: clock-generator@36 { /* SI5341 - u46 */
928a5747	418	compatible = "silabs,si5341";
b8aee022	419	reg = <0x36>;
928a5747 MS	420	#clock-cells = <2>;
	421	#address-cells = <1>;
	422	#size-cells = <0>;
	423	clocks = <&ref48>;
	424	clock-names = "xtal";
	425	clock-output-names = "si5341";
b8aee022	426
928a5747 MS	427	si5341_0: out@0 {
	428	/* refclk0 for PS-GT, used for DP */
	429	reg = <0>;
	430	always-on;
	431	};
	432	si5341_2: out@2 {
	433	/* refclk2 for PS-GT, used for USB3 */
	434	reg = <2>;
	435	always-on;
	436	};
	437	si5341_3: out@3 {
	438	/* refclk3 for PS-GT, used for SATA */
	439	reg = <3>;
	440	always-on;
	441	};
	442	si5341_5: out@5 {
	443	/* refclk5 PL CLK100 */
	444	reg = <5>;
	445	always-on;
	446	};
	447	si5341_6: out@6 {
	448	/* refclk6 PL CLK125 */
	449	reg = <6>;
	450	always-on;
	451	};
	452	si5341_9: out@9 {
	453	/* refclk9 used for PS_REF_CLK 33.3 MHz */
	454	reg = <9>;
	455	always-on;
	456	};
	457	};
b8aee022 MS	458	};
	459	i2c@2 {
	460	#address-cells = <1>;
	461	#size-cells = <0>;
	462	reg = <2>;
	463	si570_1: clock-generator@5d { /* USER SI570 - u47 */
	464	#clock-cells = <0>;
	465	compatible = "silabs,si570";
	466	reg = <0x5d>;
	467	temperature-stability = <50>;
	468	factory-fout = <300000000>;
	469	clock-frequency = <300000000>;
48b44b90	470	clock-output-names = "si570_user";
b8aee022 MS	471	};
	472	};
	473	i2c@3 {
	474	#address-cells = <1>;
	475	#size-cells = <0>;
	476	reg = <3>;
	477	si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
	478	#clock-cells = <0>;
	479	compatible = "silabs,si570";
	480	reg = <0x5d>;
	481	temperature-stability = <50>;
	482	factory-fout = <156250000>;
25ef9bb6	483	clock-frequency = <156250000>;
48b44b90	484	clock-output-names = "si570_mgt";
b8aee022 MS	485	};
	486	};
	487	i2c@4 {
	488	#address-cells = <1>;
	489	#size-cells = <0>;
	490	reg = <4>;
31533c21	491	/* SI5382 - u48 */
b8aee022 MS	492	};
	493	i2c@5 {
	494	#address-cells = <1>;
	495	#size-cells = <0>;
	496	reg = <5>;
	497	sc18is603@2f { /* sc18is602 - u93 */
	498	compatible = "nxp,sc18is603";
	499	reg = <0x2f>;
	500	/* 4 gpios for CS not handled by driver */
	501	/*
	502	* USB2ANY cable or
	503	* LMK04208 - u90 or
	504	* LMX2594 - u102 or
	505	* LMX2594 - u103 or
	506	* LMX2594 - u104
	507	*/
	508	};
	509	};
	510	i2c@6 {
	511	#address-cells = <1>;
	512	#size-cells = <0>;
	513	reg = <6>;
	514	/* FMC connector */
	515	};
	516	/* 7 NC */
	517	};
	518
	519	i2c-mux@75 {
	520	compatible = "nxp,pca9548"; /* u27 */
	521	#address-cells = <1>;
	522	#size-cells = <0>;
	523	reg = <0x75>;
	524
	525	i2c@0 {
	526	#address-cells = <1>;
	527	#size-cells = <0>;
	528	reg = <0>;
	529	/* FMCP_HSPC_IIC */
	530	};
	531	i2c@1 {
	532	#address-cells = <1>;
	533	#size-cells = <0>;
	534	reg = <1>;
	535	/* NC */
	536	};
	537	i2c@2 {
	538	#address-cells = <1>;
	539	#size-cells = <0>;
	540	reg = <2>;
	541	/* SYSMON */
	542	};
	543	i2c@3 {
	544	#address-cells = <1>;
	545	#size-cells = <0>;
	546	reg = <3>;
	547	/* DDR4 SODIMM */
	548	};
	549	i2c@4 {
	550	#address-cells = <1>;
	551	#size-cells = <0>;
	552	reg = <4>;
	553	/* SFP3 */
	554	};
	555	i2c@5 {
556	#address-cells = <1>;
557	#size-cells = <0>;
558	reg = <5>;
559	/* SFP2 */
560	};
561	i2c@6 {
562	#address-cells = <1>;
563	#size-cells = <0>;
564	reg = <6>;
565	/* SFP1 */
566	};
567	i2c@7 {
568	#address-cells = <1>;
569	#size-cells = <0>;
570	reg = <7>;
571	/* SFP0 */
572	};
573	};
574	};
575
c821045f MS	576	&pinctrl0 {
	577	status = "okay";
	578	pinctrl_i2c0_default: i2c0-default {
	579	mux {
	580	groups = "i2c0_3_grp";
	581	function = "i2c0";
	582	};
	583
	584	conf {
	585	groups = "i2c0_3_grp";
	586	bias-pull-up;
	587	slew-rate = <SLEW_RATE_SLOW>;
	588	power-source = <IO_STANDARD_LVCMOS18>;
	589	};
	590	};
	591
	592	pinctrl_i2c0_gpio: i2c0-gpio {
	593	mux {
	594	groups = "gpio0_14_grp", "gpio0_15_grp";
	595	function = "gpio0";
	596	};
	597
	598	conf {
	599	groups = "gpio0_14_grp", "gpio0_15_grp";
	600	slew-rate = <SLEW_RATE_SLOW>;
	601	power-source = <IO_STANDARD_LVCMOS18>;
	602	};
	603	};
	604
	605	pinctrl_i2c1_default: i2c1-default {
	606	mux {
	607	groups = "i2c1_4_grp";
	608	function = "i2c1";
	609	};
	610
	611	conf {
	612	groups = "i2c1_4_grp";
	613	bias-pull-up;
	614	slew-rate = <SLEW_RATE_SLOW>;
	615	power-source = <IO_STANDARD_LVCMOS18>;
	616	};
	617	};
	618
	619	pinctrl_i2c1_gpio: i2c1-gpio {
	620	mux {
	621	groups = "gpio0_16_grp", "gpio0_17_grp";
	622	function = "gpio0";
	623	};
	624
	625	conf {
	626	groups = "gpio0_16_grp", "gpio0_17_grp";
	627	slew-rate = <SLEW_RATE_SLOW>;
	628	power-source = <IO_STANDARD_LVCMOS18>;
	629	};
	630	};
	631
	632	pinctrl_uart0_default: uart0-default {
	633	mux {
	634	groups = "uart0_4_grp";
	635	function = "uart0";
	636	};
	637
	638	conf {
	639	groups = "uart0_4_grp";
640	slew-rate = <SLEW_RATE_SLOW>;
641	power-source = <IO_STANDARD_LVCMOS18>;
642	};
643
644	conf-rx {
645	pins = "MIO18";
646	bias-high-impedance;
647	};
648
649	conf-tx {
650	pins = "MIO19";
651	bias-disable;
652	};
653	};
654
655	pinctrl_usb0_default: usb0-default {
656	mux {
657	groups = "usb0_0_grp";
658	function = "usb0";
659	};
660
661	conf {
662	groups = "usb0_0_grp";
663	slew-rate = <SLEW_RATE_SLOW>;
664	power-source = <IO_STANDARD_LVCMOS18>;
665	};
666
667	conf-rx {
668	pins = "MIO52", "MIO53", "MIO55";
669	bias-high-impedance;
670	};
671
672	conf-tx {
673	pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
674	"MIO60", "MIO61", "MIO62", "MIO63";
675	bias-disable;
676	};
677	};
678
679	pinctrl_gem3_default: gem3-default {
680	mux {
681	function = "ethernet3";
682	groups = "ethernet3_0_grp";
683	};
684
685	conf {
686	groups = "ethernet3_0_grp";
687	slew-rate = <SLEW_RATE_SLOW>;
688	power-source = <IO_STANDARD_LVCMOS18>;
689	};
690
691	conf-rx {
692	pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
693	"MIO75";
694	bias-high-impedance;
695	low-power-disable;
696	};
697
698	conf-tx {
699	pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
700	"MIO69";
701	bias-disable;
702	low-power-enable;
703	};
704
705	mux-mdio {
706	function = "mdio3";
707	groups = "mdio3_0_grp";
708	};
709
710	conf-mdio {
711	groups = "mdio3_0_grp";
712	slew-rate = <SLEW_RATE_SLOW>;
713	power-source = <IO_STANDARD_LVCMOS18>;
714	bias-disable;
715	};
716	};
717
718	pinctrl_sdhci1_default: sdhci1-default {
719	mux {
720	groups = "sdio1_0_grp";
721	function = "sdio1";
722	};
723
724	conf {
725	groups = "sdio1_0_grp";
726	slew-rate = <SLEW_RATE_SLOW>;
727	power-source = <IO_STANDARD_LVCMOS18>;
728	bias-disable;
729	};
730
731	mux-cd {
732	groups = "sdio1_cd_0_grp";
733	function = "sdio1_cd";
734	};
735
736	conf-cd {
737	groups = "sdio1_cd_0_grp";
738	bias-high-impedance;
739	bias-pull-up;
740	slew-rate = <SLEW_RATE_SLOW>;
741	power-source = <IO_STANDARD_LVCMOS18>;
742	};
743	};
744
745	pinctrl_gpio_default: gpio-default {
746	mux {
747	function = "gpio0";
748	groups = "gpio0_22_grp", "gpio0_23_grp";
749	};
750
751	conf {
752	groups = "gpio0_22_grp", "gpio0_23_grp";
753	slew-rate = <SLEW_RATE_SLOW>;
754	power-source = <IO_STANDARD_LVCMOS18>;
755	};
756
757	mux-msp {
758	function = "gpio0";
759	groups = "gpio0_13_grp", "gpio0_38_grp";
760	};
761
762	conf-msp {
763	groups = "gpio0_13_grp", "gpio0_38_grp";
764	slew-rate = <SLEW_RATE_SLOW>;
765	power-source = <IO_STANDARD_LVCMOS18>;
766	};
767
768	conf-pull-up {
769	pins = "MIO22";
770	bias-pull-up;
771	};
772
773	conf-pull-none {
774	pins = "MIO13", "MIO23", "MIO38";
775	bias-disable;
776	};
777	};
778	};
779
51733f16 MS	780	&psgtr {
51733f16 MS	781	status = "okay";
b20c1e4d MS	782	/* nc, dp, usb3, sata */
b20c1e4d MS	783	clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
51733f16 MS	784	clock-names = "ref1", "ref2", "ref3";
	785	};
	786
56e54601 MS	787	&qspi {
56e54601 MS	788	status = "okay";
56e54601	789	flash@0 {
adc40ff8	790	compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
56e54601 MS	791	#address-cells = <1>;
	792	#size-cells = <1>;
	793	reg = <0x0>;
	794	spi-tx-bus-width = <1>;
	795	spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
	796	spi-max-frequency = <108000000>; /* Based on DC1 spec */
	797	};
	798	};
	799
b8aee022 MS	800	&rtc {
	801	status = "okay";
	802	};
	803
	804	&sata {
	805	status = "okay";
	806	/* SATA OOB timing settings */
	807	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
	808	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
	809	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	810	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
	811	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
	812	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
	813	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
	814	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
51733f16	815	phy-names = "sata-phy";
b20c1e4d	816	phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
b8aee022 MS	817	};
	818
	819	/* SD1 with level shifter */
	820	&sdhci1 {
	821	status = "okay";
c821045f MS	822	pinctrl-names = "default";
c821045f MS	823	pinctrl-0 = <&pinctrl_sdhci1_default>;
2f6aa2a5	824	disable-wp;
1d4bd118 MS	825	/*
	826	* This property should be removed for supporting UHS mode
	827	*/
	828	no-1-8-v;
63481699	829	xlnx,mio-bank = <1>;
b8aee022 MS	830	};
	831
	832	&uart0 {
	833	status = "okay";
c821045f MS	834	pinctrl-names = "default";
c821045f MS	835	pinctrl-0 = <&pinctrl_uart0_default>;
b8aee022 MS	836	};
	837
	838	/* ULPI SMSC USB3320 */
	839	&usb0 {
	840	status = "okay";
c821045f MS	841	pinctrl-names = "default";
c821045f MS	842	pinctrl-0 = <&pinctrl_usb0_default>;
8b698f1b MS	843	phy-names = "usb3-phy";
8b698f1b MS	844	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
b61c4ff9 MS	845	};
	846
	847	&dwc3_0 {
	848	status = "okay";
	849	dr_mode = "host";
	850	snps,usb3_lpm_capable;
8b698f1b	851	maximum-speed = "super-speed";
b8aee022	852	};
55563399 LP	853
	854	&zynqmp_dpdma {
	855	status = "okay";
	856	};
	857
	858	&zynqmp_dpsub {
	859	status = "okay";
	860	phy-names = "dp-phy0", "dp-phy1";
	861	phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
	862	<&psgtr 0 PHY_TYPE_DP 1 1>;
	863	};