[linux-2.6-block.git] / arch / arm64 / boot / dts / xilinx / zynqmp-zcu102-revB.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP ZCU102 RevB
 *
 * (C) Copyright 2016 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@amd.com>
 */

#include "zynqmp-zcu102-revA.dts"

/ {
	model = "ZynqMP ZCU102 RevB";
	compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
};

&gem3 {
	phy-handle = <&phyc>;
	phyc: ethernet-phy@c {
		reg = <0xc>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,dp83867-rxctrl-strap-quirk;
		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
	};
	/* Cleanup from RevA */
	/delete-node/ ethernet-phy@21;
};

/* Fix collision with u61 */
&i2c0 {
	i2c-mux@75 {
		i2c@2 {
			max15303@1b { /* u8 */
				compatible = "maxim,max15303";
				reg = <0x1b>;
			};
			/delete-node/ max15303@20;
		};
	};
};
Commit	Line	Data
ef797b53 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* dts file for Xilinx ZynqMP ZCU102 RevB
	4	*
58ccd7e8	5	* (C) Copyright 2016 - 2021, Xilinx, Inc.
ef797b53	6	*
4e4ddd3d	7	* Michal Simek <michal.simek@amd.com>
ef797b53 MS	8	*/
	9
	10	#include "zynqmp-zcu102-revA.dts"
	11
	12	/ {
	13	model = "ZynqMP ZCU102 RevB";
	14	compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
	15	};
	16
	17	&gem3 {
	18	phy-handle = <&phyc>;
13d21eba	19	phyc: ethernet-phy@c {
ef797b53 MS	20	reg = <0xc>;
	21	ti,rx-internal-delay = <0x8>;
	22	ti,tx-internal-delay = <0xa>;
	23	ti,fifo-depth = <0x1>;
78c484a5	24	ti,dp83867-rxctrl-strap-quirk;
58ccd7e8	25	/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
ef797b53 MS	26	};
ef797b53 MS	27	/* Cleanup from RevA */
13d21eba	28	/delete-node/ ethernet-phy@21;
ef797b53 MS	29	};
	30
	31	/* Fix collision with u61 */
	32	&i2c0 {
	33	i2c-mux@75 {
	34	i2c@2 {
	35	max15303@1b { /* u8 */
	36	compatible = "maxim,max15303";
	37	reg = <0x1b>;
	38	};
	39	/delete-node/ max15303@20;
	40	};
	41	};
	42	};