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26a7e06d SH |
1 | /* |
2 | * Device Tree Source for the r8a7795 SoC | |
3 | * | |
4 | * Copyright (C) 2015 Renesas Electronics Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
49af46b4 | 11 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
26a7e06d SH |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
13 | ||
14 | / { | |
15 | compatible = "renesas,r8a7795"; | |
16 | #address-cells = <2>; | |
17 | #size-cells = <2>; | |
18 | ||
32bc0c51 KM |
19 | aliases { |
20 | i2c0 = &i2c0; | |
21 | i2c1 = &i2c1; | |
22 | i2c2 = &i2c2; | |
23 | i2c3 = &i2c3; | |
24 | i2c4 = &i2c4; | |
25 | i2c5 = &i2c5; | |
26 | i2c6 = &i2c6; | |
27 | }; | |
28 | ||
26a7e06d SH |
29 | cpus { |
30 | #address-cells = <1>; | |
31 | #size-cells = <0>; | |
32 | ||
33 | /* 1 core only at this point */ | |
34 | a57_0: cpu@0 { | |
35 | compatible = "arm,cortex-a57", "arm,armv8"; | |
36 | reg = <0x0>; | |
37 | device_type = "cpu"; | |
38 | }; | |
39 | }; | |
40 | ||
41 | extal_clk: extal { | |
42 | compatible = "fixed-clock"; | |
43 | #clock-cells = <0>; | |
44 | /* This value must be overridden by the board */ | |
45 | clock-frequency = <0>; | |
46 | }; | |
47 | ||
48 | extalr_clk: extalr { | |
49 | compatible = "fixed-clock"; | |
50 | #clock-cells = <0>; | |
51 | /* This value must be overridden by the board */ | |
52 | clock-frequency = <0>; | |
53 | }; | |
54 | ||
55 | soc { | |
56 | compatible = "simple-bus"; | |
57 | interrupt-parent = <&gic>; | |
58 | #address-cells = <2>; | |
59 | #size-cells = <2>; | |
60 | ranges; | |
61 | ||
62 | gic: interrupt-controller@0xf1010000 { | |
63 | compatible = "arm,gic-400"; | |
64 | #interrupt-cells = <3>; | |
65 | #address-cells = <0>; | |
66 | interrupt-controller; | |
67 | reg = <0x0 0xf1010000 0 0x1000>, | |
68 | <0x0 0xf1020000 0 0x2000>; | |
69 | interrupts = <GIC_PPI 9 | |
70 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | |
71 | }; | |
72 | ||
7b08623a TK |
73 | gpio0: gpio@e6050000 { |
74 | compatible = "renesas,gpio-r8a7795", | |
75 | "renesas,gpio-rcar"; | |
76 | reg = <0 0xe6050000 0 0x50>; | |
77 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
78 | #gpio-cells = <2>; | |
79 | gpio-controller; | |
80 | gpio-ranges = <&pfc 0 0 16>; | |
81 | #interrupt-cells = <2>; | |
82 | interrupt-controller; | |
83 | clocks = <&cpg CPG_MOD 912>; | |
84 | power-domains = <&cpg>; | |
85 | }; | |
86 | ||
87 | gpio1: gpio@e6051000 { | |
88 | compatible = "renesas,gpio-r8a7795", | |
89 | "renesas,gpio-rcar"; | |
90 | reg = <0 0xe6051000 0 0x50>; | |
91 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
92 | #gpio-cells = <2>; | |
93 | gpio-controller; | |
94 | gpio-ranges = <&pfc 0 32 28>; | |
95 | #interrupt-cells = <2>; | |
96 | interrupt-controller; | |
97 | clocks = <&cpg CPG_MOD 911>; | |
98 | power-domains = <&cpg>; | |
99 | }; | |
100 | ||
101 | gpio2: gpio@e6052000 { | |
102 | compatible = "renesas,gpio-r8a7795", | |
103 | "renesas,gpio-rcar"; | |
104 | reg = <0 0xe6052000 0 0x50>; | |
105 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
106 | #gpio-cells = <2>; | |
107 | gpio-controller; | |
108 | gpio-ranges = <&pfc 0 64 15>; | |
109 | #interrupt-cells = <2>; | |
110 | interrupt-controller; | |
111 | clocks = <&cpg CPG_MOD 910>; | |
112 | power-domains = <&cpg>; | |
113 | }; | |
114 | ||
115 | gpio3: gpio@e6053000 { | |
116 | compatible = "renesas,gpio-r8a7795", | |
117 | "renesas,gpio-rcar"; | |
118 | reg = <0 0xe6053000 0 0x50>; | |
119 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
120 | #gpio-cells = <2>; | |
121 | gpio-controller; | |
122 | gpio-ranges = <&pfc 0 96 16>; | |
123 | #interrupt-cells = <2>; | |
124 | interrupt-controller; | |
125 | clocks = <&cpg CPG_MOD 909>; | |
126 | power-domains = <&cpg>; | |
127 | }; | |
128 | ||
129 | gpio4: gpio@e6054000 { | |
130 | compatible = "renesas,gpio-r8a7795", | |
131 | "renesas,gpio-rcar"; | |
132 | reg = <0 0xe6054000 0 0x50>; | |
133 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
134 | #gpio-cells = <2>; | |
135 | gpio-controller; | |
136 | gpio-ranges = <&pfc 0 128 18>; | |
137 | #interrupt-cells = <2>; | |
138 | interrupt-controller; | |
139 | clocks = <&cpg CPG_MOD 908>; | |
140 | power-domains = <&cpg>; | |
141 | }; | |
142 | ||
143 | gpio5: gpio@e6055000 { | |
144 | compatible = "renesas,gpio-r8a7795", | |
145 | "renesas,gpio-rcar"; | |
146 | reg = <0 0xe6055000 0 0x50>; | |
147 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
148 | #gpio-cells = <2>; | |
149 | gpio-controller; | |
150 | gpio-ranges = <&pfc 0 160 26>; | |
151 | #interrupt-cells = <2>; | |
152 | interrupt-controller; | |
153 | clocks = <&cpg CPG_MOD 907>; | |
154 | power-domains = <&cpg>; | |
155 | }; | |
156 | ||
157 | gpio6: gpio@e6055400 { | |
158 | compatible = "renesas,gpio-r8a7795", | |
159 | "renesas,gpio-rcar"; | |
160 | reg = <0 0xe6055400 0 0x50>; | |
161 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
162 | #gpio-cells = <2>; | |
163 | gpio-controller; | |
164 | gpio-ranges = <&pfc 0 192 32>; | |
165 | #interrupt-cells = <2>; | |
166 | interrupt-controller; | |
167 | clocks = <&cpg CPG_MOD 906>; | |
168 | power-domains = <&cpg>; | |
169 | }; | |
170 | ||
171 | gpio7: gpio@e6055800 { | |
172 | compatible = "renesas,gpio-r8a7795", | |
173 | "renesas,gpio-rcar"; | |
174 | reg = <0 0xe6055800 0 0x50>; | |
175 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
176 | #gpio-cells = <2>; | |
177 | gpio-controller; | |
178 | gpio-ranges = <&pfc 0 224 4>; | |
179 | #interrupt-cells = <2>; | |
180 | interrupt-controller; | |
181 | clocks = <&cpg CPG_MOD 905>; | |
182 | power-domains = <&cpg>; | |
183 | }; | |
184 | ||
26a7e06d SH |
185 | timer { |
186 | compatible = "arm,armv8-timer"; | |
187 | interrupts = <GIC_PPI 13 | |
188 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
189 | <GIC_PPI 14 | |
190 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
191 | <GIC_PPI 11 | |
192 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
193 | <GIC_PPI 10 | |
194 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
195 | }; | |
196 | ||
197 | cpg: clock-controller@e6150000 { | |
198 | compatible = "renesas,r8a7795-cpg-mssr"; | |
199 | reg = <0 0xe6150000 0 0x1000>; | |
200 | clocks = <&extal_clk>, <&extalr_clk>; | |
201 | clock-names = "extal", "extalr"; | |
202 | #clock-cells = <2>; | |
203 | #power-domain-cells = <0>; | |
204 | }; | |
d9202126 | 205 | |
b281f4c8 KM |
206 | audma0: dma-controller@ec700000 { |
207 | compatible = "renesas,rcar-dmac"; | |
208 | reg = <0 0xec700000 0 0x10000>; | |
209 | interrupts = <0 350 IRQ_TYPE_LEVEL_HIGH | |
210 | 0 320 IRQ_TYPE_LEVEL_HIGH | |
211 | 0 321 IRQ_TYPE_LEVEL_HIGH | |
212 | 0 322 IRQ_TYPE_LEVEL_HIGH | |
213 | 0 323 IRQ_TYPE_LEVEL_HIGH | |
214 | 0 324 IRQ_TYPE_LEVEL_HIGH | |
215 | 0 325 IRQ_TYPE_LEVEL_HIGH | |
216 | 0 326 IRQ_TYPE_LEVEL_HIGH | |
217 | 0 327 IRQ_TYPE_LEVEL_HIGH | |
218 | 0 328 IRQ_TYPE_LEVEL_HIGH | |
219 | 0 329 IRQ_TYPE_LEVEL_HIGH | |
220 | 0 330 IRQ_TYPE_LEVEL_HIGH | |
221 | 0 331 IRQ_TYPE_LEVEL_HIGH | |
222 | 0 332 IRQ_TYPE_LEVEL_HIGH | |
223 | 0 333 IRQ_TYPE_LEVEL_HIGH | |
224 | 0 334 IRQ_TYPE_LEVEL_HIGH | |
225 | 0 335 IRQ_TYPE_LEVEL_HIGH>; | |
226 | interrupt-names = "error", | |
227 | "ch0", "ch1", "ch2", "ch3", | |
228 | "ch4", "ch5", "ch6", "ch7", | |
229 | "ch8", "ch9", "ch10", "ch11", | |
230 | "ch12", "ch13", "ch14", "ch15"; | |
231 | clocks = <&cpg CPG_MOD 502>; | |
232 | clock-names = "fck"; | |
233 | power-domains = <&cpg>; | |
234 | #dma-cells = <1>; | |
235 | dma-channels = <16>; | |
236 | }; | |
237 | ||
238 | audma1: dma-controller@ec720000 { | |
239 | compatible = "renesas,rcar-dmac"; | |
240 | reg = <0 0xec720000 0 0x10000>; | |
241 | interrupts = <0 351 IRQ_TYPE_LEVEL_HIGH | |
242 | 0 336 IRQ_TYPE_LEVEL_HIGH | |
243 | 0 337 IRQ_TYPE_LEVEL_HIGH | |
244 | 0 338 IRQ_TYPE_LEVEL_HIGH | |
245 | 0 339 IRQ_TYPE_LEVEL_HIGH | |
246 | 0 340 IRQ_TYPE_LEVEL_HIGH | |
247 | 0 341 IRQ_TYPE_LEVEL_HIGH | |
248 | 0 342 IRQ_TYPE_LEVEL_HIGH | |
249 | 0 343 IRQ_TYPE_LEVEL_HIGH | |
250 | 0 344 IRQ_TYPE_LEVEL_HIGH | |
251 | 0 345 IRQ_TYPE_LEVEL_HIGH | |
252 | 0 346 IRQ_TYPE_LEVEL_HIGH | |
253 | 0 347 IRQ_TYPE_LEVEL_HIGH | |
254 | 0 348 IRQ_TYPE_LEVEL_HIGH | |
255 | 0 349 IRQ_TYPE_LEVEL_HIGH | |
256 | 0 382 IRQ_TYPE_LEVEL_HIGH | |
257 | 0 383 IRQ_TYPE_LEVEL_HIGH>; | |
258 | interrupt-names = "error", | |
259 | "ch0", "ch1", "ch2", "ch3", | |
260 | "ch4", "ch5", "ch6", "ch7", | |
261 | "ch8", "ch9", "ch10", "ch11", | |
262 | "ch12", "ch13", "ch14", "ch15"; | |
263 | clocks = <&cpg CPG_MOD 501>; | |
264 | clock-names = "fck"; | |
265 | power-domains = <&cpg>; | |
266 | #dma-cells = <1>; | |
267 | dma-channels = <16>; | |
268 | }; | |
269 | ||
9241844a KM |
270 | pfc: pfc@e6060000 { |
271 | compatible = "renesas,pfc-r8a7795"; | |
272 | reg = <0 0xe6060000 0 0x50c>; | |
273 | }; | |
274 | ||
d9202126 GU |
275 | dmac0: dma-controller@e6700000 { |
276 | /* Empty node for now */ | |
277 | }; | |
278 | ||
279 | dmac1: dma-controller@e7300000 { | |
280 | /* Empty node for now */ | |
281 | }; | |
282 | ||
283 | dmac2: dma-controller@e7310000 { | |
284 | /* Empty node for now */ | |
285 | }; | |
49af46b4 | 286 | |
a92843c8 KM |
287 | avb: ethernet@e6800000 { |
288 | compatible = "renesas,etheravb-r8a7795"; | |
289 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; | |
290 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
291 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
292 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
293 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
294 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
295 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
296 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
297 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
298 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
299 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
300 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
301 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
302 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
303 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
304 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
305 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
306 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
307 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
308 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
309 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
310 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
311 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
312 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
313 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
314 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
315 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
316 | "ch4", "ch5", "ch6", "ch7", | |
317 | "ch8", "ch9", "ch10", "ch11", | |
318 | "ch12", "ch13", "ch14", "ch15", | |
319 | "ch16", "ch17", "ch18", "ch19", | |
320 | "ch20", "ch21", "ch22", "ch23", | |
321 | "ch24"; | |
322 | clocks = <&cpg CPG_MOD 812>; | |
323 | power-domains = <&cpg>; | |
324 | phy-mode = "rgmii-id"; | |
325 | #address-cells = <1>; | |
326 | #size-cells = <0>; | |
327 | }; | |
328 | ||
4fa04299 GU |
329 | hscif0: serial@e6540000 { |
330 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
331 | reg = <0 0xe6540000 0 96>; | |
332 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
333 | clocks = <&cpg CPG_MOD 520>; | |
334 | clock-names = "sci_ick"; | |
335 | dmas = <&dmac1 0x31>, <&dmac1 0x30>; | |
336 | dma-names = "tx", "rx"; | |
337 | power-domains = <&cpg>; | |
338 | status = "disabled"; | |
339 | }; | |
340 | ||
341 | hscif1: serial@e6550000 { | |
342 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
343 | reg = <0 0xe6550000 0 96>; | |
344 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
345 | clocks = <&cpg CPG_MOD 519>; | |
346 | clock-names = "sci_ick"; | |
347 | dmas = <&dmac1 0x33>, <&dmac1 0x32>; | |
348 | dma-names = "tx", "rx"; | |
349 | power-domains = <&cpg>; | |
350 | status = "disabled"; | |
351 | }; | |
352 | ||
353 | hscif2: serial@e6560000 { | |
354 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
355 | reg = <0 0xe6560000 0 96>; | |
356 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
357 | clocks = <&cpg CPG_MOD 518>; | |
358 | clock-names = "sci_ick"; | |
359 | dmas = <&dmac1 0x35>, <&dmac1 0x34>; | |
360 | dma-names = "tx", "rx"; | |
361 | power-domains = <&cpg>; | |
362 | status = "disabled"; | |
363 | }; | |
364 | ||
365 | hscif3: serial@e66a0000 { | |
366 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
367 | reg = <0 0xe66a0000 0 96>; | |
368 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
369 | clocks = <&cpg CPG_MOD 517>; | |
370 | clock-names = "sci_ick"; | |
371 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
372 | dma-names = "tx", "rx"; | |
373 | power-domains = <&cpg>; | |
374 | status = "disabled"; | |
375 | }; | |
376 | ||
377 | hscif4: serial@e66b0000 { | |
378 | compatible = "renesas,hscif-r8a7795", "renesas,hscif"; | |
379 | reg = <0 0xe66b0000 0 96>; | |
380 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
381 | clocks = <&cpg CPG_MOD 516>; | |
382 | clock-names = "sci_ick"; | |
383 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; | |
384 | dma-names = "tx", "rx"; | |
385 | power-domains = <&cpg>; | |
386 | status = "disabled"; | |
387 | }; | |
388 | ||
49af46b4 GU |
389 | scif0: serial@e6e60000 { |
390 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
391 | reg = <0 0xe6e60000 0 64>; | |
392 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
393 | clocks = <&cpg CPG_MOD 207>; | |
394 | clock-names = "sci_ick"; | |
395 | dmas = <&dmac1 0x51>, <&dmac1 0x50>; | |
396 | dma-names = "tx", "rx"; | |
397 | power-domains = <&cpg>; | |
398 | status = "disabled"; | |
399 | }; | |
400 | ||
401 | scif1: serial@e6e68000 { | |
402 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
403 | reg = <0 0xe6e68000 0 64>; | |
404 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
405 | clocks = <&cpg CPG_MOD 206>; | |
406 | clock-names = "sci_ick"; | |
407 | dmas = <&dmac1 0x53>, <&dmac1 0x52>; | |
408 | dma-names = "tx", "rx"; | |
409 | power-domains = <&cpg>; | |
410 | status = "disabled"; | |
411 | }; | |
412 | ||
413 | scif2: serial@e6e88000 { | |
414 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
415 | reg = <0 0xe6e88000 0 64>; | |
416 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
417 | clocks = <&cpg CPG_MOD 310>; | |
418 | clock-names = "sci_ick"; | |
419 | dmas = <&dmac1 0x13>, <&dmac1 0x12>; | |
420 | dma-names = "tx", "rx"; | |
421 | power-domains = <&cpg>; | |
422 | status = "disabled"; | |
423 | }; | |
424 | ||
425 | scif3: serial@e6c50000 { | |
426 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
427 | reg = <0 0xe6c50000 0 64>; | |
428 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
429 | clocks = <&cpg CPG_MOD 204>; | |
430 | clock-names = "sci_ick"; | |
431 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
432 | dma-names = "tx", "rx"; | |
433 | power-domains = <&cpg>; | |
434 | status = "disabled"; | |
435 | }; | |
436 | ||
437 | scif4: serial@e6c40000 { | |
438 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
439 | reg = <0 0xe6c40000 0 64>; | |
440 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
441 | clocks = <&cpg CPG_MOD 203>; | |
442 | clock-names = "sci_ick"; | |
443 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
444 | dma-names = "tx", "rx"; | |
445 | power-domains = <&cpg>; | |
446 | status = "disabled"; | |
447 | }; | |
448 | ||
449 | scif5: serial@e6f30000 { | |
450 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
451 | reg = <0 0xe6f30000 0 64>; | |
452 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
453 | clocks = <&cpg CPG_MOD 202>; | |
454 | clock-names = "sci_ick"; | |
455 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; | |
456 | dma-names = "tx", "rx"; | |
457 | power-domains = <&cpg>; | |
458 | status = "disabled"; | |
459 | }; | |
32bc0c51 KM |
460 | |
461 | i2c0: i2c@e6500000 { | |
462 | #address-cells = <1>; | |
463 | #size-cells = <0>; | |
464 | compatible = "renesas,i2c-r8a7795"; | |
465 | reg = <0 0xe6500000 0 0x40>; | |
466 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
467 | clocks = <&cpg CPG_MOD 931>; | |
468 | power-domains = <&cpg>; | |
469 | status = "disabled"; | |
470 | }; | |
471 | ||
472 | i2c1: i2c@e6508000 { | |
473 | #address-cells = <1>; | |
474 | #size-cells = <0>; | |
475 | compatible = "renesas,i2c-r8a7795"; | |
476 | reg = <0 0xe6508000 0 0x40>; | |
477 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
478 | clocks = <&cpg CPG_MOD 930>; | |
479 | power-domains = <&cpg>; | |
480 | status = "disabled"; | |
481 | }; | |
482 | ||
483 | i2c2: i2c@e6510000 { | |
484 | #address-cells = <1>; | |
485 | #size-cells = <0>; | |
486 | compatible = "renesas,i2c-r8a7795"; | |
487 | reg = <0 0xe6510000 0 0x40>; | |
488 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
489 | clocks = <&cpg CPG_MOD 929>; | |
490 | power-domains = <&cpg>; | |
491 | status = "disabled"; | |
492 | }; | |
493 | ||
494 | i2c3: i2c@e66d0000 { | |
495 | #address-cells = <1>; | |
496 | #size-cells = <0>; | |
497 | compatible = "renesas,i2c-r8a7795"; | |
498 | reg = <0 0xe66d0000 0 0x40>; | |
499 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
500 | clocks = <&cpg CPG_MOD 928>; | |
501 | power-domains = <&cpg>; | |
502 | status = "disabled"; | |
503 | }; | |
504 | ||
505 | i2c4: i2c@e66d8000 { | |
506 | #address-cells = <1>; | |
507 | #size-cells = <0>; | |
508 | compatible = "renesas,i2c-r8a7795"; | |
509 | reg = <0 0xe66d8000 0 0x40>; | |
510 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
511 | clocks = <&cpg CPG_MOD 927>; | |
512 | power-domains = <&cpg>; | |
513 | status = "disabled"; | |
514 | }; | |
515 | ||
516 | i2c5: i2c@e66e0000 { | |
517 | #address-cells = <1>; | |
518 | #size-cells = <0>; | |
519 | compatible = "renesas,i2c-r8a7795"; | |
520 | reg = <0 0xe66e0000 0 0x40>; | |
521 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
522 | clocks = <&cpg CPG_MOD 919>; | |
523 | power-domains = <&cpg>; | |
524 | status = "disabled"; | |
525 | }; | |
526 | ||
527 | i2c6: i2c@e66e8000 { | |
528 | #address-cells = <1>; | |
529 | #size-cells = <0>; | |
530 | compatible = "renesas,i2c-r8a7795"; | |
531 | reg = <0 0xe66e8000 0 0x40>; | |
532 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
533 | clocks = <&cpg CPG_MOD 918>; | |
534 | power-domains = <&cpg>; | |
535 | status = "disabled"; | |
536 | }; | |
26a7e06d SH |
537 | }; |
538 | }; |