[linux-2.6-block.git] / arch / arm64 / boot / dts / renesas / r8a7795.dtsi

/*
 * Device Tree Source for the r8a7795 SoC
 *
 * Copyright (C) 2015 Renesas Electronics Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "renesas,r8a7795";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* 1 core only at this point */
		a57_0: cpu@0 {
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x0>;
			device_type = "cpu";
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	extalr_clk: extalr {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gic: interrupt-controller@0xf1010000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xf1010000 0 0x1000>,
			      <0x0 0xf1020000 0 0x2000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 16>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&cpg>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 28>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&cpg>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 15>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&cpg>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 16>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&cpg>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 18>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&cpg>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 26>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&cpg>;
		};

		gpio6: gpio@e6055400 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6055400 0 0x50>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 192 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 906>;
			power-domains = <&cpg>;
		};

		gpio7: gpio@e6055800 {
			compatible = "renesas,gpio-r8a7795",
				     "renesas,gpio-rcar";
			reg = <0 0xe6055800 0 0x50>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 224 4>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 905>;
			power-domains = <&cpg>;
		};

		timer {
			compatible = "arm,armv8-timer";
			interrupts = <GIC_PPI 13
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 14
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 11
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 10
					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a7795-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>, <&extalr_clk>;
			clock-names = "extal", "extalr";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
		};

		pfc: pfc@e6060000 {
			compatible = "renesas,pfc-r8a7795";
			reg = <0 0xe6060000 0 0x50c>;
		};

		dmac0: dma-controller@e6700000 {
			/* Empty node for now */
		};

		dmac1: dma-controller@e7300000 {
			/* Empty node for now */
		};

		dmac2: dma-controller@e7310000 {
			/* Empty node for now */
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a7795";
			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14", "ch15",
					  "ch16", "ch17", "ch18", "ch19",
					  "ch20", "ch21", "ch22", "ch23",
					  "ch24";
			clocks = <&cpg CPG_MOD 812>;
			power-domains = <&cpg>;
			phy-mode = "rgmii-id";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		scif0: serial@e6e60000 {
			compatible = "renesas,scif-r8a7795", "renesas,scif";
			reg = <0 0xe6e60000 0 64>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 207>;
			clock-names = "sci_ick";
			dmas = <&dmac1 0x51>, <&dmac1 0x50>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif1: serial@e6e68000 {
			compatible = "renesas,scif-r8a7795", "renesas,scif";
			reg = <0 0xe6e68000 0 64>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 206>;
			clock-names = "sci_ick";
			dmas = <&dmac1 0x53>, <&dmac1 0x52>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif2: serial@e6e88000 {
			compatible = "renesas,scif-r8a7795", "renesas,scif";
			reg = <0 0xe6e88000 0 64>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 310>;
			clock-names = "sci_ick";
			dmas = <&dmac1 0x13>, <&dmac1 0x12>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif3: serial@e6c50000 {
			compatible = "renesas,scif-r8a7795", "renesas,scif";
			reg = <0 0xe6c50000 0 64>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 204>;
			clock-names = "sci_ick";
			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif4: serial@e6c40000 {
			compatible = "renesas,scif-r8a7795", "renesas,scif";
			reg = <0 0xe6c40000 0 64>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 203>;
			clock-names = "sci_ick";
			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			status = "disabled";
		};

		scif5: serial@e6f30000 {
			compatible = "renesas,scif-r8a7795", "renesas,scif";
			reg = <0 0xe6f30000 0 64>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 202>;
			clock-names = "sci_ick";
			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c0: i2c@e6500000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7795";
			reg = <0 0xe6500000 0 0x40>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 931>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c1: i2c@e6508000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7795";
			reg = <0 0xe6508000 0 0x40>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 930>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c2: i2c@e6510000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7795";
			reg = <0 0xe6510000 0 0x40>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 929>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c3: i2c@e66d0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7795";
			reg = <0 0xe66d0000 0 0x40>;
			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 928>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c4: i2c@e66d8000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7795";
			reg = <0 0xe66d8000 0 0x40>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 927>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c5: i2c@e66e0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7795";
			reg = <0 0xe66e0000 0 0x40>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 919>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c6: i2c@e66e8000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7795";
			reg = <0 0xe66e8000 0 0x40>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 918>;
			power-domains = <&cpg>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
26a7e06d SH	1	/*
	2	* Device Tree Source for the r8a7795 SoC
	3	*
	4	* Copyright (C) 2015 Renesas Electronics Corp.
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
49af46b4	11	#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
26a7e06d SH	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
	13
	14	/ {
	15	compatible = "renesas,r8a7795";
	16	#address-cells = <2>;
	17	#size-cells = <2>;
	18
32bc0c51 KM	19	aliases {
	20	i2c0 = &i2c0;
	21	i2c1 = &i2c1;
	22	i2c2 = &i2c2;
	23	i2c3 = &i2c3;
	24	i2c4 = &i2c4;
	25	i2c5 = &i2c5;
	26	i2c6 = &i2c6;
	27	};
	28
26a7e06d SH	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	/* 1 core only at this point */
	34	a57_0: cpu@0 {
	35	compatible = "arm,cortex-a57", "arm,armv8";
	36	reg = <0x0>;
	37	device_type = "cpu";
	38	};
	39	};
	40
	41	extal_clk: extal {
	42	compatible = "fixed-clock";
	43	#clock-cells = <0>;
	44	/* This value must be overridden by the board */
	45	clock-frequency = <0>;
	46	};
	47
	48	extalr_clk: extalr {
	49	compatible = "fixed-clock";
	50	#clock-cells = <0>;
	51	/* This value must be overridden by the board */
	52	clock-frequency = <0>;
	53	};
	54
	55	soc {
	56	compatible = "simple-bus";
	57	interrupt-parent = <&gic>;
	58	#address-cells = <2>;
	59	#size-cells = <2>;
	60	ranges;
	61
	62	gic: interrupt-controller@0xf1010000 {
	63	compatible = "arm,gic-400";
	64	#interrupt-cells = <3>;
	65	#address-cells = <0>;
	66	interrupt-controller;
	67	reg = <0x0 0xf1010000 0 0x1000>,
	68	<0x0 0xf1020000 0 0x2000>;
	69	interrupts = <GIC_PPI 9
	70	(GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_HIGH)>;
	71	};
	72
7b08623a TK	73	gpio0: gpio@e6050000 {
	74	compatible = "renesas,gpio-r8a7795",
	75	"renesas,gpio-rcar";
	76	reg = <0 0xe6050000 0 0x50>;
	77	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	78	#gpio-cells = <2>;
	79	gpio-controller;
	80	gpio-ranges = <&pfc 0 0 16>;
	81	#interrupt-cells = <2>;
	82	interrupt-controller;
	83	clocks = <&cpg CPG_MOD 912>;
	84	power-domains = <&cpg>;
	85	};
	86
	87	gpio1: gpio@e6051000 {
	88	compatible = "renesas,gpio-r8a7795",
	89	"renesas,gpio-rcar";
	90	reg = <0 0xe6051000 0 0x50>;
	91	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	92	#gpio-cells = <2>;
	93	gpio-controller;
	94	gpio-ranges = <&pfc 0 32 28>;
	95	#interrupt-cells = <2>;
	96	interrupt-controller;
	97	clocks = <&cpg CPG_MOD 911>;
	98	power-domains = <&cpg>;
	99	};
	100
	101	gpio2: gpio@e6052000 {
	102	compatible = "renesas,gpio-r8a7795",
	103	"renesas,gpio-rcar";
	104	reg = <0 0xe6052000 0 0x50>;
	105	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	106	#gpio-cells = <2>;
	107	gpio-controller;
	108	gpio-ranges = <&pfc 0 64 15>;
	109	#interrupt-cells = <2>;
	110	interrupt-controller;
	111	clocks = <&cpg CPG_MOD 910>;
	112	power-domains = <&cpg>;
	113	};
	114
	115	gpio3: gpio@e6053000 {
	116	compatible = "renesas,gpio-r8a7795",
	117	"renesas,gpio-rcar";
	118	reg = <0 0xe6053000 0 0x50>;
	119	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	120	#gpio-cells = <2>;
	121	gpio-controller;
	122	gpio-ranges = <&pfc 0 96 16>;
	123	#interrupt-cells = <2>;
	124	interrupt-controller;
	125	clocks = <&cpg CPG_MOD 909>;
	126	power-domains = <&cpg>;
	127	};
	128
	129	gpio4: gpio@e6054000 {
	130	compatible = "renesas,gpio-r8a7795",
	131	"renesas,gpio-rcar";
	132	reg = <0 0xe6054000 0 0x50>;
	133	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	134	#gpio-cells = <2>;
	135	gpio-controller;
	136	gpio-ranges = <&pfc 0 128 18>;
137	#interrupt-cells = <2>;
138	interrupt-controller;
139	clocks = <&cpg CPG_MOD 908>;
140	power-domains = <&cpg>;
141	};
142
143	gpio5: gpio@e6055000 {
144	compatible = "renesas,gpio-r8a7795",
145	"renesas,gpio-rcar";
146	reg = <0 0xe6055000 0 0x50>;
147	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
148	#gpio-cells = <2>;
149	gpio-controller;
150	gpio-ranges = <&pfc 0 160 26>;
151	#interrupt-cells = <2>;
152	interrupt-controller;
153	clocks = <&cpg CPG_MOD 907>;
154	power-domains = <&cpg>;
155	};
156
157	gpio6: gpio@e6055400 {
158	compatible = "renesas,gpio-r8a7795",
159	"renesas,gpio-rcar";
160	reg = <0 0xe6055400 0 0x50>;
161	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
162	#gpio-cells = <2>;
163	gpio-controller;
164	gpio-ranges = <&pfc 0 192 32>;
165	#interrupt-cells = <2>;
166	interrupt-controller;
167	clocks = <&cpg CPG_MOD 906>;
168	power-domains = <&cpg>;
169	};
170
171	gpio7: gpio@e6055800 {
172	compatible = "renesas,gpio-r8a7795",
173	"renesas,gpio-rcar";
174	reg = <0 0xe6055800 0 0x50>;
175	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
176	#gpio-cells = <2>;
177	gpio-controller;
178	gpio-ranges = <&pfc 0 224 4>;
179	#interrupt-cells = <2>;
180	interrupt-controller;
181	clocks = <&cpg CPG_MOD 905>;
182	power-domains = <&cpg>;
183	};
184
26a7e06d SH	185	timer {
	186	compatible = "arm,armv8-timer";
	187	interrupts = <GIC_PPI 13
	188	(GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	189	<GIC_PPI 14
	190	(GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	191	<GIC_PPI 11
	192	(GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>,
	193	<GIC_PPI 10
	194	(GIC_CPU_MASK_SIMPLE(1) \| IRQ_TYPE_LEVEL_LOW)>;
	195	};
	196
	197	cpg: clock-controller@e6150000 {
	198	compatible = "renesas,r8a7795-cpg-mssr";
	199	reg = <0 0xe6150000 0 0x1000>;
	200	clocks = <&extal_clk>, <&extalr_clk>;
	201	clock-names = "extal", "extalr";
	202	#clock-cells = <2>;
	203	#power-domain-cells = <0>;
	204	};
d9202126	205
9241844a KM	206	pfc: pfc@e6060000 {
	207	compatible = "renesas,pfc-r8a7795";
	208	reg = <0 0xe6060000 0 0x50c>;
	209	};
	210
d9202126 GU	211	dmac0: dma-controller@e6700000 {
	212	/* Empty node for now */
	213	};
	214
	215	dmac1: dma-controller@e7300000 {
	216	/* Empty node for now */
	217	};
	218
	219	dmac2: dma-controller@e7310000 {
	220	/* Empty node for now */
	221	};
49af46b4	222
a92843c8 KM	223	avb: ethernet@e6800000 {
	224	compatible = "renesas,etheravb-r8a7795";
	225	reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
	226	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	227	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	229	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	230	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	231	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	232	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	233	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	234	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	235	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	236	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	237	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	238	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	239	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	240	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	241	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	242	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	243	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	244	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	245	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	246	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	247	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	248	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	249	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	251	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	252	"ch4", "ch5", "ch6", "ch7",
	253	"ch8", "ch9", "ch10", "ch11",
	254	"ch12", "ch13", "ch14", "ch15",
	255	"ch16", "ch17", "ch18", "ch19",
	256	"ch20", "ch21", "ch22", "ch23",
	257	"ch24";
	258	clocks = <&cpg CPG_MOD 812>;
	259	power-domains = <&cpg>;
	260	phy-mode = "rgmii-id";
	261	#address-cells = <1>;
	262	#size-cells = <0>;
	263	};
	264
49af46b4 GU	265	scif0: serial@e6e60000 {
	266	compatible = "renesas,scif-r8a7795", "renesas,scif";
	267	reg = <0 0xe6e60000 0 64>;
	268	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	269	clocks = <&cpg CPG_MOD 207>;
	270	clock-names = "sci_ick";
	271	dmas = <&dmac1 0x51>, <&dmac1 0x50>;
	272	dma-names = "tx", "rx";
	273	power-domains = <&cpg>;
	274	status = "disabled";
	275	};
	276
	277	scif1: serial@e6e68000 {
	278	compatible = "renesas,scif-r8a7795", "renesas,scif";
	279	reg = <0 0xe6e68000 0 64>;
	280	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	281	clocks = <&cpg CPG_MOD 206>;
	282	clock-names = "sci_ick";
	283	dmas = <&dmac1 0x53>, <&dmac1 0x52>;
	284	dma-names = "tx", "rx";
	285	power-domains = <&cpg>;
	286	status = "disabled";
	287	};
	288
	289	scif2: serial@e6e88000 {
	290	compatible = "renesas,scif-r8a7795", "renesas,scif";
	291	reg = <0 0xe6e88000 0 64>;
	292	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	293	clocks = <&cpg CPG_MOD 310>;
	294	clock-names = "sci_ick";
	295	dmas = <&dmac1 0x13>, <&dmac1 0x12>;
	296	dma-names = "tx", "rx";
	297	power-domains = <&cpg>;
	298	status = "disabled";
	299	};
	300
	301	scif3: serial@e6c50000 {
	302	compatible = "renesas,scif-r8a7795", "renesas,scif";
	303	reg = <0 0xe6c50000 0 64>;
	304	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	305	clocks = <&cpg CPG_MOD 204>;
	306	clock-names = "sci_ick";
	307	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	308	dma-names = "tx", "rx";
	309	power-domains = <&cpg>;
	310	status = "disabled";
	311	};
	312
	313	scif4: serial@e6c40000 {
	314	compatible = "renesas,scif-r8a7795", "renesas,scif";
	315	reg = <0 0xe6c40000 0 64>;
	316	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	317	clocks = <&cpg CPG_MOD 203>;
	318	clock-names = "sci_ick";
	319	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
	320	dma-names = "tx", "rx";
	321	power-domains = <&cpg>;
	322	status = "disabled";
	323	};
	324
	325	scif5: serial@e6f30000 {
	326	compatible = "renesas,scif-r8a7795", "renesas,scif";
	327	reg = <0 0xe6f30000 0 64>;
	328	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
329	clocks = <&cpg CPG_MOD 202>;
330	clock-names = "sci_ick";
331	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
332	dma-names = "tx", "rx";
333	power-domains = <&cpg>;
334	status = "disabled";
335	};
32bc0c51 KM	336
	337	i2c0: i2c@e6500000 {
	338	#address-cells = <1>;
	339	#size-cells = <0>;
	340	compatible = "renesas,i2c-r8a7795";
	341	reg = <0 0xe6500000 0 0x40>;
	342	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	343	clocks = <&cpg CPG_MOD 931>;
	344	power-domains = <&cpg>;
	345	status = "disabled";
	346	};
	347
	348	i2c1: i2c@e6508000 {
	349	#address-cells = <1>;
	350	#size-cells = <0>;
	351	compatible = "renesas,i2c-r8a7795";
	352	reg = <0 0xe6508000 0 0x40>;
	353	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
	354	clocks = <&cpg CPG_MOD 930>;
	355	power-domains = <&cpg>;
	356	status = "disabled";
	357	};
	358
	359	i2c2: i2c@e6510000 {
	360	#address-cells = <1>;
	361	#size-cells = <0>;
	362	compatible = "renesas,i2c-r8a7795";
	363	reg = <0 0xe6510000 0 0x40>;
	364	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	365	clocks = <&cpg CPG_MOD 929>;
	366	power-domains = <&cpg>;
	367	status = "disabled";
	368	};
	369
	370	i2c3: i2c@e66d0000 {
	371	#address-cells = <1>;
	372	#size-cells = <0>;
	373	compatible = "renesas,i2c-r8a7795";
	374	reg = <0 0xe66d0000 0 0x40>;
	375	interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
	376	clocks = <&cpg CPG_MOD 928>;
	377	power-domains = <&cpg>;
	378	status = "disabled";
	379	};
	380
	381	i2c4: i2c@e66d8000 {
	382	#address-cells = <1>;
	383	#size-cells = <0>;
	384	compatible = "renesas,i2c-r8a7795";
	385	reg = <0 0xe66d8000 0 0x40>;
	386	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	387	clocks = <&cpg CPG_MOD 927>;
	388	power-domains = <&cpg>;
	389	status = "disabled";
	390	};
	391
	392	i2c5: i2c@e66e0000 {
	393	#address-cells = <1>;
	394	#size-cells = <0>;
	395	compatible = "renesas,i2c-r8a7795";
	396	reg = <0 0xe66e0000 0 0x40>;
	397	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	398	clocks = <&cpg CPG_MOD 919>;
	399	power-domains = <&cpg>;
400	status = "disabled";
401	};
402
403	i2c6: i2c@e66e8000 {
404	#address-cells = <1>;
405	#size-cells = <0>;
406	compatible = "renesas,i2c-r8a7795";
407	reg = <0 0xe66e8000 0 0x40>;
408	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
409	clocks = <&cpg CPG_MOD 918>;
410	power-domains = <&cpg>;
411	status = "disabled";
412	};
26a7e06d SH	413	};
26a7e06d SH	414	};