projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 26a7e06d SH |
1 | /* |
| 2 | * Device Tree Source for the r8a7795 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2015 Renesas Electronics Corp. | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 49af46b4 | 11 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
| 26a7e06d SH |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | ||
| 14 | / { | |
| 15 | compatible = "renesas,r8a7795"; | |
| 16 | #address-cells = <2>; | |
| 17 | #size-cells = <2>; | |
| 18 | ||
| 19 | cpus { | |
| 20 | #address-cells = <1>; | |
| 21 | #size-cells = <0>; | |
| 22 | ||
| 23 | /* 1 core only at this point */ | |
| 24 | a57_0: cpu@0 { | |
| 25 | compatible = "arm,cortex-a57", "arm,armv8"; | |
| 26 | reg = <0x0>; | |
| 27 | device_type = "cpu"; | |
| 28 | }; | |
| 29 | }; | |
| 30 | ||
| 31 | extal_clk: extal { | |
| 32 | compatible = "fixed-clock"; | |
| 33 | #clock-cells = <0>; | |
| 34 | /* This value must be overridden by the board */ | |
| 35 | clock-frequency = <0>; | |
| 36 | }; | |
| 37 | ||
| 38 | extalr_clk: extalr { | |
| 39 | compatible = "fixed-clock"; | |
| 40 | #clock-cells = <0>; | |
| 41 | /* This value must be overridden by the board */ | |
| 42 | clock-frequency = <0>; | |
| 43 | }; | |
| 44 | ||
| 45 | soc { | |
| 46 | compatible = "simple-bus"; | |
| 47 | interrupt-parent = <&gic>; | |
| 48 | #address-cells = <2>; | |
| 49 | #size-cells = <2>; | |
| 50 | ranges; | |
| 51 | ||
| 52 | gic: interrupt-controller@0xf1010000 { | |
| 53 | compatible = "arm,gic-400"; | |
| 54 | #interrupt-cells = <3>; | |
| 55 | #address-cells = <0>; | |
| 56 | interrupt-controller; | |
| 57 | reg = <0x0 0xf1010000 0 0x1000>, | |
| 58 | <0x0 0xf1020000 0 0x2000>; | |
| 59 | interrupts = <GIC_PPI 9 | |
| 60 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 61 | }; | |
| 62 | ||
| 63 | timer { | |
| 64 | compatible = "arm,armv8-timer"; | |
| 65 | interrupts = <GIC_PPI 13 | |
| 66 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 67 | <GIC_PPI 14 | |
| 68 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 69 | <GIC_PPI 11 | |
| 70 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 71 | <GIC_PPI 10 | |
| 72 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
| 73 | }; | |
| 74 | ||
| 75 | cpg: clock-controller@e6150000 { | |
| 76 | compatible = "renesas,r8a7795-cpg-mssr"; | |
| 77 | reg = <0 0xe6150000 0 0x1000>; | |
| 78 | clocks = <&extal_clk>, <&extalr_clk>; | |
| 79 | clock-names = "extal", "extalr"; | |
| 80 | #clock-cells = <2>; | |
| 81 | #power-domain-cells = <0>; | |
| 82 | }; | |
| d9202126 GU |
83 | |
| 84 | dmac0: dma-controller@e6700000 { | |
| 85 | /* Empty node for now */ | |
| 86 | }; | |
| 87 | ||
| 88 | dmac1: dma-controller@e7300000 { | |
| 89 | /* Empty node for now */ | |
| 90 | }; | |
| 91 | ||
| 92 | dmac2: dma-controller@e7310000 { | |
| 93 | /* Empty node for now */ | |
| 94 | }; | |
| 49af46b4 GU |
95 | |
| 96 | scif0: serial@e6e60000 { | |
| 97 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
| 98 | reg = <0 0xe6e60000 0 64>; | |
| 99 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 100 | clocks = <&cpg CPG_MOD 207>; | |
| 101 | clock-names = "sci_ick"; | |
| 102 | dmas = <&dmac1 0x51>, <&dmac1 0x50>; | |
| 103 | dma-names = "tx", "rx"; | |
| 104 | power-domains = <&cpg>; | |
| 105 | status = "disabled"; | |
| 106 | }; | |
| 107 | ||
| 108 | scif1: serial@e6e68000 { | |
| 109 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
| 110 | reg = <0 0xe6e68000 0 64>; | |
| 111 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
| 112 | clocks = <&cpg CPG_MOD 206>; | |
| 113 | clock-names = "sci_ick"; | |
| 114 | dmas = <&dmac1 0x53>, <&dmac1 0x52>; | |
| 115 | dma-names = "tx", "rx"; | |
| 116 | power-domains = <&cpg>; | |
| 117 | status = "disabled"; | |
| 118 | }; | |
| 119 | ||
| 120 | scif2: serial@e6e88000 { | |
| 121 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
| 122 | reg = <0 0xe6e88000 0 64>; | |
| 123 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| 124 | clocks = <&cpg CPG_MOD 310>; | |
| 125 | clock-names = "sci_ick"; | |
| 126 | dmas = <&dmac1 0x13>, <&dmac1 0x12>; | |
| 127 | dma-names = "tx", "rx"; | |
| 128 | power-domains = <&cpg>; | |
| 129 | status = "disabled"; | |
| 130 | }; | |
| 131 | ||
| 132 | scif3: serial@e6c50000 { | |
| 133 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
| 134 | reg = <0 0xe6c50000 0 64>; | |
| 135 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 136 | clocks = <&cpg CPG_MOD 204>; | |
| 137 | clock-names = "sci_ick"; | |
| 138 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
| 139 | dma-names = "tx", "rx"; | |
| 140 | power-domains = <&cpg>; | |
| 141 | status = "disabled"; | |
| 142 | }; | |
| 143 | ||
| 144 | scif4: serial@e6c40000 { | |
| 145 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
| 146 | reg = <0 0xe6c40000 0 64>; | |
| 147 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 148 | clocks = <&cpg CPG_MOD 203>; | |
| 149 | clock-names = "sci_ick"; | |
| 150 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
| 151 | dma-names = "tx", "rx"; | |
| 152 | power-domains = <&cpg>; | |
| 153 | status = "disabled"; | |
| 154 | }; | |
| 155 | ||
| 156 | scif5: serial@e6f30000 { | |
| 157 | compatible = "renesas,scif-r8a7795", "renesas,scif"; | |
| 158 | reg = <0 0xe6f30000 0 64>; | |
| 159 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 160 | clocks = <&cpg CPG_MOD 202>; | |
| 161 | clock-names = "sci_ick"; | |
| 162 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; | |
| 163 | dma-names = "tx", "rx"; | |
| 164 | power-domains = <&cpg>; | |
| 165 | status = "disabled"; | |
| 166 | }; | |
| 26a7e06d SH |
167 | }; |
| 168 | }; |