[linux-2.6-block.git] / arch / arm64 / boot / dts / qcom / msm8916.dtsi

/*
 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>

/ {
	model = "Qualcomm Technologies, Inc. MSM8916";
	compatible = "qcom,msm8916";

	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD card slot */
	};

	chosen { };

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		reserve_aligned@86000000 {
			reg = <0x0 0x86000000 0x0 0x0300000>;
			no-map;
		};

		smem_mem: smem_region@86300000 {
			reg = <0x0 0x86300000 0x0 0x0100000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x0>;
			next-level-cache = <&L2_0>;
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x2>;
			next-level-cache = <&L2_0>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0x3>;
			next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache {
		      compatible = "cache";
		      cache-level = <2>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
		};

		msmgpio: pinctrl@1000000 {
			compatible = "qcom,msm8916-pinctrl";
			reg = <0x1000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-msm8916";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x1800000 0x80000>;
		};

		tcsr_mutex_regs: syscon@1905000 {
			compatible = "syscon";
			reg = <0x1905000 0x20000>;
		};

		tcsr_mutex: hwlock {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_regs 0 0x1000>;
			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x60000 0x8000>;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		apcs: syscon@b011000 {
			compatible = "syscon";
			reg = <0x0b011000 0x1000>;
		};

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp_spi1: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_default>;
			pinctrl-1 = <&spi1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi2: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_default>;
			pinctrl-1 = <&spi2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi3: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi3_default>;
			pinctrl-1 = <&spi3_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi4: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x600>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi4_default>;
			pinctrl-1 = <&spi4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi5: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x600>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi5_default>;
			pinctrl-1 = <&spi5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi6: spi@78ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078ba000 0x600>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi6_default>;
			pinctrl-1 = <&spi6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c2: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b6000 0x1000>;
			interrupts = <GIC_SPI 96 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c2_default>;
			pinctrl-1 = <&i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c4: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b8000 0x1000>;
			interrupts = <GIC_SPI 98 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c4_default>;
			pinctrl-1 = <&i2c4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c6: i2c@78ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78ba000 0x1000>;
			interrupts = <GIC_SPI 100 0>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c6_default>;
			pinctrl-1 = <&i2c6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		lpass: lpass@07708000 {
			status = "disabled";
			compatible = "qcom,lpass-cpu-apq8016";
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;

			clock-names = "ahbix-clk",
					"pcnoc-mport-clk",
					"pcnoc-sway-clk",
					"mi2s-bit-clk0",
					"mi2s-bit-clk1",
					"mi2s-bit-clk2",
					"mi2s-bit-clk3";
			#sound-dai-cells = <1>;

			interrupts = <0 160 0>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x07708000 0x10000>;
			reg-names = "lpass-lpaif";
		};

		sdhc_1: sdhci@07824000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			bus-width = <8>;
			non-removable;
			status = "disabled";
		};

		sdhc_2: sdhci@07864000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			bus-width = <4>;
			status = "disabled";
		};

		usb_dev: usb@78d9000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x78d9000 0x400>;
			dr_mode = "peripheral";
			interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
			usb-phy = <&usb_otg>;
			status = "disabled";
		};

		usb_host: ehci@78d9000 {
			compatible = "qcom,ehci-host";
			reg = <0x78d9000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
			usb-phy = <&usb_otg>;
			status = "disabled";
		};

		usb_otg: phy@78d9000 {
			compatible = "qcom,usb-otg-snps";
			reg = <0x78d9000 0x400>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;

			qcom,vdd-levels = <500000 1000000 1320000>;
			qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
			dr_mode = "peripheral";
			qcom,otg-control = <2>; // PMIC
			qcom,manual-pullup;

			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>,
				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
			clock-names = "iface", "core", "sleep";

			resets = <&gcc GCC_USB2A_PHY_BCR>,
				 <&gcc GCC_USB_HS_BCR>;
			reset-names = "phy", "link";
			status = "disabled";
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
		};

		timer@b020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xb020000 0x1000>;
			clock-frequency = <19200000>;

			frame@b021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb021000 0x1000>,
				      <0xb022000 0x1000>;
			};

			frame@b023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb023000 0x1000>;
				status = "disabled";
			};

			frame@b024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb024000 0x1000>;
				status = "disabled";
			};

			frame@b025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb025000 0x1000>;
				status = "disabled";
			};

			frame@b026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb026000 0x1000>;
				status = "disabled";
			};

			frame@b027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb027000 0x1000>;
				status = "disabled";
			};

			frame@b028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb028000 0x1000>;
				status = "disabled";
			};
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x200f000 0x001000>,
			      <0x2400000 0x400000>,
			      <0x2c00000 0x400000>,
			      <0x3800000 0x200000>,
			      <0x200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x00022000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8916";
				qcom,smd-channels = "rpm_requests";

				rpmcc: qcom,rpmcc {
					compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
					#clock-cells = <1>;
				};

				smd_rpm_regulators: pm8916-regulators {
					compatible = "qcom,rpm-pm8916-regulators";

					pm8916_s1: s1 {};
					pm8916_s3: s3 {};
					pm8916_s4: s4 {};

					pm8916_l1: l1 {};
					pm8916_l2: l2 {};
					pm8916_l3: l3 {};
					pm8916_l4: l4 {};
					pm8916_l5: l5 {};
					pm8916_l6: l6 {};
					pm8916_l7: l7 {};
					pm8916_l8: l8 {};
					pm8916_l9: l9 {};
					pm8916_l10: l10 {};
					pm8916_l11: l11 {};
					pm8916_l12: l12 {};
					pm8916_l13: l13 {};
					pm8916_l14: l14 {};
					pm8916_l15: l15 {};
					pm8916_l16: l16 {};
					pm8916_l17: l17 {};
					pm8916_l18: l18 {};
				};
			};
		};
	};
};

#include "msm8916-pins.dtsi"
Commit	Line	Data
57f0a7ea KG	1	/*
	2	* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <dt-bindings/interrupt-controller/arm-gic.h>
	15	#include <dt-bindings/clock/qcom,gcc-msm8916.h>
	16	#include <dt-bindings/reset/qcom,gcc-msm8916.h>
	17
	18	/ {
	19	model = "Qualcomm Technologies, Inc. MSM8916";
	20	compatible = "qcom,msm8916";
	21
	22	interrupt-parent = <&intc>;
	23
	24	#address-cells = <2>;
	25	#size-cells = <2>;
	26
c4da5a56 SK	27	aliases {
	28	sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
	29	sdhc2 = &sdhc_2; /* SDC2 SD card slot */
	30	};
57f0a7ea KG	31
	32	chosen { };
	33
	34	memory {
	35	device_type = "memory";
	36	/* We expect the bootloader to fill in the reg */
	37	reg = <0 0 0 0>;
	38	};
	39
a0ece657 AG	40	reserved-memory {
	41	#address-cells = <2>;
	42	#size-cells = <2>;
	43	ranges;
	44
	45	reserve_aligned@86000000 {
	46	reg = <0x0 0x86000000 0x0 0x0300000>;
	47	no-map;
	48	};
	49
	50	smem_mem: smem_region@86300000 {
	51	reg = <0x0 0x86300000 0x0 0x0100000>;
	52	no-map;
	53	};
	54	};
	55
57f0a7ea KG	56	cpus {
	57	#address-cells = <1>;
	58	#size-cells = <0>;
	59
	60	CPU0: cpu@0 {
	61	device_type = "cpu";
	62	compatible = "arm,cortex-a53", "arm,armv8";
	63	reg = <0x0>;
0a9bcf4e	64	next-level-cache = <&L2_0>;
57f0a7ea KG	65	};
	66
	67	CPU1: cpu@1 {
	68	device_type = "cpu";
	69	compatible = "arm,cortex-a53", "arm,armv8";
	70	reg = <0x1>;
0a9bcf4e	71	next-level-cache = <&L2_0>;
57f0a7ea KG	72	};
	73
	74	CPU2: cpu@2 {
	75	device_type = "cpu";
	76	compatible = "arm,cortex-a53", "arm,armv8";
	77	reg = <0x2>;
0a9bcf4e	78	next-level-cache = <&L2_0>;
57f0a7ea KG	79	};
	80
	81	CPU3: cpu@3 {
	82	device_type = "cpu";
	83	compatible = "arm,cortex-a53", "arm,armv8";
	84	reg = <0x3>;
0a9bcf4e SB	85	next-level-cache = <&L2_0>;
	86	};
	87
	88	L2_0: l2-cache {
	89	compatible = "cache";
	90	cache-level = <2>;
57f0a7ea KG	91	};
	92	};
	93
	94	timer {
	95	compatible = "arm,armv8-timer";
	96	interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	97	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	98	<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	99	<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	100	};
	101
f4fb6aea GD	102	clocks {
	103	xo_board: xo_board {
	104	compatible = "fixed-clock";
	105	#clock-cells = <0>;
	106	clock-frequency = <19200000>;
	107	};
	108
	109	sleep_clk: sleep_clk {
	110	compatible = "fixed-clock";
	111	#clock-cells = <0>;
	112	clock-frequency = <32768>;
	113	};
	114	};
	115
a0ece657 AG	116	smem {
	117	compatible = "qcom,smem";
	118
	119	memory-region = <&smem_mem>;
	120	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	121
	122	hwlocks = <&tcsr_mutex 3>;
	123	};
	124
57f0a7ea KG	125	soc: soc {
	126	#address-cells = <1>;
	127	#size-cells = <1>;
	128	ranges = <0 0 0 0xffffffff>;
	129	compatible = "simple-bus";
	130
366655c9 II	131	restart@4ab000 {
	132	compatible = "qcom,pshold";
	133	reg = <0x4ab000 0x4>;
	134	};
	135
a190a1ce	136	msmgpio: pinctrl@1000000 {
57f0a7ea KG	137	compatible = "qcom,msm8916-pinctrl";
	138	reg = <0x1000000 0x300000>;
	139	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	140	gpio-controller;
	141	#gpio-cells = <2>;
	142	interrupt-controller;
	143	#interrupt-cells = <2>;
57f0a7ea KG	144	};
57f0a7ea KG	145
886c73ba	146	gcc: clock-controller@1800000 {
57f0a7ea KG	147	compatible = "qcom,gcc-msm8916";
	148	#clock-cells = <1>;
	149	#reset-cells = <1>;
89c7e671	150	#power-domain-cells = <1>;
57f0a7ea KG	151	reg = <0x1800000 0x80000>;
	152	};
	153
a0ece657 AG	154	tcsr_mutex_regs: syscon@1905000 {
	155	compatible = "syscon";
	156	reg = <0x1905000 0x20000>;
	157	};
	158
	159	tcsr_mutex: hwlock {
	160	compatible = "qcom,tcsr-mutex";
	161	syscon = <&tcsr_mutex_regs 0 0x1000>;
	162	#hwlock-cells = <1>;
	163	};
	164
	165	rpm_msg_ram: memory@60000 {
	166	compatible = "qcom,rpm-msg-ram";
	167	reg = <0x60000 0x8000>;
	168	};
	169
9f43020d AG	170	blsp1_uart1: serial@78af000 {
	171	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	172	reg = <0x78af000 0x200>;
	173	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	174	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	175	clock-names = "core", "iface";
d66dd9e0 II	176	dmas = <&blsp_dma 1>, <&blsp_dma 0>;
d66dd9e0 II	177	dma-names = "rx", "tx";
9f43020d AG	178	status = "disabled";
	179	};
	180
8fd55d41 AG	181	apcs: syscon@b011000 {
	182	compatible = "syscon";
	183	reg = <0x0b011000 0x1000>;
	184	};
	185
57f0a7ea KG	186	blsp1_uart2: serial@78b0000 {
	187	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	188	reg = <0x78b0000 0x200>;
	189	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
	190	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	191	clock-names = "core", "iface";
d66dd9e0 II	192	dmas = <&blsp_dma 3>, <&blsp_dma 2>;
d66dd9e0 II	193	dma-names = "rx", "tx";
57f0a7ea KG	194	status = "disabled";
57f0a7ea KG	195	};
a0e5fb10 II	196
	197	blsp_dma: dma@7884000 {
	198	compatible = "qcom,bam-v1.7.0";
	199	reg = <0x07884000 0x23000>;
	200	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	201	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	202	clock-names = "bam_clk";
	203	#dma-cells = <1>;
	204	qcom,ee = <0>;
	205	status = "disabled";
	206	};
	207
	208	blsp_spi1: spi@78b5000 {
	209	compatible = "qcom,spi-qup-v2.2.1";
	210	reg = <0x078b5000 0x600>;
	211	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	212	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	213	<&gcc GCC_BLSP1_AHB_CLK>;
	214	clock-names = "core", "iface";
	215	dmas = <&blsp_dma 5>, <&blsp_dma 4>;
	216	dma-names = "rx", "tx";
	217	pinctrl-names = "default", "sleep";
	218	pinctrl-0 = <&spi1_default>;
	219	pinctrl-1 = <&spi1_sleep>;
	220	#address-cells = <1>;
	221	#size-cells = <0>;
	222	status = "disabled";
	223	};
	224
	225	blsp_spi2: spi@78b6000 {
	226	compatible = "qcom,spi-qup-v2.2.1";
	227	reg = <0x078b6000 0x600>;
	228	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	229	clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
	230	<&gcc GCC_BLSP1_AHB_CLK>;
	231	clock-names = "core", "iface";
	232	dmas = <&blsp_dma 7>, <&blsp_dma 6>;
	233	dma-names = "rx", "tx";
	234	pinctrl-names = "default", "sleep";
	235	pinctrl-0 = <&spi2_default>;
	236	pinctrl-1 = <&spi2_sleep>;
	237	#address-cells = <1>;
	238	#size-cells = <0>;
	239	status = "disabled";
	240	};
	241
	242	blsp_spi3: spi@78b7000 {
	243	compatible = "qcom,spi-qup-v2.2.1";
	244	reg = <0x078b7000 0x600>;
	245	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	246	clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
	247	<&gcc GCC_BLSP1_AHB_CLK>;
	248	clock-names = "core", "iface";
	249	dmas = <&blsp_dma 9>, <&blsp_dma 8>;
	250	dma-names = "rx", "tx";
	251	pinctrl-names = "default", "sleep";
	252	pinctrl-0 = <&spi3_default>;
	253	pinctrl-1 = <&spi3_sleep>;
	254	#address-cells = <1>;
	255	#size-cells = <0>;
	256	status = "disabled";
	257	};
	258
	259	blsp_spi4: spi@78b8000 {
260	compatible = "qcom,spi-qup-v2.2.1";
261	reg = <0x078b8000 0x600>;
262	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
263	clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
264	<&gcc GCC_BLSP1_AHB_CLK>;
265	clock-names = "core", "iface";
266	dmas = <&blsp_dma 11>, <&blsp_dma 10>;
267	dma-names = "rx", "tx";
268	pinctrl-names = "default", "sleep";
269	pinctrl-0 = <&spi4_default>;
270	pinctrl-1 = <&spi4_sleep>;
271	#address-cells = <1>;
272	#size-cells = <0>;
273	status = "disabled";
274	};
275
276	blsp_spi5: spi@78b9000 {
277	compatible = "qcom,spi-qup-v2.2.1";
278	reg = <0x078b9000 0x600>;
279	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
280	clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
281	<&gcc GCC_BLSP1_AHB_CLK>;
282	clock-names = "core", "iface";
283	dmas = <&blsp_dma 13>, <&blsp_dma 12>;
284	dma-names = "rx", "tx";
285	pinctrl-names = "default", "sleep";
286	pinctrl-0 = <&spi5_default>;
287	pinctrl-1 = <&spi5_sleep>;
288	#address-cells = <1>;
289	#size-cells = <0>;
290	status = "disabled";
291	};
292
293	blsp_spi6: spi@78ba000 {
294	compatible = "qcom,spi-qup-v2.2.1";
295	reg = <0x078ba000 0x600>;
296	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
297	clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
298	<&gcc GCC_BLSP1_AHB_CLK>;
299	clock-names = "core", "iface";
300	dmas = <&blsp_dma 15>, <&blsp_dma 14>;
301	dma-names = "rx", "tx";
302	pinctrl-names = "default", "sleep";
303	pinctrl-0 = <&spi6_default>;
304	pinctrl-1 = <&spi6_sleep>;
305	#address-cells = <1>;
306	#size-cells = <0>;
307	status = "disabled";
308	};
309
7f5b0921 SK	310	blsp_i2c2: i2c@78b6000 {
	311	compatible = "qcom,i2c-qup-v2.2.1";
	312	reg = <0x78b6000 0x1000>;
	313	interrupts = <GIC_SPI 96 0>;
	314	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	315	<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	316	clock-names = "iface", "core";
	317	pinctrl-names = "default", "sleep";
	318	pinctrl-0 = <&i2c2_default>;
	319	pinctrl-1 = <&i2c2_sleep>;
	320	#address-cells = <1>;
	321	#size-cells = <0>;
	322	status = "disabled";
	323	};
	324
a0e5fb10 II	325	blsp_i2c4: i2c@78b8000 {
	326	compatible = "qcom,i2c-qup-v2.2.1";
	327	reg = <0x78b8000 0x1000>;
	328	interrupts = <GIC_SPI 98 0>;
	329	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	330	<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
	331	clock-names = "iface", "core";
	332	pinctrl-names = "default", "sleep";
	333	pinctrl-0 = <&i2c4_default>;
	334	pinctrl-1 = <&i2c4_sleep>;
	335	#address-cells = <1>;
	336	#size-cells = <0>;
	337	status = "disabled";
	338	};
c4da5a56	339
7f5b0921 SK	340	blsp_i2c6: i2c@78ba000 {
	341	compatible = "qcom,i2c-qup-v2.2.1";
	342	reg = <0x78ba000 0x1000>;
	343	interrupts = <GIC_SPI 100 0>;
	344	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	345	<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
	346	clock-names = "iface", "core";
	347	pinctrl-names = "default", "sleep";
	348	pinctrl-0 = <&i2c6_default>;
	349	pinctrl-1 = <&i2c6_sleep>;
	350	#address-cells = <1>;
	351	#size-cells = <0>;
	352	status = "disabled";
	353	};
	354
3761a361 SK	355	lpass: lpass@07708000 {
	356	status = "disabled";
	357	compatible = "qcom,lpass-cpu-apq8016";
	358	clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
	359	<&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
	360	<&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
	361	<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
	362	<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
	363	<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
	364	<&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
	365
	366	clock-names = "ahbix-clk",
	367	"pcnoc-mport-clk",
	368	"pcnoc-sway-clk",
	369	"mi2s-bit-clk0",
	370	"mi2s-bit-clk1",
	371	"mi2s-bit-clk2",
	372	"mi2s-bit-clk3";
	373	#sound-dai-cells = <1>;
	374
	375	interrupts = <0 160 0>;
	376	interrupt-names = "lpass-irq-lpaif";
	377	reg = <0x07708000 0x10000>;
	378	reg-names = "lpass-lpaif";
	379	};
	380
c4da5a56 SK	381	sdhc_1: sdhci@07824000 {
	382	compatible = "qcom,sdhci-msm-v4";
	383	reg = <0x07824900 0x11c>, <0x07824000 0x800>;
	384	reg-names = "hc_mem", "core_mem";
	385
	386	interrupts = <0 123 0>, <0 138 0>;
	387	interrupt-names = "hc_irq", "pwr_irq";
	388	clocks = <&gcc GCC_SDCC1_APPS_CLK>,
	389	<&gcc GCC_SDCC1_AHB_CLK>;
	390	clock-names = "core", "iface";
	391	bus-width = <8>;
	392	non-removable;
	393	status = "disabled";
	394	};
	395
	396	sdhc_2: sdhci@07864000 {
	397	compatible = "qcom,sdhci-msm-v4";
	398	reg = <0x07864900 0x11c>, <0x07864000 0x800>;
	399	reg-names = "hc_mem", "core_mem";
	400
	401	interrupts = <0 125 0>, <0 221 0>;
	402	interrupt-names = "hc_irq", "pwr_irq";
	403	clocks = <&gcc GCC_SDCC2_APPS_CLK>,
	404	<&gcc GCC_SDCC2_AHB_CLK>;
	405	clock-names = "core", "iface";
	406	bus-width = <4>;
	407	status = "disabled";
	408	};
59600865 II	409
	410	usb_dev: usb@78d9000 {
	411	compatible = "qcom,ci-hdrc";
	412	reg = <0x78d9000 0x400>;
	413	dr_mode = "peripheral";
	414	interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
	415	usb-phy = <&usb_otg>;
	416	status = "disabled";
	417	};
	418
	419	usb_host: ehci@78d9000 {
	420	compatible = "qcom,ehci-host";
	421	reg = <0x78d9000 0x400>;
	422	interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
	423	usb-phy = <&usb_otg>;
	424	status = "disabled";
	425	};
	426
	427	usb_otg: phy@78d9000 {
	428	compatible = "qcom,usb-otg-snps";
	429	reg = <0x78d9000 0x400>;
	430	interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
	431	<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
	432
a7b2466c	433	qcom,vdd-levels = <500000 1000000 1320000>;
59600865 II	434	qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
	435	dr_mode = "peripheral";
	436	qcom,otg-control = <2>; // PMIC
2a0bc810	437	qcom,manual-pullup;
59600865 II	438
	439	clocks = <&gcc GCC_USB_HS_AHB_CLK>,
	440	<&gcc GCC_USB_HS_SYSTEM_CLK>,
	441	<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
	442	clock-names = "iface", "core", "sleep";
	443
	444	resets = <&gcc GCC_USB2A_PHY_BCR>,
	445	<&gcc GCC_USB_HS_BCR>;
	446	reset-names = "phy", "link";
	447	status = "disabled";
	448	};
57f0a7ea KG	449
	450	intc: interrupt-controller@b000000 {
	451	compatible = "qcom,msm-qgic2";
	452	interrupt-controller;
	453	#interrupt-cells = <3>;
	454	reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
	455	};
	456
	457	timer@b020000 {
	458	#address-cells = <1>;
	459	#size-cells = <1>;
	460	ranges;
	461	compatible = "arm,armv7-timer-mem";
	462	reg = <0xb020000 0x1000>;
	463	clock-frequency = <19200000>;
	464
	465	frame@b021000 {
	466	frame-number = <0>;
	467	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	468	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	469	reg = <0xb021000 0x1000>,
	470	<0xb022000 0x1000>;
	471	};
	472
	473	frame@b023000 {
	474	frame-number = <1>;
	475	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	476	reg = <0xb023000 0x1000>;
	477	status = "disabled";
	478	};
	479
	480	frame@b024000 {
	481	frame-number = <2>;
	482	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	483	reg = <0xb024000 0x1000>;
	484	status = "disabled";
	485	};
	486
	487	frame@b025000 {
	488	frame-number = <3>;
	489	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	490	reg = <0xb025000 0x1000>;
	491	status = "disabled";
	492	};
	493
	494	frame@b026000 {
	495	frame-number = <4>;
	496	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	497	reg = <0xb026000 0x1000>;
	498	status = "disabled";
	499	};
	500
	501	frame@b027000 {
	502	frame-number = <5>;
	503	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	504	reg = <0xb027000 0x1000>;
	505	status = "disabled";
	506	};
	507
	508	frame@b028000 {
	509	frame-number = <6>;
	510	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	511	reg = <0xb028000 0x1000>;
	512	status = "disabled";
513	};
514	};
232461ff II	515
	516	spmi_bus: spmi@200f000 {
	517	compatible = "qcom,spmi-pmic-arb";
	518	reg = <0x200f000 0x001000>,
	519	<0x2400000 0x400000>,
	520	<0x2c00000 0x400000>,
	521	<0x3800000 0x200000>,
	522	<0x200a000 0x002100>;
	523	reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
	524	interrupt-names = "periph_irq";
	525	interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
	526	qcom,ee = <0>;
	527	qcom,channel = <0>;
	528	#address-cells = <2>;
	529	#size-cells = <0>;
	530	interrupt-controller;
	531	#interrupt-cells = <4>;
	532	};
f6d24bf3 SV	533
	534	rng@22000 {
	535	compatible = "qcom,prng";
	536	reg = <0x00022000 0x200>;
	537	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	538	clock-names = "core";
	539	};
57f0a7ea	540	};
8fd55d41 AG	541
	542	smd {
	543	compatible = "qcom,smd";
	544
	545	rpm {
	546	interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
	547	qcom,ipc = <&apcs 8 0>;
	548	qcom,smd-edge = <15>;
	549
	550	rpm_requests {
	551	compatible = "qcom,rpm-msm8916";
	552	qcom,smd-channels = "rpm_requests";
9e1dfb85	553
e2841db7 GD	554	rpmcc: qcom,rpmcc {
	555	compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
	556	#clock-cells = <1>;
	557	};
	558
0ba7da26	559	smd_rpm_regulators: pm8916-regulators {
9e1dfb85 AG	560	compatible = "qcom,rpm-pm8916-regulators";
	561
	562	pm8916_s1: s1 {};
9e1dfb85 AG	563	pm8916_s3: s3 {};
	564	pm8916_s4: s4 {};
	565
	566	pm8916_l1: l1 {};
	567	pm8916_l2: l2 {};
	568	pm8916_l3: l3 {};
	569	pm8916_l4: l4 {};
	570	pm8916_l5: l5 {};
	571	pm8916_l6: l6 {};
	572	pm8916_l7: l7 {};
	573	pm8916_l8: l8 {};
	574	pm8916_l9: l9 {};
	575	pm8916_l10: l10 {};
	576	pm8916_l11: l11 {};
	577	pm8916_l12: l12 {};
	578	pm8916_l13: l13 {};
	579	pm8916_l14: l14 {};
	580	pm8916_l15: l15 {};
	581	pm8916_l16: l16 {};
	582	pm8916_l17: l17 {};
	583	pm8916_l18: l18 {};
	584	};
8fd55d41 AG	585	};
	586	};
	587	};
57f0a7ea	588	};
1b08a582 II	589
1b08a582 II	590	#include "msm8916-pins.dtsi"