[linux-2.6-block.git] / arch / arm64 / boot / dts / nvidia / tegra186.dtsi

// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>

/ {
	compatible = "nvidia,tegra186";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	gpio: gpio@2200000 {
		compatible = "nvidia,tegra186-gpio";
		reg-names = "security", "gpio";
		reg = <0x0 0x2200000 0x0 0x10000>,
		      <0x0 0x2210000 0x0 0x10000>;
		interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
		#interrupt-cells = <2>;
		interrupt-controller;
		#gpio-cells = <2>;
		gpio-controller;
	};

	ethernet@2490000 {
		compatible = "nvidia,tegra186-eqos",
			     "snps,dwc-qos-ethernet-4.10";
		reg = <0x0 0x02490000 0x0 0x10000>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
			     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
			     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
			     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
			     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
			     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
			     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
			     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
			 <&bpmp TEGRA186_CLK_EQOS_RX>,
			 <&bpmp TEGRA186_CLK_EQOS_TX>,
			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
		clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
		resets = <&bpmp TEGRA186_RESET_EQOS>;
		reset-names = "eqos";
		status = "disabled";

		snps,write-requests = <1>;
		snps,read-requests = <3>;
		snps,burst-map = <0x7>;
		snps,txpbl = <32>;
		snps,rxpbl = <8>;
	};

	uarta: serial@3100000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03100000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTA>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTA>;
		reset-names = "serial";
		status = "disabled";
	};

	uartb: serial@3110000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03110000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTB>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTB>;
		reset-names = "serial";
		status = "disabled";
	};

	uartd: serial@3130000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03130000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTD>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTD>;
		reset-names = "serial";
		status = "disabled";
	};

	uarte: serial@3140000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03140000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTE>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTE>;
		reset-names = "serial";
		status = "disabled";
	};

	uartf: serial@3150000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x03150000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTF>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTF>;
		reset-names = "serial";
		status = "disabled";
	};

	gen1_i2c: i2c@3160000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x03160000 0x0 0x10000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C1>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C1>;
		reset-names = "i2c";
		status = "disabled";
	};

	cam_i2c: i2c@3180000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x03180000 0x0 0x10000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C3>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C3>;
		reset-names = "i2c";
		status = "disabled";
	};

	/* shares pads with dpaux1 */
	dp_aux_ch1_i2c: i2c@3190000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x03190000 0x0 0x10000>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C4>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C4>;
		reset-names = "i2c";
		status = "disabled";
	};

	/* controlled by BPMP, should not be enabled */
	pwr_i2c: i2c@31a0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x031a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C5>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C5>;
		reset-names = "i2c";
		status = "disabled";
	};

	/* shares pads with dpaux0 */
	dp_aux_ch0_i2c: i2c@31b0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x031b0000 0x0 0x10000>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C6>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C6>;
		reset-names = "i2c";
		status = "disabled";
	};

	gen7_i2c: i2c@31c0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x031c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C7>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C7>;
		reset-names = "i2c";
		status = "disabled";
	};

	gen9_i2c: i2c@31e0000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x031e0000 0x0 0x10000>;
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C9>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C9>;
		reset-names = "i2c";
		status = "disabled";
	};

	sdmmc1: sdhci@3400000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03400000 0x0 0x10000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
		clock-names = "sdhci";
		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
		reset-names = "sdhci";
		status = "disabled";
	};

	sdmmc2: sdhci@3420000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03420000 0x0 0x10000>;
		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
		clock-names = "sdhci";
		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
		reset-names = "sdhci";
		status = "disabled";
	};

	sdmmc3: sdhci@3440000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03440000 0x0 0x10000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
		clock-names = "sdhci";
		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
		reset-names = "sdhci";
		status = "disabled";
	};

	sdmmc4: sdhci@3460000 {
		compatible = "nvidia,tegra186-sdhci";
		reg = <0x0 0x03460000 0x0 0x10000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
		clock-names = "sdhci";
		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
		reset-names = "sdhci";
		status = "disabled";
	};

	gic: interrupt-controller@3881000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x03881000 0x0 0x1000>,
		      <0x0 0x03882000 0x0 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

	hsp_top0: hsp@3c00000 {
		compatible = "nvidia,tegra186-hsp";
		reg = <0x0 0x03c00000 0x0 0xa0000>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "doorbell";
		#mbox-cells = <2>;
		status = "disabled";
	};

	gen2_i2c: i2c@c240000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x0c240000 0x0 0x10000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C2>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C2>;
		reset-names = "i2c";
		status = "disabled";
	};

	gen8_i2c: i2c@c250000 {
		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x0c250000 0x0 0x10000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&bpmp TEGRA186_CLK_I2C8>;
		clock-names = "div-clk";
		resets = <&bpmp TEGRA186_RESET_I2C8>;
		reset-names = "i2c";
		status = "disabled";
	};

	uartc: serial@c280000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x0c280000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTC>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTC>;
		reset-names = "serial";
		status = "disabled";
	};

	uartg: serial@c290000 {
		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x0c290000 0x0 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA186_CLK_UARTG>;
		clock-names = "serial";
		resets = <&bpmp TEGRA186_RESET_UARTG>;
		reset-names = "serial";
		status = "disabled";
	};

	gpio_aon: gpio@c2f0000 {
		compatible = "nvidia,tegra186-gpio-aon";
		reg-names = "security", "gpio";
		reg = <0x0 0xc2f0000 0x0 0x1000>,
		      <0x0 0xc2f1000 0x0 0x1000>;
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	pmc@c360000 {
		compatible = "nvidia,tegra186-pmc";
		reg = <0 0x0c360000 0 0x10000>,
		      <0 0x0c370000 0 0x10000>,
		      <0 0x0c380000 0 0x10000>,
		      <0 0x0c390000 0 0x10000>;
		reg-names = "pmc", "wake", "aotag", "scratch";
	};

	ccplex@e000000 {
		compatible = "nvidia,tegra186-ccplex-cluster";
		reg = <0x0 0x0e000000 0x0 0x3fffff>;

		nvidia,bpmp = <&bpmp>;
	};

	gpu@17000000 {
		compatible = "nvidia,gp10b";
		reg = <0x0 0x17000000 0x0 0x1000000>,
		      <0x0 0x18000000 0x0 0x1000000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "stall", "nonstall";

		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
			 <&bpmp TEGRA186_CLK_GPU>;
		clock-names = "gpu", "pwr";
		resets = <&bpmp TEGRA186_RESET_GPU>;
		reset-names = "gpu";
		status = "disabled";

		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
	};

	sysram@30000000 {
		compatible = "nvidia,tegra186-sysram", "mmio-sram";
		reg = <0x0 0x30000000 0x0 0x50000>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;

		cpu_bpmp_tx: shmem@4e000 {
			compatible = "nvidia,tegra186-bpmp-shmem";
			reg = <0x0 0x4e000 0x0 0x1000>;
			label = "cpu-bpmp-tx";
			pool;
		};

		cpu_bpmp_rx: shmem@4f000 {
			compatible = "nvidia,tegra186-bpmp-shmem";
			reg = <0x0 0x4f000 0x0 0x1000>;
			label = "cpu-bpmp-rx";
			pool;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "nvidia,tegra186-denver", "arm,armv8";
			device_type = "cpu";
			reg = <0x000>;
		};

		cpu@1 {
			compatible = "nvidia,tegra186-denver", "arm,armv8";
			device_type = "cpu";
			reg = <0x001>;
		};

		cpu@2 {
			compatible = "arm,cortex-a57", "arm,armv8";
			device_type = "cpu";
			reg = <0x100>;
		};

		cpu@3 {
			compatible = "arm,cortex-a57", "arm,armv8";
			device_type = "cpu";
			reg = <0x101>;
		};

		cpu@4 {
			compatible = "arm,cortex-a57", "arm,armv8";
			device_type = "cpu";
			reg = <0x102>;
		};

		cpu@5 {
			compatible = "arm,cortex-a57", "arm,armv8";
			device_type = "cpu";
			reg = <0x103>;
		};
	};

	bpmp: bpmp {
		compatible = "nvidia,tegra186-bpmp";
		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
				    TEGRA_HSP_DB_MASTER_BPMP>;
		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
		#clock-cells = <1>;
		#reset-cells = <1>;

		bpmp_i2c: i2c {
			compatible = "nvidia,tegra186-bpmp-i2c";
			nvidia,bpmp-bus-id = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&gic>;
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
c58f5f88	2	#include <dt-bindings/clock/tegra186-clock.h>
fc4bb754	3	#include <dt-bindings/gpio/tegra186-gpio.h>
39cb62cb	4	#include <dt-bindings/interrupt-controller/arm-gic.h>
5edcebb9	5	#include <dt-bindings/mailbox/tegra186-hsp.h>
dfd7a384	6	#include <dt-bindings/power/tegra186-powergate.h>
7bcf2664	7	#include <dt-bindings/reset/tegra186-reset.h>
39cb62cb JL	8
	9	/ {
	10	compatible = "nvidia,tegra186";
	11	interrupt-parent = <&gic>;
	12	#address-cells = <2>;
	13	#size-cells = <2>;
	14
fc4bb754 TR	15	gpio: gpio@2200000 {
	16	compatible = "nvidia,tegra186-gpio";
	17	reg-names = "security", "gpio";
	18	reg = <0x0 0x2200000 0x0 0x10000>,
	19	<0x0 0x2210000 0x0 0x10000>;
	20	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	21	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	22	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	23	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	24	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	25	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	26	#interrupt-cells = <2>;
	27	interrupt-controller;
	28	#gpio-cells = <2>;
	29	gpio-controller;
	30	};
	31
0caafbde TR	32	ethernet@2490000 {
	33	compatible = "nvidia,tegra186-eqos",
	34	"snps,dwc-qos-ethernet-4.10";
	35	reg = <0x0 0x02490000 0x0 0x10000>;
	36	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
	37	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
	38	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
	39	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
	40	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
	41	<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
	42	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
	43	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
	44	<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
	45	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
	46	clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
	47	<&bpmp TEGRA186_CLK_EQOS_AXI>,
	48	<&bpmp TEGRA186_CLK_EQOS_RX>,
	49	<&bpmp TEGRA186_CLK_EQOS_TX>,
	50	<&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
	51	clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
	52	resets = <&bpmp TEGRA186_RESET_EQOS>;
	53	reset-names = "eqos";
	54	status = "disabled";
	55
	56	snps,write-requests = <1>;
	57	snps,read-requests = <3>;
	58	snps,burst-map = <0x7>;
	59	snps,txpbl = <32>;
	60	snps,rxpbl = <8>;
	61	};
	62
39cb62cb JL	63	uarta: serial@3100000 {
	64	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	65	reg = <0x0 0x03100000 0x0 0x40>;
	66	reg-shift = <2>;
	67	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	68	clocks = <&bpmp TEGRA186_CLK_UARTA>;
a7a77e2e	69	clock-names = "serial";
7bcf2664	70	resets = <&bpmp TEGRA186_RESET_UARTA>;
a7a77e2e TR	71	reset-names = "serial";
	72	status = "disabled";
	73	};
	74
	75	uartb: serial@3110000 {
	76	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	77	reg = <0x0 0x03110000 0x0 0x40>;
	78	reg-shift = <2>;
	79	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	80	clocks = <&bpmp TEGRA186_CLK_UARTB>;
a7a77e2e	81	clock-names = "serial";
7bcf2664	82	resets = <&bpmp TEGRA186_RESET_UARTB>;
a7a77e2e TR	83	reset-names = "serial";
	84	status = "disabled";
	85	};
	86
	87	uartd: serial@3130000 {
	88	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	89	reg = <0x0 0x03130000 0x0 0x40>;
	90	reg-shift = <2>;
	91	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	92	clocks = <&bpmp TEGRA186_CLK_UARTD>;
a7a77e2e	93	clock-names = "serial";
7bcf2664	94	resets = <&bpmp TEGRA186_RESET_UARTD>;
a7a77e2e TR	95	reset-names = "serial";
	96	status = "disabled";
	97	};
	98
	99	uarte: serial@3140000 {
	100	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	101	reg = <0x0 0x03140000 0x0 0x40>;
	102	reg-shift = <2>;
	103	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	104	clocks = <&bpmp TEGRA186_CLK_UARTE>;
a7a77e2e	105	clock-names = "serial";
7bcf2664	106	resets = <&bpmp TEGRA186_RESET_UARTE>;
a7a77e2e TR	107	reset-names = "serial";
	108	status = "disabled";
	109	};
	110
	111	uartf: serial@3150000 {
	112	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	113	reg = <0x0 0x03150000 0x0 0x40>;
	114	reg-shift = <2>;
	115	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	116	clocks = <&bpmp TEGRA186_CLK_UARTF>;
a7a77e2e	117	clock-names = "serial";
7bcf2664	118	resets = <&bpmp TEGRA186_RESET_UARTF>;
a7a77e2e	119	reset-names = "serial";
39cb62cb JL	120	status = "disabled";
	121	};
	122
40cc83b3 TR	123	gen1_i2c: i2c@3160000 {
	124	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	125	reg = <0x0 0x03160000 0x0 0x10000>;
	126	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	127	#address-cells = <1>;
	128	#size-cells = <0>;
c58f5f88	129	clocks = <&bpmp TEGRA186_CLK_I2C1>;
40cc83b3	130	clock-names = "div-clk";
7bcf2664	131	resets = <&bpmp TEGRA186_RESET_I2C1>;
40cc83b3 TR	132	reset-names = "i2c";
	133	status = "disabled";
	134	};
	135
	136	cam_i2c: i2c@3180000 {
	137	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	138	reg = <0x0 0x03180000 0x0 0x10000>;
	139	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	140	#address-cells = <1>;
	141	#size-cells = <0>;
c58f5f88	142	clocks = <&bpmp TEGRA186_CLK_I2C3>;
40cc83b3	143	clock-names = "div-clk";
7bcf2664	144	resets = <&bpmp TEGRA186_RESET_I2C3>;
40cc83b3 TR	145	reset-names = "i2c";
	146	status = "disabled";
	147	};
	148
	149	/* shares pads with dpaux1 */
	150	dp_aux_ch1_i2c: i2c@3190000 {
	151	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	152	reg = <0x0 0x03190000 0x0 0x10000>;
	153	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	154	#address-cells = <1>;
	155	#size-cells = <0>;
c58f5f88	156	clocks = <&bpmp TEGRA186_CLK_I2C4>;
40cc83b3	157	clock-names = "div-clk";
7bcf2664	158	resets = <&bpmp TEGRA186_RESET_I2C4>;
40cc83b3 TR	159	reset-names = "i2c";
	160	status = "disabled";
	161	};
	162
	163	/* controlled by BPMP, should not be enabled */
	164	pwr_i2c: i2c@31a0000 {
	165	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	166	reg = <0x0 0x031a0000 0x0 0x10000>;
	167	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	168	#address-cells = <1>;
	169	#size-cells = <0>;
c58f5f88	170	clocks = <&bpmp TEGRA186_CLK_I2C5>;
40cc83b3	171	clock-names = "div-clk";
7bcf2664	172	resets = <&bpmp TEGRA186_RESET_I2C5>;
40cc83b3 TR	173	reset-names = "i2c";
	174	status = "disabled";
	175	};
	176
	177	/* shares pads with dpaux0 */
	178	dp_aux_ch0_i2c: i2c@31b0000 {
	179	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	180	reg = <0x0 0x031b0000 0x0 0x10000>;
	181	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	182	#address-cells = <1>;
	183	#size-cells = <0>;
c58f5f88	184	clocks = <&bpmp TEGRA186_CLK_I2C6>;
40cc83b3	185	clock-names = "div-clk";
7bcf2664	186	resets = <&bpmp TEGRA186_RESET_I2C6>;
40cc83b3 TR	187	reset-names = "i2c";
	188	status = "disabled";
	189	};
	190
	191	gen7_i2c: i2c@31c0000 {
	192	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	193	reg = <0x0 0x031c0000 0x0 0x10000>;
	194	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	195	#address-cells = <1>;
	196	#size-cells = <0>;
c58f5f88	197	clocks = <&bpmp TEGRA186_CLK_I2C7>;
40cc83b3	198	clock-names = "div-clk";
7bcf2664	199	resets = <&bpmp TEGRA186_RESET_I2C7>;
40cc83b3 TR	200	reset-names = "i2c";
	201	status = "disabled";
	202	};
	203
	204	gen9_i2c: i2c@31e0000 {
	205	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	206	reg = <0x0 0x031e0000 0x0 0x10000>;
	207	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
	208	#address-cells = <1>;
	209	#size-cells = <0>;
c58f5f88	210	clocks = <&bpmp TEGRA186_CLK_I2C9>;
40cc83b3	211	clock-names = "div-clk";
7bcf2664	212	resets = <&bpmp TEGRA186_RESET_I2C9>;
40cc83b3 TR	213	reset-names = "i2c";
	214	status = "disabled";
	215	};
	216
99425dfd TR	217	sdmmc1: sdhci@3400000 {
	218	compatible = "nvidia,tegra186-sdhci";
	219	reg = <0x0 0x03400000 0x0 0x10000>;
	220	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	221	clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
99425dfd	222	clock-names = "sdhci";
7bcf2664	223	resets = <&bpmp TEGRA186_RESET_SDMMC1>;
99425dfd TR	224	reset-names = "sdhci";
	225	status = "disabled";
	226	};
	227
	228	sdmmc2: sdhci@3420000 {
	229	compatible = "nvidia,tegra186-sdhci";
	230	reg = <0x0 0x03420000 0x0 0x10000>;
	231	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	232	clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
99425dfd	233	clock-names = "sdhci";
7bcf2664	234	resets = <&bpmp TEGRA186_RESET_SDMMC2>;
99425dfd TR	235	reset-names = "sdhci";
	236	status = "disabled";
	237	};
	238
	239	sdmmc3: sdhci@3440000 {
	240	compatible = "nvidia,tegra186-sdhci";
	241	reg = <0x0 0x03440000 0x0 0x10000>;
	242	interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	243	clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
99425dfd	244	clock-names = "sdhci";
7bcf2664	245	resets = <&bpmp TEGRA186_RESET_SDMMC3>;
99425dfd TR	246	reset-names = "sdhci";
	247	status = "disabled";
	248	};
	249
	250	sdmmc4: sdhci@3460000 {
	251	compatible = "nvidia,tegra186-sdhci";
	252	reg = <0x0 0x03460000 0x0 0x10000>;
	253	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	254	clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
99425dfd	255	clock-names = "sdhci";
7bcf2664	256	resets = <&bpmp TEGRA186_RESET_SDMMC4>;
99425dfd TR	257	reset-names = "sdhci";
	258	status = "disabled";
	259	};
	260
39cb62cb JL	261	gic: interrupt-controller@3881000 {
	262	compatible = "arm,gic-400";
	263	#interrupt-cells = <3>;
	264	interrupt-controller;
	265	reg = <0x0 0x03881000 0x0 0x1000>,
	266	<0x0 0x03882000 0x0 0x2000>;
	267	interrupts = <GIC_PPI 9
	268	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	269	interrupt-parent = <&gic>;
	270	};
	271
	272	hsp_top0: hsp@3c00000 {
	273	compatible = "nvidia,tegra186-hsp";
	274	reg = <0x0 0x03c00000 0x0 0xa0000>;
	275	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	276	interrupt-names = "doorbell";
	277	#mbox-cells = <2>;
	278	status = "disabled";
	279	};
	280
40cc83b3 TR	281	gen2_i2c: i2c@c240000 {
	282	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	283	reg = <0x0 0x0c240000 0x0 0x10000>;
	284	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	285	#address-cells = <1>;
	286	#size-cells = <0>;
c58f5f88	287	clocks = <&bpmp TEGRA186_CLK_I2C2>;
40cc83b3	288	clock-names = "div-clk";
7bcf2664	289	resets = <&bpmp TEGRA186_RESET_I2C2>;
40cc83b3 TR	290	reset-names = "i2c";
	291	status = "disabled";
	292	};
	293
	294	gen8_i2c: i2c@c250000 {
	295	compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
	296	reg = <0x0 0x0c250000 0x0 0x10000>;
	297	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	298	#address-cells = <1>;
	299	#size-cells = <0>;
c58f5f88	300	clocks = <&bpmp TEGRA186_CLK_I2C8>;
40cc83b3	301	clock-names = "div-clk";
7bcf2664	302	resets = <&bpmp TEGRA186_RESET_I2C8>;
40cc83b3 TR	303	reset-names = "i2c";
	304	status = "disabled";
	305	};
	306
a7a77e2e TR	307	uartc: serial@c280000 {
	308	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	309	reg = <0x0 0x0c280000 0x0 0x40>;
	310	reg-shift = <2>;
	311	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	312	clocks = <&bpmp TEGRA186_CLK_UARTC>;
a7a77e2e	313	clock-names = "serial";
7bcf2664	314	resets = <&bpmp TEGRA186_RESET_UARTC>;
a7a77e2e TR	315	reset-names = "serial";
	316	status = "disabled";
	317	};
	318
	319	uartg: serial@c290000 {
	320	compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
	321	reg = <0x0 0x0c290000 0x0 0x40>;
	322	reg-shift = <2>;
	323	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
c58f5f88	324	clocks = <&bpmp TEGRA186_CLK_UARTG>;
a7a77e2e	325	clock-names = "serial";
7bcf2664	326	resets = <&bpmp TEGRA186_RESET_UARTG>;
a7a77e2e TR	327	reset-names = "serial";
	328	status = "disabled";
	329	};
	330
fc4bb754 TR	331	gpio_aon: gpio@c2f0000 {
	332	compatible = "nvidia,tegra186-gpio-aon";
	333	reg-names = "security", "gpio";
	334	reg = <0x0 0xc2f0000 0x0 0x1000>,
	335	<0x0 0xc2f1000 0x0 0x1000>;
	336	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	337	gpio-controller;
	338	#gpio-cells = <2>;
	339	interrupt-controller;
	340	#interrupt-cells = <2>;
	341	};
	342
73bf90d4 TR	343	pmc@c360000 {
	344	compatible = "nvidia,tegra186-pmc";
	345	reg = <0 0x0c360000 0 0x10000>,
	346	<0 0x0c370000 0 0x10000>,
	347	<0 0x0c380000 0 0x10000>,
	348	<0 0x0c390000 0 0x10000>;
	349	reg-names = "pmc", "wake", "aotag", "scratch";
	350	};
	351
7b7ef494 MP	352	ccplex@e000000 {
	353	compatible = "nvidia,tegra186-ccplex-cluster";
	354	reg = <0x0 0x0e000000 0x0 0x3fffff>;
	355
	356	nvidia,bpmp = <&bpmp>;
	357	};
	358
dfd7a384 AC	359	gpu@17000000 {
	360	compatible = "nvidia,gp10b";
	361	reg = <0x0 0x17000000 0x0 0x1000000>,
	362	<0x0 0x18000000 0x0 0x1000000>;
	363	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
	364	GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	365	interrupt-names = "stall", "nonstall";
	366
	367	clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
	368	<&bpmp TEGRA186_CLK_GPU>;
	369	clock-names = "gpu", "pwr";
	370	resets = <&bpmp TEGRA186_RESET_GPU>;
	371	reset-names = "gpu";
	372	status = "disabled";
	373
	374	power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
	375	};
	376
39cb62cb JL	377	sysram@30000000 {
	378	compatible = "nvidia,tegra186-sysram", "mmio-sram";
	379	reg = <0x0 0x30000000 0x0 0x50000>;
	380	#address-cells = <2>;
	381	#size-cells = <2>;
	382	ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
	383
	384	cpu_bpmp_tx: shmem@4e000 {
	385	compatible = "nvidia,tegra186-bpmp-shmem";
	386	reg = <0x0 0x4e000 0x0 0x1000>;
	387	label = "cpu-bpmp-tx";
	388	pool;
	389	};
	390
	391	cpu_bpmp_rx: shmem@4f000 {
	392	compatible = "nvidia,tegra186-bpmp-shmem";
	393	reg = <0x0 0x4f000 0x0 0x1000>;
	394	label = "cpu-bpmp-rx";
	395	pool;
	396	};
	397	};
	398
cd6fe32e TR	399	cpus {
	400	#address-cells = <1>;
	401	#size-cells = <0>;
	402
	403	cpu@0 {
	404	compatible = "nvidia,tegra186-denver", "arm,armv8";
	405	device_type = "cpu";
	406	reg = <0x000>;
	407	};
	408
	409	cpu@1 {
	410	compatible = "nvidia,tegra186-denver", "arm,armv8";
	411	device_type = "cpu";
	412	reg = <0x001>;
	413	};
	414
	415	cpu@2 {
	416	compatible = "arm,cortex-a57", "arm,armv8";
	417	device_type = "cpu";
	418	reg = <0x100>;
	419	};
	420
	421	cpu@3 {
	422	compatible = "arm,cortex-a57", "arm,armv8";
	423	device_type = "cpu";
	424	reg = <0x101>;
	425	};
	426
	427	cpu@4 {
	428	compatible = "arm,cortex-a57", "arm,armv8";
	429	device_type = "cpu";
	430	reg = <0x102>;
	431	};
	432
	433	cpu@5 {
	434	compatible = "arm,cortex-a57", "arm,armv8";
	435	device_type = "cpu";
	436	reg = <0x103>;
	437	};
	438	};
	439
39cb62cb JL	440	bpmp: bpmp {
39cb62cb JL	441	compatible = "nvidia,tegra186-bpmp";
5edcebb9 TR	442	mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
5edcebb9 TR	443	TEGRA_HSP_DB_MASTER_BPMP>;
39cb62cb JL	444	shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
	445	#clock-cells = <1>;
	446	#reset-cells = <1>;
	447
	448	bpmp_i2c: i2c {
	449	compatible = "nvidia,tegra186-bpmp-i2c";
	450	nvidia,bpmp-bus-id = <5>;
	451	#address-cells = <1>;
	452	#size-cells = <0>;
	453	status = "disabled";
	454	};
	455	};
	456
	457	timer {
	458	compatible = "arm,armv8-timer";
	459	interrupts = <GIC_PPI 13
	460	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	461	<GIC_PPI 14
	462	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	463	<GIC_PPI 11
	464	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	465	<GIC_PPI 10
	466	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	467	interrupt-parent = <&gic>;
	468	};
	469	};