[linux-2.6-block.git] / arch / arm64 / boot / dts / marvell / armada-ap806.dtsi

/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Device Tree file for Marvell Armada AP806.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/dts-v1/;

/ {
	model = "Marvell Armada AP806";
	compatible = "marvell,armada-ap806";
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};


	ap806 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xf0000000 0x1000000>;

			gic: interrupt-controller@210000 {
				compatible = "arm,gic-400";
				#interrupt-cells = <3>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				interrupt-controller;
				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				reg = <0x210000 0x10000>,
				      <0x220000 0x20000>,
				      <0x240000 0x20000>,
				      <0x260000 0x20000>;

				gic_v2m0: v2m@280000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x280000 0x1000>;
					arm,msi-base-spi = <160>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m1: v2m@290000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x290000 0x1000>;
					arm,msi-base-spi = <192>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m2: v2m@2a0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2a0000 0x1000>;
					arm,msi-base-spi = <224>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m3: v2m@2b0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2b0000 0x1000>;
					arm,msi-base-spi = <256>;
					arm,msi-num-spis = <32>;
				};
			};

			timer {
				compatible = "arm,armv8-timer";
				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
			};

			odmi: odmi@300000 {
				compatible = "marvell,odmi-controller";
				interrupt-controller;
				msi-controller;
				marvell,odmi-frames = <4>;
				reg = <0x300000 0x4000>,
				      <0x304000 0x4000>,
				      <0x308000 0x4000>,
				      <0x30C000 0x4000>;
				marvell,spi-base = <128>, <136>, <144>, <152>;
			};

			spi0: spi@510600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x510600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ringclk 2>;
				status = "disabled";
			};

			i2c0: i2c@511000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x511000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&ringclk 2>;
				status = "disabled";
			};

			serial@512000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ringclk 2>;
				status = "disabled";
			};

			serial@512100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ringclk 2>;
				status = "disabled";

			};

			coreclk: clk@0x6F8204 {
				compatible = "marvell,armada-ap806-core-clock";
				reg = <0x6F8204 0x04>;
				#clock-cells = <1>;
				clock-output-names = "ddr", "ring", "cpu";
			};

			ringclk: clk@0x6F8250 {
				compatible = "marvell,armada-ap806-ring-clock";
				reg = <0x6F8250 0x04>;
				#clock-cells = <1>;
				clock-output-names = "ring-0", "ring-2",
						     "ring-3", "ring-4",
						     "ring-5";
				clocks = <&coreclk 1>;
			};

			xor0@400000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x400000 0x1000>,
				      <0x410000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor1@420000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x420000 0x1000>,
				      <0x430000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor2@440000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x440000 0x1000>,
				      <0x450000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor3@460000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x460000 0x1000>,
				      <0x470000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};
		};
	};

};
Commit	Line	Data
ec7e5a56 TP	1	/*
	2	* Copyright (C) 2016 Marvell Technology Group Ltd.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPLv2 or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/*
	44	* Device Tree file for Marvell Armada AP806.
	45	*/
	46
	47	#include <dt-bindings/interrupt-controller/arm-gic.h>
	48
	49	/dts-v1/;
	50
	51	/ {
	52	model = "Marvell Armada AP806";
	53	compatible = "marvell,armada-ap806";
	54	#address-cells = <2>;
	55	#size-cells = <2>;
	56
	57	psci {
	58	compatible = "arm,psci-0.2";
	59	method = "smc";
	60	};
	61
	62
	63	ap806 {
	64	#address-cells = <2>;
65	#size-cells = <2>;
66	compatible = "simple-bus";
67	interrupt-parent = <&gic>;
68	ranges;
69
70	config-space {
71	#address-cells = <1>;
72	#size-cells = <1>;
73	compatible = "simple-bus";
74	ranges = <0x0 0x0 0xf0000000 0x1000000>;
75
76	gic: interrupt-controller@210000 {
77	compatible = "arm,gic-400";
78	#interrupt-cells = <3>;
79	#address-cells = <1>;
80	#size-cells = <1>;
81	ranges;
82	interrupt-controller;
83	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
84	reg = <0x210000 0x10000>,
85	<0x220000 0x20000>,
86	<0x240000 0x20000>,
87	<0x260000 0x20000>;
88
89	gic_v2m0: v2m@280000 {
90	compatible = "arm,gic-v2m-frame";
91	msi-controller;
92	reg = <0x280000 0x1000>;
93	arm,msi-base-spi = <160>;
94	arm,msi-num-spis = <32>;
95	};
96	gic_v2m1: v2m@290000 {
97	compatible = "arm,gic-v2m-frame";
98	msi-controller;
99	reg = <0x290000 0x1000>;
100	arm,msi-base-spi = <192>;
101	arm,msi-num-spis = <32>;
102	};
103	gic_v2m2: v2m@2a0000 {
104	compatible = "arm,gic-v2m-frame";
105	msi-controller;
106	reg = <0x2a0000 0x1000>;
107	arm,msi-base-spi = <224>;
108	arm,msi-num-spis = <32>;
109	};
110	gic_v2m3: v2m@2b0000 {
111	compatible = "arm,gic-v2m-frame";
112	msi-controller;
113	reg = <0x2b0000 0x1000>;
114	arm,msi-base-spi = <256>;
115	arm,msi-num-spis = <32>;
116	};
117	};
118
119	timer {
120	compatible = "arm,armv8-timer";
121	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>,
122	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>,
123	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>,
124	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
125	};
126
127	odmi: odmi@300000 {
128	compatible = "marvell,odmi-controller";
129	interrupt-controller;
130	msi-controller;
131	marvell,odmi-frames = <4>;
132	reg = <0x300000 0x4000>,
133	<0x304000 0x4000>,
134	<0x308000 0x4000>,
135	<0x30C000 0x4000>;
136	marvell,spi-base = <128>, <136>, <144>, <152>;
137	};
138
139	spi0: spi@510600 {
140	compatible = "marvell,armada-380-spi";
141	reg = <0x510600 0x50>;
142	#address-cells = <1>;
143	#size-cells = <0>;
144	cell-index = <0>;
145	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
146	clocks = <&ringclk 2>;
147	status = "disabled";
148	};
149
150	i2c0: i2c@511000 {
151	compatible = "marvell,mv64xxx-i2c";
152	reg = <0x511000 0x20>;
153	#address-cells = <1>;
154	#size-cells = <0>;
155	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
156	timeout-ms = <1000>;
157	clocks = <&ringclk 2>;
158	status = "disabled";
159	};
160
161	serial@512000 {
162	compatible = "snps,dw-apb-uart";
163	reg = <0x512000 0x100>;
164	reg-shift = <2>;
165	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
166	reg-io-width = <1>;
167	clocks = <&ringclk 2>;
168	status = "disabled";
169	};
170
171	serial@512100 {
172	compatible = "snps,dw-apb-uart";
173	reg = <0x512100 0x100>;
174	reg-shift = <2>;
175	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
176	reg-io-width = <1>;
177	clocks = <&ringclk 2>;
178	status = "disabled";
179
180	};
181
182	coreclk: clk@0x6F8204 {
183	compatible = "marvell,armada-ap806-core-clock";
184	reg = <0x6F8204 0x04>;
185	#clock-cells = <1>;
186	clock-output-names = "ddr", "ring", "cpu";
187	};
188
189	ringclk: clk@0x6F8250 {
190	compatible = "marvell,armada-ap806-ring-clock";
191	reg = <0x6F8250 0x04>;
192	#clock-cells = <1>;
193	clock-output-names = "ring-0", "ring-2",
194	"ring-3", "ring-4",
195	"ring-5";
196	clocks = <&coreclk 1>;
197	};
198
199	xor0@400000 {
200	compatible = "marvell,mv-xor-v2";
201	reg = <0x400000 0x1000>,
202	<0x410000 0x1000>;
203	msi-parent = <&gic_v2m0>;
204	dma-coherent;
205	};
206
207	xor1@420000 {
208	compatible = "marvell,mv-xor-v2";
209	reg = <0x420000 0x1000>,
210	<0x430000 0x1000>;
211	msi-parent = <&gic_v2m0>;
212	dma-coherent;
213	};
214
215	xor2@440000 {
216	compatible = "marvell,mv-xor-v2";
217	reg = <0x440000 0x1000>,
218	<0x450000 0x1000>;
219	msi-parent = <&gic_v2m0>;
220	dma-coherent;
221	};
222
223	xor3@460000 {
224	compatible = "marvell,mv-xor-v2";
225	reg = <0x460000 0x1000>,
226	<0x470000 0x1000>;
227	msi-parent = <&gic_v2m0>;
228	dma-coherent;
229	};
230	};
231	};
232
233	};
234