[linux-2.6-block.git] / arch / arm64 / boot / dts / marvell / armada-ap806.dtsi

/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Device Tree file for Marvell Armada AP806.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/dts-v1/;

/ {
	model = "Marvell Armada AP806";
	compatible = "marvell,armada-ap806";
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	ap806 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			ranges = <0x0 0x0 0xf0000000 0x1000000>;

			gic: interrupt-controller@210000 {
				compatible = "arm,gic-400";
				#interrupt-cells = <3>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges;
				interrupt-controller;
				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
				reg = <0x210000 0x10000>,
				      <0x220000 0x20000>,
				      <0x240000 0x20000>,
				      <0x260000 0x20000>;

				gic_v2m0: v2m@280000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x280000 0x1000>;
					arm,msi-base-spi = <160>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m1: v2m@290000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x290000 0x1000>;
					arm,msi-base-spi = <192>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m2: v2m@2a0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2a0000 0x1000>;
					arm,msi-base-spi = <224>;
					arm,msi-num-spis = <32>;
				};
				gic_v2m3: v2m@2b0000 {
					compatible = "arm,gic-v2m-frame";
					msi-controller;
					reg = <0x2b0000 0x1000>;
					arm,msi-base-spi = <256>;
					arm,msi-num-spis = <32>;
				};
			};

			timer {
				compatible = "arm,armv8-timer";
				interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
					     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
					     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
					     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
			};

			odmi: odmi@300000 {
				compatible = "marvell,odmi-controller";
				interrupt-controller;
				msi-controller;
				marvell,odmi-frames = <4>;
				reg = <0x300000 0x4000>,
				      <0x304000 0x4000>,
				      <0x308000 0x4000>,
				      <0x30C000 0x4000>;
				marvell,spi-base = <128>, <136>, <144>, <152>;
			};

			xor@400000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x400000 0x1000>,
				      <0x410000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor@420000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x420000 0x1000>,
				      <0x430000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor@440000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x440000 0x1000>,
				      <0x450000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			xor@460000 {
				compatible = "marvell,mv-xor-v2";
				reg = <0x460000 0x1000>,
				      <0x470000 0x1000>;
				msi-parent = <&gic_v2m0>;
				dma-coherent;
			};

			spi0: spi@510600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x510600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&ringclk 2>;
				status = "disabled";
			};

			i2c0: i2c@511000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x511000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&ringclk 2>;
				status = "disabled";
			};

			uart0: serial@512000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ringclk 2>;
				status = "disabled";
			};

			uart1: serial@512100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x512100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&ringclk 2>;
				status = "disabled";

			};

			dfx-server@6f8000 {
				compatible = "simple-mfd", "syscon";
				reg = <0x6f8000 0x70000>;

				coreclk: clk@204 {
					compatible = "marvell,armada-ap806-core-clock";
					#clock-cells = <1>;
					clock-output-names = "ddr", "ring", "cpu";
				};

				ringclk: clk@250 {
					compatible = "marvell,armada-ap806-ring-clock";
					#clock-cells = <1>;
					clock-output-names = "ring-0", "ring-2",
							     "ring-3", "ring-4",
							     "ring-5";
					clocks = <&coreclk 1>;
				};
			};
		};
	};
};
Commit	Line	Data
ec7e5a56 TP	1	/*
	2	* Copyright (C) 2016 Marvell Technology Group Ltd.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPLv2 or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/*
	44	* Device Tree file for Marvell Armada AP806.
	45	*/
	46
	47	#include <dt-bindings/interrupt-controller/arm-gic.h>
	48
	49	/dts-v1/;
	50
	51	/ {
	52	model = "Marvell Armada AP806";
	53	compatible = "marvell,armada-ap806";
	54	#address-cells = <2>;
	55	#size-cells = <2>;
	56
	57	psci {
	58	compatible = "arm,psci-0.2";
	59	method = "smc";
	60	};
	61
ec7e5a56 TP	62	ap806 {
	63	#address-cells = <2>;
	64	#size-cells = <2>;
	65	compatible = "simple-bus";
	66	interrupt-parent = <&gic>;
	67	ranges;
	68
	69	config-space {
	70	#address-cells = <1>;
	71	#size-cells = <1>;
	72	compatible = "simple-bus";
	73	ranges = <0x0 0x0 0xf0000000 0x1000000>;
	74
	75	gic: interrupt-controller@210000 {
	76	compatible = "arm,gic-400";
	77	#interrupt-cells = <3>;
	78	#address-cells = <1>;
	79	#size-cells = <1>;
	80	ranges;
	81	interrupt-controller;
	82	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	83	reg = <0x210000 0x10000>,
	84	<0x220000 0x20000>,
	85	<0x240000 0x20000>,
	86	<0x260000 0x20000>;
	87
	88	gic_v2m0: v2m@280000 {
	89	compatible = "arm,gic-v2m-frame";
	90	msi-controller;
	91	reg = <0x280000 0x1000>;
	92	arm,msi-base-spi = <160>;
	93	arm,msi-num-spis = <32>;
	94	};
	95	gic_v2m1: v2m@290000 {
	96	compatible = "arm,gic-v2m-frame";
	97	msi-controller;
	98	reg = <0x290000 0x1000>;
	99	arm,msi-base-spi = <192>;
	100	arm,msi-num-spis = <32>;
	101	};
	102	gic_v2m2: v2m@2a0000 {
	103	compatible = "arm,gic-v2m-frame";
	104	msi-controller;
	105	reg = <0x2a0000 0x1000>;
	106	arm,msi-base-spi = <224>;
	107	arm,msi-num-spis = <32>;
	108	};
	109	gic_v2m3: v2m@2b0000 {
	110	compatible = "arm,gic-v2m-frame";
	111	msi-controller;
	112	reg = <0x2b0000 0x1000>;
	113	arm,msi-base-spi = <256>;
	114	arm,msi-num-spis = <32>;
	115	};
	116	};
	117
	118	timer {
	119	compatible = "arm,armv8-timer";
	120	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>,
	121	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>,
	122	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>,
	123	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
	124	};
	125
126	odmi: odmi@300000 {
127	compatible = "marvell,odmi-controller";
128	interrupt-controller;
129	msi-controller;
130	marvell,odmi-frames = <4>;
131	reg = <0x300000 0x4000>,
132	<0x304000 0x4000>,
133	<0x308000 0x4000>,
134	<0x30C000 0x4000>;
135	marvell,spi-base = <128>, <136>, <144>, <152>;
136	};
137
1093e5f6	138	xor@400000 {
b5ebfad8 TP	139	compatible = "marvell,mv-xor-v2";
	140	reg = <0x400000 0x1000>,
	141	<0x410000 0x1000>;
	142	msi-parent = <&gic_v2m0>;
	143	dma-coherent;
	144	};
	145
1093e5f6	146	xor@420000 {
b5ebfad8 TP	147	compatible = "marvell,mv-xor-v2";
	148	reg = <0x420000 0x1000>,
	149	<0x430000 0x1000>;
	150	msi-parent = <&gic_v2m0>;
	151	dma-coherent;
	152	};
	153
1093e5f6	154	xor@440000 {
b5ebfad8 TP	155	compatible = "marvell,mv-xor-v2";
	156	reg = <0x440000 0x1000>,
	157	<0x450000 0x1000>;
	158	msi-parent = <&gic_v2m0>;
	159	dma-coherent;
	160	};
	161
1093e5f6	162	xor@460000 {
b5ebfad8 TP	163	compatible = "marvell,mv-xor-v2";
	164	reg = <0x460000 0x1000>,
	165	<0x470000 0x1000>;
	166	msi-parent = <&gic_v2m0>;
	167	dma-coherent;
	168	};
	169
ec7e5a56 TP	170	spi0: spi@510600 {
	171	compatible = "marvell,armada-380-spi";
	172	reg = <0x510600 0x50>;
	173	#address-cells = <1>;
	174	#size-cells = <0>;
	175	cell-index = <0>;
	176	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	177	clocks = <&ringclk 2>;
	178	status = "disabled";
	179	};
	180
	181	i2c0: i2c@511000 {
	182	compatible = "marvell,mv64xxx-i2c";
	183	reg = <0x511000 0x20>;
	184	#address-cells = <1>;
	185	#size-cells = <0>;
	186	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	187	timeout-ms = <1000>;
	188	clocks = <&ringclk 2>;
	189	status = "disabled";
	190	};
	191
037ad463	192	uart0: serial@512000 {
ec7e5a56 TP	193	compatible = "snps,dw-apb-uart";
	194	reg = <0x512000 0x100>;
	195	reg-shift = <2>;
	196	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
	197	reg-io-width = <1>;
	198	clocks = <&ringclk 2>;
	199	status = "disabled";
	200	};
	201
037ad463	202	uart1: serial@512100 {
ec7e5a56 TP	203	compatible = "snps,dw-apb-uart";
	204	reg = <0x512100 0x100>;
	205	reg-shift = <2>;
	206	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	207	reg-io-width = <1>;
	208	clocks = <&ringclk 2>;
	209	status = "disabled";
	210
	211	};
	212
d2b78fb6 TP	213	dfx-server@6f8000 {
	214	compatible = "simple-mfd", "syscon";
	215	reg = <0x6f8000 0x70000>;
	216
	217	coreclk: clk@204 {
	218	compatible = "marvell,armada-ap806-core-clock";
	219	#clock-cells = <1>;
	220	clock-output-names = "ddr", "ring", "cpu";
	221	};
	222
	223	ringclk: clk@250 {
	224	compatible = "marvell,armada-ap806-ring-clock";
	225	#clock-cells = <1>;
	226	clock-output-names = "ring-0", "ring-2",
	227	"ring-3", "ring-4",
	228	"ring-5";
	229	clocks = <&coreclk 1>;
	230	};
	231	};
ec7e5a56 TP	232	};
ec7e5a56 TP	233	};
ec7e5a56	234	};