[linux-2.6-block.git] / arch / arm64 / boot / dts / hisilicon / hi3660.dtsi

/*
 * dts file for Hisilicon Hi3660 SoC
 *
 * Copyright (C) 2016, Hisilicon Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>

/ {
	compatible = "hisilicon,hi3660";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x101>;
			enable-method = "psci";
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x102>;
			enable-method = "psci";
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x103>;
			enable-method = "psci";
		};
	};

	gic: interrupt-controller@e82b0000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
		      <0x0 0xe82b2000 0 0x2000>, /* GICC */
		      <0x0 0xe82b4000 0 0x2000>, /* GICH */
		      <0x0 0xe82b6000 0 0x2000>; /* GICV */
		#address-cells = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		crg_ctrl: crg_ctrl@fff35000 {
			compatible = "hisilicon,hi3660-crgctrl", "syscon";
			reg = <0x0 0xfff35000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		crg_rst: crg_rst_controller {
			compatible = "hisilicon,hi3660-reset";
			#reset-cells = <2>;
			hisi,rst-syscon = <&crg_ctrl>;
		};


		pctrl: pctrl@e8a09000 {
			compatible = "hisilicon,hi3660-pctrl", "syscon";
			reg = <0x0 0xe8a09000 0x0 0x2000>;
			#clock-cells = <1>;
		};

		pmuctrl: crg_ctrl@fff34000 {
			compatible = "hisilicon,hi3660-pmuctrl", "syscon";
			reg = <0x0 0xfff34000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		sctrl: sctrl@fff0a000 {
			compatible = "hisilicon,hi3660-sctrl", "syscon";
			reg = <0x0 0xfff0a000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		iomcu: iomcu@ffd7e000 {
			compatible = "hisilicon,hi3660-iomcu", "syscon";
			reg = <0x0 0xffd7e000 0x0 0x1000>;
			#clock-cells = <1>;

		};

		iomcu_rst: reset {
			compatible = "hisilicon,hi3660-reset";
			hisi,rst-syscon = <&iomcu>;
			#reset-cells = <2>;
		};

		i2c0: i2c@ffd71000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd71000 0x0 0x1000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
			resets = <&iomcu_rst 0x20 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
			status = "disabled";
		};

		i2c1: i2c@ffd72000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd72000 0x0 0x1000>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
			resets = <&iomcu_rst 0x20 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
			status = "disabled";
		};

		i2c3: i2c@fdf0c000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0c000 0x0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
			resets = <&crg_rst 0x78 7>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
			status = "disabled";
		};

		i2c7: i2c@fdf0b000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0b000 0x0 0x1000>;
			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
			resets = <&crg_rst 0x60 14>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
			status = "disabled";
		};

		uart5: serial@fdf05000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf05000 0x0 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		gpio0: gpio@e8a0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0b000 0 0x1000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 0 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@e8a0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0c000 0 0x1000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 7 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@e8a0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0d000 0 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 14 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@e8a0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0e000 0 0x1000>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 22 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio4: gpio@e8a0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0f000 0 0x1000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 30 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio5: gpio@e8a10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a10000 0 0x1000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 38 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio6: gpio@e8a11000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a11000 0 0x1000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 46 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
			clock-names = "apb_pclk";
		};

		gpio7: gpio@e8a12000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a12000 0 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 54 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
			clock-names = "apb_pclk";
		};

		gpio8: gpio@e8a13000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a13000 0 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 62 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
			clock-names = "apb_pclk";
		};

		gpio9: gpio@e8a14000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a14000 0 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 70 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
			clock-names = "apb_pclk";
		};

		gpio10: gpio@e8a15000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a15000 0 0x1000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 78 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
			clock-names = "apb_pclk";
		};

		gpio11: gpio@e8a16000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a16000 0 0x1000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 86 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
			clock-names = "apb_pclk";
		};

		gpio12: gpio@e8a17000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a17000 0 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
			clock-names = "apb_pclk";
		};

		gpio13: gpio@e8a18000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a18000 0 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 102 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
			clock-names = "apb_pclk";
		};

		gpio14: gpio@e8a19000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a19000 0 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 110 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
			clock-names = "apb_pclk";
		};

		gpio15: gpio@e8a1a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1a000 0 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 118 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
			clock-names = "apb_pclk";
		};

		gpio16: gpio@e8a1b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1b000 0 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
			clock-names = "apb_pclk";
		};

		gpio17: gpio@e8a1c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1c000 0 0x1000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
			clock-names = "apb_pclk";
		};

		gpio18: gpio@ff3b4000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xff3b4000 0 0x1000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx2 0 0 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
			clock-names = "apb_pclk";
		};

		gpio19: gpio@ff3b5000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xff3b5000 0 0x1000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx2 0 8 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
			clock-names = "apb_pclk";
		};

		gpio20: gpio@e8a1f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1f000 0 0x1000>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx1 0 0 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
			clock-names = "apb_pclk";
		};

		gpio21: gpio@e8a20000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a20000 0 0x1000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx3 0 0 6>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
			clock-names = "apb_pclk";
		};

		gpio22: gpio@fff0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0b000 0 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO176 */
			gpio-ranges = <&pmx4 2 0 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio23: gpio@fff0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0c000 0 0x1000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO184 */
			gpio-ranges = <&pmx4 0 6 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio24: gpio@fff0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0d000 0 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO192 */
			gpio-ranges = <&pmx4 0 13 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio25: gpio@fff0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0e000 0 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO200 */
			gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio26: gpio@fff0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0f000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO208 */
			gpio-ranges = <&pmx4 0 28 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio27: gpio@fff10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff10000 0 0x1000>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO216 */
			gpio-ranges = <&pmx4 0 36 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio28: gpio@fff1d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff1d000 0 0x1000>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
			clock-names = "apb_pclk";
		};
	};
};
Commit	Line	Data
35ca8168 CF	1	/*
	2	* dts file for Hisilicon Hi3660 SoC
	3	*
	4	* Copyright (C) 2016, Hisilicon Ltd.
	5	*/
	6
	7	#include <dt-bindings/interrupt-controller/arm-gic.h>
a4e36ae0	8	#include <dt-bindings/clock/hi3660-clock.h>
35ca8168 CF	9
	10	/ {
	11	compatible = "hisilicon,hi3660";
	12	interrupt-parent = <&gic>;
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
	16	psci {
	17	compatible = "arm,psci-0.2";
	18	method = "smc";
	19	};
	20
	21	cpus {
	22	#address-cells = <2>;
	23	#size-cells = <0>;
	24
	25	cpu-map {
	26	cluster0 {
	27	core0 {
	28	cpu = <&cpu0>;
	29	};
	30	core1 {
	31	cpu = <&cpu1>;
	32	};
	33	core2 {
	34	cpu = <&cpu2>;
	35	};
	36	core3 {
	37	cpu = <&cpu3>;
	38	};
	39	};
	40	cluster1 {
	41	core0 {
	42	cpu = <&cpu4>;
	43	};
	44	core1 {
	45	cpu = <&cpu5>;
	46	};
	47	core2 {
	48	cpu = <&cpu6>;
	49	};
	50	core3 {
	51	cpu = <&cpu7>;
	52	};
	53	};
	54	};
	55
	56	cpu0: cpu@0 {
	57	compatible = "arm,cortex-a53", "arm,armv8";
	58	device_type = "cpu";
	59	reg = <0x0 0x0>;
	60	enable-method = "psci";
	61	};
	62
	63	cpu1: cpu@1 {
	64	compatible = "arm,cortex-a53", "arm,armv8";
	65	device_type = "cpu";
	66	reg = <0x0 0x1>;
	67	enable-method = "psci";
	68	};
	69
	70	cpu2: cpu@2 {
	71	compatible = "arm,cortex-a53", "arm,armv8";
	72	device_type = "cpu";
73	reg = <0x0 0x2>;
74	enable-method = "psci";
75	};
76
77	cpu3: cpu@3 {
78	compatible = "arm,cortex-a53", "arm,armv8";
79	device_type = "cpu";
80	reg = <0x0 0x3>;
81	enable-method = "psci";
82	};
83
84	cpu4: cpu@100 {
85	compatible = "arm,cortex-a73", "arm,armv8";
86	device_type = "cpu";
87	reg = <0x0 0x100>;
88	enable-method = "psci";
89	};
90
91	cpu5: cpu@101 {
92	compatible = "arm,cortex-a73", "arm,armv8";
93	device_type = "cpu";
94	reg = <0x0 0x101>;
95	enable-method = "psci";
96	};
97
98	cpu6: cpu@102 {
99	compatible = "arm,cortex-a73", "arm,armv8";
100	device_type = "cpu";
101	reg = <0x0 0x102>;
102	enable-method = "psci";
103	};
104
105	cpu7: cpu@103 {
106	compatible = "arm,cortex-a73", "arm,armv8";
107	device_type = "cpu";
108	reg = <0x0 0x103>;
109	enable-method = "psci";
110	};
111	};
112
113	gic: interrupt-controller@e82b0000 {
114	compatible = "arm,gic-400";
115	reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
116	<0x0 0xe82b2000 0 0x2000>, /* GICC */
117	<0x0 0xe82b4000 0 0x2000>, /* GICH */
118	<0x0 0xe82b6000 0 0x2000>; /* GICV */
119	#address-cells = <0>;
120	#interrupt-cells = <3>;
121	interrupt-controller;
122	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) \|
123	IRQ_TYPE_LEVEL_HIGH)>;
124	};
125
126	timer {
127	compatible = "arm,armv8-timer";
128	interrupt-parent = <&gic>;
129	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \|
130	IRQ_TYPE_LEVEL_LOW)>,
131	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \|
132	IRQ_TYPE_LEVEL_LOW)>,
133	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \|
134	IRQ_TYPE_LEVEL_LOW)>,
135	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \|
136	IRQ_TYPE_LEVEL_LOW)>;
137	};
138
139	soc {
140	compatible = "simple-bus";
141	#address-cells = <2>;
142	#size-cells = <2>;
143	ranges;
144
a4e36ae0 ZG	145	crg_ctrl: crg_ctrl@fff35000 {
	146	compatible = "hisilicon,hi3660-crgctrl", "syscon";
	147	reg = <0x0 0xfff35000 0x0 0x1000>;
	148	#clock-cells = <1>;
35ca8168 CF	149	};
35ca8168 CF	150
a4e36ae0 ZG	151	crg_rst: crg_rst_controller {
	152	compatible = "hisilicon,hi3660-reset";
	153	#reset-cells = <2>;
	154	hisi,rst-syscon = <&crg_ctrl>;
	155	};
	156
	157
	158	pctrl: pctrl@e8a09000 {
	159	compatible = "hisilicon,hi3660-pctrl", "syscon";
	160	reg = <0x0 0xe8a09000 0x0 0x2000>;
	161	#clock-cells = <1>;
	162	};
	163
	164	pmuctrl: crg_ctrl@fff34000 {
	165	compatible = "hisilicon,hi3660-pmuctrl", "syscon";
	166	reg = <0x0 0xfff34000 0x0 0x1000>;
	167	#clock-cells = <1>;
	168	};
	169
	170	sctrl: sctrl@fff0a000 {
	171	compatible = "hisilicon,hi3660-sctrl", "syscon";
	172	reg = <0x0 0xfff0a000 0x0 0x1000>;
	173	#clock-cells = <1>;
	174	};
	175
	176	iomcu: iomcu@ffd7e000 {
	177	compatible = "hisilicon,hi3660-iomcu", "syscon";
	178	reg = <0x0 0xffd7e000 0x0 0x1000>;
	179	#clock-cells = <1>;
	180
	181	};
	182
	183	iomcu_rst: reset {
	184	compatible = "hisilicon,hi3660-reset";
	185	hisi,rst-syscon = <&iomcu>;
	186	#reset-cells = <2>;
	187	};
	188
5f8a3b77 ZG	189	i2c0: i2c@ffd71000 {
	190	compatible = "snps,designware-i2c";
	191	reg = <0x0 0xffd71000 0x0 0x1000>;
	192	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195	clock-frequency = <400000>;
	196	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
	197	resets = <&iomcu_rst 0x20 3>;
	198	pinctrl-names = "default";
	199	pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
	200	status = "disabled";
	201	};
	202
	203	i2c1: i2c@ffd72000 {
	204	compatible = "snps,designware-i2c";
	205	reg = <0x0 0xffd72000 0x0 0x1000>;
	206	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	207	#address-cells = <1>;
	208	#size-cells = <0>;
	209	clock-frequency = <400000>;
	210	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
	211	resets = <&iomcu_rst 0x20 4>;
	212	pinctrl-names = "default";
	213	pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
	214	status = "disabled";
	215	};
	216
	217	i2c3: i2c@fdf0c000 {
	218	compatible = "snps,designware-i2c";
	219	reg = <0x0 0xfdf0c000 0x0 0x1000>;
	220	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	221	#address-cells = <1>;
	222	#size-cells = <0>;
	223	clock-frequency = <400000>;
	224	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
	225	resets = <&crg_rst 0x78 7>;
	226	pinctrl-names = "default";
	227	pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
	228	status = "disabled";
	229	};
	230
	231	i2c7: i2c@fdf0b000 {
	232	compatible = "snps,designware-i2c";
	233	reg = <0x0 0xfdf0b000 0x0 0x1000>;
	234	interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
	235	#address-cells = <1>;
	236	#size-cells = <0>;
	237	clock-frequency = <400000>;
	238	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
	239	resets = <&crg_rst 0x60 14>;
	240	pinctrl-names = "default";
	241	pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
	242	status = "disabled";
	243	};
	244
a4e36ae0	245	uart5: serial@fdf05000 {
35ca8168 CF	246	compatible = "arm,pl011", "arm,primecell";
	247	reg = <0x0 0xfdf05000 0x0 0x1000>;
	248	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
a4e36ae0 ZG	249	clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
a4e36ae0 ZG	250	<&crg_ctrl HI3660_CLK_GATE_UART5>;
35ca8168 CF	251	clock-names = "uartclk", "apb_pclk";
	252	status = "disabled";
	253	};
d94eab86 WX	254
	255	gpio0: gpio@e8a0b000 {
	256	compatible = "arm,pl061", "arm,primecell";
	257	reg = <0 0xe8a0b000 0 0x1000>;
	258	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	259	gpio-controller;
	260	#gpio-cells = <2>;
	261	gpio-ranges = <&pmx0 1 0 7>;
	262	interrupt-controller;
	263	#interrupt-cells = <2>;
	264	clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
	265	clock-names = "apb_pclk";
	266	};
	267
	268	gpio1: gpio@e8a0c000 {
	269	compatible = "arm,pl061", "arm,primecell";
	270	reg = <0 0xe8a0c000 0 0x1000>;
	271	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	272	gpio-controller;
	273	#gpio-cells = <2>;
	274	gpio-ranges = <&pmx0 1 7 7>;
	275	interrupt-controller;
	276	#interrupt-cells = <2>;
	277	clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
	278	clock-names = "apb_pclk";
	279	};
	280
	281	gpio2: gpio@e8a0d000 {
	282	compatible = "arm,pl061", "arm,primecell";
	283	reg = <0 0xe8a0d000 0 0x1000>;
	284	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	285	gpio-controller;
	286	#gpio-cells = <2>;
	287	gpio-ranges = <&pmx0 0 14 8>;
	288	interrupt-controller;
	289	#interrupt-cells = <2>;
	290	clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
	291	clock-names = "apb_pclk";
	292	};
	293
	294	gpio3: gpio@e8a0e000 {
	295	compatible = "arm,pl061", "arm,primecell";
	296	reg = <0 0xe8a0e000 0 0x1000>;
	297	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	298	gpio-controller;
	299	#gpio-cells = <2>;
	300	gpio-ranges = <&pmx0 0 22 8>;
	301	interrupt-controller;
	302	#interrupt-cells = <2>;
	303	clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
	304	clock-names = "apb_pclk";
	305	};
	306
	307	gpio4: gpio@e8a0f000 {
	308	compatible = "arm,pl061", "arm,primecell";
	309	reg = <0 0xe8a0f000 0 0x1000>;
	310	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	311	gpio-controller;
	312	#gpio-cells = <2>;
	313	gpio-ranges = <&pmx0 0 30 8>;
	314	interrupt-controller;
	315	#interrupt-cells = <2>;
	316	clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
	317	clock-names = "apb_pclk";
318	};
319
320	gpio5: gpio@e8a10000 {
321	compatible = "arm,pl061", "arm,primecell";
322	reg = <0 0xe8a10000 0 0x1000>;
323	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
324	gpio-controller;
325	#gpio-cells = <2>;
326	gpio-ranges = <&pmx0 0 38 8>;
327	interrupt-controller;
328	#interrupt-cells = <2>;
329	clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
330	clock-names = "apb_pclk";
331	};
332
333	gpio6: gpio@e8a11000 {
334	compatible = "arm,pl061", "arm,primecell";
335	reg = <0 0xe8a11000 0 0x1000>;
336	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
337	gpio-controller;
338	#gpio-cells = <2>;
339	gpio-ranges = <&pmx0 0 46 8>;
340	interrupt-controller;
341	#interrupt-cells = <2>;
342	clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
343	clock-names = "apb_pclk";
344	};
345
346	gpio7: gpio@e8a12000 {
347	compatible = "arm,pl061", "arm,primecell";
348	reg = <0 0xe8a12000 0 0x1000>;
349	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
350	gpio-controller;
351	#gpio-cells = <2>;
352	gpio-ranges = <&pmx0 0 54 8>;
353	interrupt-controller;
354	#interrupt-cells = <2>;
355	clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
356	clock-names = "apb_pclk";
357	};
358
359	gpio8: gpio@e8a13000 {
360	compatible = "arm,pl061", "arm,primecell";
361	reg = <0 0xe8a13000 0 0x1000>;
362	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
363	gpio-controller;
364	#gpio-cells = <2>;
365	gpio-ranges = <&pmx0 0 62 8>;
366	interrupt-controller;
367	#interrupt-cells = <2>;
368	clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
369	clock-names = "apb_pclk";
370	};
371
372	gpio9: gpio@e8a14000 {
373	compatible = "arm,pl061", "arm,primecell";
374	reg = <0 0xe8a14000 0 0x1000>;
375	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
376	gpio-controller;
377	#gpio-cells = <2>;
378	gpio-ranges = <&pmx0 0 70 8>;
379	interrupt-controller;
380	#interrupt-cells = <2>;
381	clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
382	clock-names = "apb_pclk";
383	};
384
385	gpio10: gpio@e8a15000 {
386	compatible = "arm,pl061", "arm,primecell";
387	reg = <0 0xe8a15000 0 0x1000>;
388	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
389	gpio-controller;
390	#gpio-cells = <2>;
391	gpio-ranges = <&pmx0 0 78 8>;
392	interrupt-controller;
393	#interrupt-cells = <2>;
394	clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
395	clock-names = "apb_pclk";
396	};
397
398	gpio11: gpio@e8a16000 {
399	compatible = "arm,pl061", "arm,primecell";
400	reg = <0 0xe8a16000 0 0x1000>;
401	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
402	gpio-controller;
403	#gpio-cells = <2>;
404	gpio-ranges = <&pmx0 0 86 8>;
405	interrupt-controller;
406	#interrupt-cells = <2>;
407	clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
408	clock-names = "apb_pclk";
409	};
410
411	gpio12: gpio@e8a17000 {
412	compatible = "arm,pl061", "arm,primecell";
413	reg = <0 0xe8a17000 0 0x1000>;
414	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
415	gpio-controller;
416	#gpio-cells = <2>;
417	gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
418	interrupt-controller;
419	#interrupt-cells = <2>;
420	clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
421	clock-names = "apb_pclk";
422	};
423
424	gpio13: gpio@e8a18000 {
425	compatible = "arm,pl061", "arm,primecell";
426	reg = <0 0xe8a18000 0 0x1000>;
427	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
428	gpio-controller;
429	#gpio-cells = <2>;
430	gpio-ranges = <&pmx0 0 102 8>;
431	interrupt-controller;
432	#interrupt-cells = <2>;
433	clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
434	clock-names = "apb_pclk";
435	};
436
437	gpio14: gpio@e8a19000 {
438	compatible = "arm,pl061", "arm,primecell";
439	reg = <0 0xe8a19000 0 0x1000>;
440	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
441	gpio-controller;
442	#gpio-cells = <2>;
443	gpio-ranges = <&pmx0 0 110 8>;
444	interrupt-controller;
445	#interrupt-cells = <2>;
446	clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
447	clock-names = "apb_pclk";
448	};
449
450	gpio15: gpio@e8a1a000 {
451	compatible = "arm,pl061", "arm,primecell";
452	reg = <0 0xe8a1a000 0 0x1000>;
453	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
454	gpio-controller;
455	#gpio-cells = <2>;
456	gpio-ranges = <&pmx0 0 118 6>;
457	interrupt-controller;
458	#interrupt-cells = <2>;
459	clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
460	clock-names = "apb_pclk";
461	};
462
463	gpio16: gpio@e8a1b000 {
464	compatible = "arm,pl061", "arm,primecell";
465	reg = <0 0xe8a1b000 0 0x1000>;
466	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
467	gpio-controller;
468	#gpio-cells = <2>;
469	interrupt-controller;
470	#interrupt-cells = <2>;
471	clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
472	clock-names = "apb_pclk";
473	};
474
475	gpio17: gpio@e8a1c000 {
476	compatible = "arm,pl061", "arm,primecell";
477	reg = <0 0xe8a1c000 0 0x1000>;
478	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
479	gpio-controller;
480	#gpio-cells = <2>;
481	interrupt-controller;
482	#interrupt-cells = <2>;
483	clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
484	clock-names = "apb_pclk";
485	};
486
487	gpio18: gpio@ff3b4000 {
488	compatible = "arm,pl061", "arm,primecell";
489	reg = <0 0xff3b4000 0 0x1000>;
490	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
491	gpio-controller;
492	#gpio-cells = <2>;
493	gpio-ranges = <&pmx2 0 0 8>;
494	interrupt-controller;
495	#interrupt-cells = <2>;
496	clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
497	clock-names = "apb_pclk";
498	};
499
500	gpio19: gpio@ff3b5000 {
501	compatible = "arm,pl061", "arm,primecell";
502	reg = <0 0xff3b5000 0 0x1000>;
503	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
504	gpio-controller;
505	#gpio-cells = <2>;
506	gpio-ranges = <&pmx2 0 8 4>;
507	interrupt-controller;
508	#interrupt-cells = <2>;
509	clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
510	clock-names = "apb_pclk";
511	};
512
513	gpio20: gpio@e8a1f000 {
514	compatible = "arm,pl061", "arm,primecell";
515	reg = <0 0xe8a1f000 0 0x1000>;
516	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
517	gpio-controller;
518	#gpio-cells = <2>;
519	gpio-ranges = <&pmx1 0 0 6>;
520	interrupt-controller;
521	#interrupt-cells = <2>;
522	clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
523	clock-names = "apb_pclk";
524	};
525
526	gpio21: gpio@e8a20000 {
527	compatible = "arm,pl061", "arm,primecell";
528	reg = <0 0xe8a20000 0 0x1000>;
529	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
530	gpio-controller;
531	#gpio-cells = <2>;
532	interrupt-controller;
533	#interrupt-cells = <2>;
534	gpio-ranges = <&pmx3 0 0 6>;
535	clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
536	clock-names = "apb_pclk";
537	};
538
539	gpio22: gpio@fff0b000 {
540	compatible = "arm,pl061", "arm,primecell";
541	reg = <0 0xfff0b000 0 0x1000>;
542	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
543	gpio-controller;
544	#gpio-cells = <2>;
545	/* GPIO176 */
546	gpio-ranges = <&pmx4 2 0 6>;
547	interrupt-controller;
548	#interrupt-cells = <2>;
549	clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
550	clock-names = "apb_pclk";
551	};
552
553	gpio23: gpio@fff0c000 {
554	compatible = "arm,pl061", "arm,primecell";
555	reg = <0 0xfff0c000 0 0x1000>;
556	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
557	gpio-controller;
558	#gpio-cells = <2>;
559	/* GPIO184 */
560	gpio-ranges = <&pmx4 0 6 7>;
561	interrupt-controller;
562	#interrupt-cells = <2>;
563	clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
564	clock-names = "apb_pclk";
565	};
566
567	gpio24: gpio@fff0d000 {
568	compatible = "arm,pl061", "arm,primecell";
569	reg = <0 0xfff0d000 0 0x1000>;
570	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
571	gpio-controller;
572	#gpio-cells = <2>;
573	/* GPIO192 */
574	gpio-ranges = <&pmx4 0 13 8>;
575	interrupt-controller;
576	#interrupt-cells = <2>;
577	clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
578	clock-names = "apb_pclk";
579	};
580
581	gpio25: gpio@fff0e000 {
582	compatible = "arm,pl061", "arm,primecell";
583	reg = <0 0xfff0e000 0 0x1000>;
584	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
585	gpio-controller;
586	#gpio-cells = <2>;
587	/* GPIO200 */
588	gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
589	interrupt-controller;
590	#interrupt-cells = <2>;
591	clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
592	clock-names = "apb_pclk";
593	};
594
595	gpio26: gpio@fff0f000 {
596	compatible = "arm,pl061", "arm,primecell";
597	reg = <0 0xfff0f000 0 0x1000>;
598	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
599	gpio-controller;
600	#gpio-cells = <2>;
601	/* GPIO208 */
602	gpio-ranges = <&pmx4 0 28 8>;
603	interrupt-controller;
604	#interrupt-cells = <2>;
605	clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
606	clock-names = "apb_pclk";
607	};
608
609	gpio27: gpio@fff10000 {
610	compatible = "arm,pl061", "arm,primecell";
611	reg = <0 0xfff10000 0 0x1000>;
612	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
613	gpio-controller;
614	#gpio-cells = <2>;
615	/* GPIO216 */
616	gpio-ranges = <&pmx4 0 36 6>;
617	interrupt-controller;
618	#interrupt-cells = <2>;
619	clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
620	clock-names = "apb_pclk";
621	};
622
623	gpio28: gpio@fff1d000 {
624	compatible = "arm,pl061", "arm,primecell";
625	reg = <0 0xfff1d000 0 0x1000>;
626	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
627	gpio-controller;
628	#gpio-cells = <2>;
629	interrupt-controller;
630	#interrupt-cells = <2>;
631	clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
632	clock-names = "apb_pclk";
633	};
35ca8168 CF	634	};
35ca8168 CF	635	};