projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 35ca8168 CF |
1 | /* |
| 2 | * dts file for Hisilicon Hi3660 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2016, Hisilicon Ltd. | |
| 5 | */ | |
| 6 | ||
| 7 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| a4e36ae0 | 8 | #include <dt-bindings/clock/hi3660-clock.h> |
| 35ca8168 CF |
9 | |
| 10 | / { | |
| 11 | compatible = "hisilicon,hi3660"; | |
| 12 | interrupt-parent = <&gic>; | |
| 13 | #address-cells = <2>; | |
| 14 | #size-cells = <2>; | |
| 15 | ||
| 16 | psci { | |
| 17 | compatible = "arm,psci-0.2"; | |
| 18 | method = "smc"; | |
| 19 | }; | |
| 20 | ||
| 21 | cpus { | |
| 22 | #address-cells = <2>; | |
| 23 | #size-cells = <0>; | |
| 24 | ||
| 25 | cpu-map { | |
| 26 | cluster0 { | |
| 27 | core0 { | |
| 28 | cpu = <&cpu0>; | |
| 29 | }; | |
| 30 | core1 { | |
| 31 | cpu = <&cpu1>; | |
| 32 | }; | |
| 33 | core2 { | |
| 34 | cpu = <&cpu2>; | |
| 35 | }; | |
| 36 | core3 { | |
| 37 | cpu = <&cpu3>; | |
| 38 | }; | |
| 39 | }; | |
| 40 | cluster1 { | |
| 41 | core0 { | |
| 42 | cpu = <&cpu4>; | |
| 43 | }; | |
| 44 | core1 { | |
| 45 | cpu = <&cpu5>; | |
| 46 | }; | |
| 47 | core2 { | |
| 48 | cpu = <&cpu6>; | |
| 49 | }; | |
| 50 | core3 { | |
| 51 | cpu = <&cpu7>; | |
| 52 | }; | |
| 53 | }; | |
| 54 | }; | |
| 55 | ||
| 56 | cpu0: cpu@0 { | |
| 57 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 58 | device_type = "cpu"; | |
| 59 | reg = <0x0 0x0>; | |
| 60 | enable-method = "psci"; | |
| a6d08344 | 61 | next-level-cache = <&A53_L2>; |
| 30fec826 | 62 | cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; |
| 35ca8168 CF |
63 | }; |
| 64 | ||
| 65 | cpu1: cpu@1 { | |
| 66 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 67 | device_type = "cpu"; | |
| 68 | reg = <0x0 0x1>; | |
| 69 | enable-method = "psci"; | |
| a6d08344 | 70 | next-level-cache = <&A53_L2>; |
| 30fec826 | 71 | cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; |
| 35ca8168 CF |
72 | }; |
| 73 | ||
| 74 | cpu2: cpu@2 { | |
| 75 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 76 | device_type = "cpu"; | |
| 77 | reg = <0x0 0x2>; | |
| 78 | enable-method = "psci"; | |
| a6d08344 | 79 | next-level-cache = <&A53_L2>; |
| 30fec826 | 80 | cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; |
| 35ca8168 CF |
81 | }; |
| 82 | ||
| 83 | cpu3: cpu@3 { | |
| 84 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 85 | device_type = "cpu"; | |
| 86 | reg = <0x0 0x3>; | |
| 87 | enable-method = "psci"; | |
| a6d08344 | 88 | next-level-cache = <&A53_L2>; |
| 30fec826 | 89 | cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; |
| 35ca8168 CF |
90 | }; |
| 91 | ||
| 92 | cpu4: cpu@100 { | |
| 93 | compatible = "arm,cortex-a73", "arm,armv8"; | |
| 94 | device_type = "cpu"; | |
| 95 | reg = <0x0 0x100>; | |
| 96 | enable-method = "psci"; | |
| a6d08344 | 97 | next-level-cache = <&A73_L2>; |
| 30fec826 LY |
98 | cpu-idle-states = < |
| 99 | &CPU_NAP | |
| 100 | &CPU_SLEEP | |
| 101 | &CLUSTER_SLEEP_1 | |
| 102 | >; | |
| 35ca8168 CF |
103 | }; |
| 104 | ||
| 105 | cpu5: cpu@101 { | |
| 106 | compatible = "arm,cortex-a73", "arm,armv8"; | |
| 107 | device_type = "cpu"; | |
| 108 | reg = <0x0 0x101>; | |
| 109 | enable-method = "psci"; | |
| a6d08344 | 110 | next-level-cache = <&A73_L2>; |
| 30fec826 LY |
111 | cpu-idle-states = < |
| 112 | &CPU_NAP | |
| 113 | &CPU_SLEEP | |
| 114 | &CLUSTER_SLEEP_1 | |
| 115 | >; | |
| 35ca8168 CF |
116 | }; |
| 117 | ||
| 118 | cpu6: cpu@102 { | |
| 119 | compatible = "arm,cortex-a73", "arm,armv8"; | |
| 120 | device_type = "cpu"; | |
| 121 | reg = <0x0 0x102>; | |
| 122 | enable-method = "psci"; | |
| a6d08344 | 123 | next-level-cache = <&A73_L2>; |
| 30fec826 LY |
124 | cpu-idle-states = < |
| 125 | &CPU_NAP | |
| 126 | &CPU_SLEEP | |
| 127 | &CLUSTER_SLEEP_1 | |
| 128 | >; | |
| 35ca8168 CF |
129 | }; |
| 130 | ||
| 131 | cpu7: cpu@103 { | |
| 132 | compatible = "arm,cortex-a73", "arm,armv8"; | |
| 133 | device_type = "cpu"; | |
| 134 | reg = <0x0 0x103>; | |
| 135 | enable-method = "psci"; | |
| a6d08344 | 136 | next-level-cache = <&A73_L2>; |
| 30fec826 LY |
137 | cpu-idle-states = < |
| 138 | &CPU_NAP | |
| 139 | &CPU_SLEEP | |
| 140 | &CLUSTER_SLEEP_1 | |
| 141 | >; | |
| 142 | }; | |
| 143 | ||
| 144 | idle-states { | |
| 145 | entry-method = "psci"; | |
| 146 | ||
| 147 | CPU_NAP: cpu-nap { | |
| 148 | compatible = "arm,idle-state"; | |
| 149 | arm,psci-suspend-param = <0x0000001>; | |
| 150 | entry-latency-us = <7>; | |
| 151 | exit-latency-us = <2>; | |
| 152 | min-residency-us = <15>; | |
| 153 | }; | |
| 154 | ||
| 155 | CPU_SLEEP: cpu-sleep { | |
| 156 | compatible = "arm,idle-state"; | |
| 157 | local-timer-stop; | |
| 158 | arm,psci-suspend-param = <0x0010000>; | |
| 159 | entry-latency-us = <40>; | |
| 160 | exit-latency-us = <70>; | |
| 161 | min-residency-us = <3000>; | |
| 162 | }; | |
| 163 | ||
| 164 | CLUSTER_SLEEP_0: cluster-sleep-0 { | |
| 165 | compatible = "arm,idle-state"; | |
| 166 | local-timer-stop; | |
| 167 | arm,psci-suspend-param = <0x1010000>; | |
| 168 | entry-latency-us = <500>; | |
| 169 | exit-latency-us = <5000>; | |
| 170 | min-residency-us = <20000>; | |
| 171 | }; | |
| 172 | ||
| 173 | CLUSTER_SLEEP_1: cluster-sleep-1 { | |
| 174 | compatible = "arm,idle-state"; | |
| 175 | local-timer-stop; | |
| 176 | arm,psci-suspend-param = <0x1010000>; | |
| 177 | entry-latency-us = <1000>; | |
| 178 | exit-latency-us = <5000>; | |
| 179 | min-residency-us = <20000>; | |
| 180 | }; | |
| 35ca8168 | 181 | }; |
| a6d08344 LY |
182 | |
| 183 | A53_L2: l2-cache0 { | |
| 184 | compatible = "cache"; | |
| 185 | }; | |
| 186 | ||
| 187 | A73_L2: l2-cache1 { | |
| 188 | compatible = "cache"; | |
| 189 | }; | |
| 35ca8168 CF |
190 | }; |
| 191 | ||
| 192 | gic: interrupt-controller@e82b0000 { | |
| 193 | compatible = "arm,gic-400"; | |
| 194 | reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ | |
| 195 | <0x0 0xe82b2000 0 0x2000>, /* GICC */ | |
| 196 | <0x0 0xe82b4000 0 0x2000>, /* GICH */ | |
| 197 | <0x0 0xe82b6000 0 0x2000>; /* GICV */ | |
| 198 | #address-cells = <0>; | |
| 199 | #interrupt-cells = <3>; | |
| 200 | interrupt-controller; | |
| 201 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | | |
| 202 | IRQ_TYPE_LEVEL_HIGH)>; | |
| 203 | }; | |
| 204 | ||
| 205 | timer { | |
| 206 | compatible = "arm,armv8-timer"; | |
| 207 | interrupt-parent = <&gic>; | |
| 208 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | | |
| 209 | IRQ_TYPE_LEVEL_LOW)>, | |
| 210 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | | |
| 211 | IRQ_TYPE_LEVEL_LOW)>, | |
| 212 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | | |
| 213 | IRQ_TYPE_LEVEL_LOW)>, | |
| 214 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | | |
| 215 | IRQ_TYPE_LEVEL_LOW)>; | |
| 216 | }; | |
| 217 | ||
| 218 | soc { | |
| 219 | compatible = "simple-bus"; | |
| 220 | #address-cells = <2>; | |
| 221 | #size-cells = <2>; | |
| 222 | ranges; | |
| 223 | ||
| a4e36ae0 ZG |
224 | crg_ctrl: crg_ctrl@fff35000 { |
| 225 | compatible = "hisilicon,hi3660-crgctrl", "syscon"; | |
| 226 | reg = <0x0 0xfff35000 0x0 0x1000>; | |
| 227 | #clock-cells = <1>; | |
| 35ca8168 CF |
228 | }; |
| 229 | ||
| a4e36ae0 ZG |
230 | crg_rst: crg_rst_controller { |
| 231 | compatible = "hisilicon,hi3660-reset"; | |
| 232 | #reset-cells = <2>; | |
| 233 | hisi,rst-syscon = <&crg_ctrl>; | |
| 234 | }; | |
| 235 | ||
| 236 | ||
| 237 | pctrl: pctrl@e8a09000 { | |
| 238 | compatible = "hisilicon,hi3660-pctrl", "syscon"; | |
| 239 | reg = <0x0 0xe8a09000 0x0 0x2000>; | |
| 240 | #clock-cells = <1>; | |
| 241 | }; | |
| 242 | ||
| 243 | pmuctrl: crg_ctrl@fff34000 { | |
| 244 | compatible = "hisilicon,hi3660-pmuctrl", "syscon"; | |
| 245 | reg = <0x0 0xfff34000 0x0 0x1000>; | |
| 246 | #clock-cells = <1>; | |
| 247 | }; | |
| 248 | ||
| 249 | sctrl: sctrl@fff0a000 { | |
| 250 | compatible = "hisilicon,hi3660-sctrl", "syscon"; | |
| 251 | reg = <0x0 0xfff0a000 0x0 0x1000>; | |
| 252 | #clock-cells = <1>; | |
| 253 | }; | |
| 254 | ||
| 255 | iomcu: iomcu@ffd7e000 { | |
| 256 | compatible = "hisilicon,hi3660-iomcu", "syscon"; | |
| 257 | reg = <0x0 0xffd7e000 0x0 0x1000>; | |
| 258 | #clock-cells = <1>; | |
| 259 | ||
| 260 | }; | |
| 261 | ||
| 262 | iomcu_rst: reset { | |
| 263 | compatible = "hisilicon,hi3660-reset"; | |
| 264 | hisi,rst-syscon = <&iomcu>; | |
| 265 | #reset-cells = <2>; | |
| 266 | }; | |
| 267 | ||
| 75196330 LY |
268 | dual_timer0: timer@fff14000 { |
| 269 | compatible = "arm,sp804", "arm,primecell"; | |
| 270 | reg = <0x0 0xfff14000 0x0 0x1000>; | |
| 271 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
| 272 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
| 273 | clocks = <&crg_ctrl HI3660_OSC32K>, | |
| 274 | <&crg_ctrl HI3660_OSC32K>, | |
| 275 | <&crg_ctrl HI3660_OSC32K>; | |
| 276 | clock-names = "timer1", "timer2", "apb_pclk"; | |
| 277 | }; | |
| 278 | ||
| 5f8a3b77 ZG |
279 | i2c0: i2c@ffd71000 { |
| 280 | compatible = "snps,designware-i2c"; | |
| 281 | reg = <0x0 0xffd71000 0x0 0x1000>; | |
| 282 | interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 283 | #address-cells = <1>; | |
| 284 | #size-cells = <0>; | |
| 285 | clock-frequency = <400000>; | |
| 286 | clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; | |
| 287 | resets = <&iomcu_rst 0x20 3>; | |
| 288 | pinctrl-names = "default"; | |
| 289 | pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; | |
| 290 | status = "disabled"; | |
| 291 | }; | |
| 292 | ||
| 293 | i2c1: i2c@ffd72000 { | |
| 294 | compatible = "snps,designware-i2c"; | |
| 295 | reg = <0x0 0xffd72000 0x0 0x1000>; | |
| 296 | interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
| 297 | #address-cells = <1>; | |
| 298 | #size-cells = <0>; | |
| 299 | clock-frequency = <400000>; | |
| 300 | clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; | |
| 301 | resets = <&iomcu_rst 0x20 4>; | |
| 302 | pinctrl-names = "default"; | |
| 303 | pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; | |
| 304 | status = "disabled"; | |
| 305 | }; | |
| 306 | ||
| 307 | i2c3: i2c@fdf0c000 { | |
| 308 | compatible = "snps,designware-i2c"; | |
| 309 | reg = <0x0 0xfdf0c000 0x0 0x1000>; | |
| 310 | interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| 311 | #address-cells = <1>; | |
| 312 | #size-cells = <0>; | |
| 313 | clock-frequency = <400000>; | |
| 314 | clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; | |
| 315 | resets = <&crg_rst 0x78 7>; | |
| 316 | pinctrl-names = "default"; | |
| 317 | pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; | |
| 318 | status = "disabled"; | |
| 319 | }; | |
| 320 | ||
| 321 | i2c7: i2c@fdf0b000 { | |
| 322 | compatible = "snps,designware-i2c"; | |
| 323 | reg = <0x0 0xfdf0b000 0x0 0x1000>; | |
| 324 | interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; | |
| 325 | #address-cells = <1>; | |
| 326 | #size-cells = <0>; | |
| 327 | clock-frequency = <400000>; | |
| 328 | clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; | |
| 329 | resets = <&crg_rst 0x60 14>; | |
| 330 | pinctrl-names = "default"; | |
| 331 | pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; | |
| 332 | status = "disabled"; | |
| 333 | }; | |
| 334 | ||
| 254b07b2 CF |
335 | uart0: serial@fdf02000 { |
| 336 | compatible = "arm,pl011", "arm,primecell"; | |
| 337 | reg = <0x0 0xfdf02000 0x0 0x1000>; | |
| 338 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; | |
| 339 | clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, | |
| 340 | <&crg_ctrl HI3660_PCLK>; | |
| 341 | clock-names = "uartclk", "apb_pclk"; | |
| 342 | pinctrl-names = "default"; | |
| 343 | pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; | |
| 344 | status = "disabled"; | |
| 345 | }; | |
| 346 | ||
| 347 | uart1: serial@fdf00000 { | |
| 348 | compatible = "arm,pl011", "arm,primecell"; | |
| 349 | reg = <0x0 0xfdf00000 0x0 0x1000>; | |
| 350 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 351 | clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, | |
| 352 | <&crg_ctrl HI3660_CLK_GATE_UART1>; | |
| 353 | clock-names = "uartclk", "apb_pclk"; | |
| 354 | pinctrl-names = "default"; | |
| 355 | pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; | |
| 356 | status = "disabled"; | |
| 357 | }; | |
| 358 | ||
| 359 | uart2: serial@fdf03000 { | |
| 360 | compatible = "arm,pl011", "arm,primecell"; | |
| 361 | reg = <0x0 0xfdf03000 0x0 0x1000>; | |
| 362 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | |
| 363 | clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, | |
| 364 | <&crg_ctrl HI3660_PCLK>; | |
| 365 | clock-names = "uartclk", "apb_pclk"; | |
| 366 | pinctrl-names = "default"; | |
| 367 | pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; | |
| 368 | status = "disabled"; | |
| 369 | }; | |
| 370 | ||
| 371 | uart3: serial@ffd74000 { | |
| 372 | compatible = "arm,pl011", "arm,primecell"; | |
| 373 | reg = <0x0 0xffd74000 0x0 0x1000>; | |
| 374 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
| 375 | clocks = <&crg_ctrl HI3660_FACTOR_UART3>, | |
| 376 | <&crg_ctrl HI3660_PCLK>; | |
| 377 | clock-names = "uartclk", "apb_pclk"; | |
| 378 | pinctrl-names = "default"; | |
| 379 | pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; | |
| 380 | status = "disabled"; | |
| 381 | }; | |
| 382 | ||
| 383 | uart4: serial@fdf01000 { | |
| 384 | compatible = "arm,pl011", "arm,primecell"; | |
| 385 | reg = <0x0 0xfdf01000 0x0 0x1000>; | |
| 386 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | |
| 387 | clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, | |
| 388 | <&crg_ctrl HI3660_CLK_GATE_UART4>; | |
| 389 | clock-names = "uartclk", "apb_pclk"; | |
| 390 | pinctrl-names = "default"; | |
| 391 | pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; | |
| 392 | status = "disabled"; | |
| 393 | }; | |
| 394 | ||
| a4e36ae0 | 395 | uart5: serial@fdf05000 { |
| 35ca8168 CF |
396 | compatible = "arm,pl011", "arm,primecell"; |
| 397 | reg = <0x0 0xfdf05000 0x0 0x1000>; | |
| 398 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; | |
| a4e36ae0 ZG |
399 | clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, |
| 400 | <&crg_ctrl HI3660_CLK_GATE_UART5>; | |
| 35ca8168 | 401 | clock-names = "uartclk", "apb_pclk"; |
| 254b07b2 CF |
402 | pinctrl-names = "default"; |
| 403 | pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; | |
| 404 | status = "disabled"; | |
| 405 | }; | |
| 406 | ||
| 407 | uart6: serial@fff32000 { | |
| 408 | compatible = "arm,pl011", "arm,primecell"; | |
| 409 | reg = <0x0 0xfff32000 0x0 0x1000>; | |
| 410 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; | |
| 411 | clocks = <&crg_ctrl HI3660_CLK_UART6>, | |
| 412 | <&crg_ctrl HI3660_PCLK>; | |
| 413 | clock-names = "uartclk", "apb_pclk"; | |
| 414 | pinctrl-names = "default"; | |
| 415 | pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; | |
| 35ca8168 CF |
416 | status = "disabled"; |
| 417 | }; | |
| d94eab86 | 418 | |
| 0a0698f6 CF |
419 | rtc0: rtc@fff04000 { |
| 420 | compatible = "arm,pl031", "arm,primecell"; | |
| 421 | reg = <0x0 0Xfff04000 0x0 0x1000>; | |
| 422 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| 423 | clocks = <&crg_ctrl HI3660_PCLK>; | |
| 424 | clock-names = "apb_pclk"; | |
| 425 | }; | |
| 426 | ||
| d94eab86 WX |
427 | gpio0: gpio@e8a0b000 { |
| 428 | compatible = "arm,pl061", "arm,primecell"; | |
| 429 | reg = <0 0xe8a0b000 0 0x1000>; | |
| 430 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| 431 | gpio-controller; | |
| 432 | #gpio-cells = <2>; | |
| 433 | gpio-ranges = <&pmx0 1 0 7>; | |
| 434 | interrupt-controller; | |
| 435 | #interrupt-cells = <2>; | |
| 436 | clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; | |
| 437 | clock-names = "apb_pclk"; | |
| 438 | }; | |
| 439 | ||
| 440 | gpio1: gpio@e8a0c000 { | |
| 441 | compatible = "arm,pl061", "arm,primecell"; | |
| 442 | reg = <0 0xe8a0c000 0 0x1000>; | |
| 443 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
| 444 | gpio-controller; | |
| 445 | #gpio-cells = <2>; | |
| 446 | gpio-ranges = <&pmx0 1 7 7>; | |
| 447 | interrupt-controller; | |
| 448 | #interrupt-cells = <2>; | |
| 449 | clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; | |
| 450 | clock-names = "apb_pclk"; | |
| 451 | }; | |
| 452 | ||
| 453 | gpio2: gpio@e8a0d000 { | |
| 454 | compatible = "arm,pl061", "arm,primecell"; | |
| 455 | reg = <0 0xe8a0d000 0 0x1000>; | |
| 456 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
| 457 | gpio-controller; | |
| 458 | #gpio-cells = <2>; | |
| 459 | gpio-ranges = <&pmx0 0 14 8>; | |
| 460 | interrupt-controller; | |
| 461 | #interrupt-cells = <2>; | |
| 462 | clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; | |
| 463 | clock-names = "apb_pclk"; | |
| 464 | }; | |
| 465 | ||
| 466 | gpio3: gpio@e8a0e000 { | |
| 467 | compatible = "arm,pl061", "arm,primecell"; | |
| 468 | reg = <0 0xe8a0e000 0 0x1000>; | |
| 469 | interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 470 | gpio-controller; | |
| 471 | #gpio-cells = <2>; | |
| 472 | gpio-ranges = <&pmx0 0 22 8>; | |
| 473 | interrupt-controller; | |
| 474 | #interrupt-cells = <2>; | |
| 475 | clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; | |
| 476 | clock-names = "apb_pclk"; | |
| 477 | }; | |
| 478 | ||
| 479 | gpio4: gpio@e8a0f000 { | |
| 480 | compatible = "arm,pl061", "arm,primecell"; | |
| 481 | reg = <0 0xe8a0f000 0 0x1000>; | |
| 482 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
| 483 | gpio-controller; | |
| 484 | #gpio-cells = <2>; | |
| 485 | gpio-ranges = <&pmx0 0 30 8>; | |
| 486 | interrupt-controller; | |
| 487 | #interrupt-cells = <2>; | |
| 488 | clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; | |
| 489 | clock-names = "apb_pclk"; | |
| 490 | }; | |
| 491 | ||
| 492 | gpio5: gpio@e8a10000 { | |
| 493 | compatible = "arm,pl061", "arm,primecell"; | |
| 494 | reg = <0 0xe8a10000 0 0x1000>; | |
| 495 | interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
| 496 | gpio-controller; | |
| 497 | #gpio-cells = <2>; | |
| 498 | gpio-ranges = <&pmx0 0 38 8>; | |
| 499 | interrupt-controller; | |
| 500 | #interrupt-cells = <2>; | |
| 501 | clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; | |
| 502 | clock-names = "apb_pclk"; | |
| 503 | }; | |
| 504 | ||
| 505 | gpio6: gpio@e8a11000 { | |
| 506 | compatible = "arm,pl061", "arm,primecell"; | |
| 507 | reg = <0 0xe8a11000 0 0x1000>; | |
| 508 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; | |
| 509 | gpio-controller; | |
| 510 | #gpio-cells = <2>; | |
| 511 | gpio-ranges = <&pmx0 0 46 8>; | |
| 512 | interrupt-controller; | |
| 513 | #interrupt-cells = <2>; | |
| 514 | clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; | |
| 515 | clock-names = "apb_pclk"; | |
| 516 | }; | |
| 517 | ||
| 518 | gpio7: gpio@e8a12000 { | |
| 519 | compatible = "arm,pl061", "arm,primecell"; | |
| 520 | reg = <0 0xe8a12000 0 0x1000>; | |
| 521 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; | |
| 522 | gpio-controller; | |
| 523 | #gpio-cells = <2>; | |
| 524 | gpio-ranges = <&pmx0 0 54 8>; | |
| 525 | interrupt-controller; | |
| 526 | #interrupt-cells = <2>; | |
| 527 | clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; | |
| 528 | clock-names = "apb_pclk"; | |
| 529 | }; | |
| 530 | ||
| 531 | gpio8: gpio@e8a13000 { | |
| 532 | compatible = "arm,pl061", "arm,primecell"; | |
| 533 | reg = <0 0xe8a13000 0 0x1000>; | |
| 534 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; | |
| 535 | gpio-controller; | |
| 536 | #gpio-cells = <2>; | |
| 537 | gpio-ranges = <&pmx0 0 62 8>; | |
| 538 | interrupt-controller; | |
| 539 | #interrupt-cells = <2>; | |
| 540 | clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; | |
| 541 | clock-names = "apb_pclk"; | |
| 542 | }; | |
| 543 | ||
| 544 | gpio9: gpio@e8a14000 { | |
| 545 | compatible = "arm,pl061", "arm,primecell"; | |
| 546 | reg = <0 0xe8a14000 0 0x1000>; | |
| 547 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; | |
| 548 | gpio-controller; | |
| 549 | #gpio-cells = <2>; | |
| 550 | gpio-ranges = <&pmx0 0 70 8>; | |
| 551 | interrupt-controller; | |
| 552 | #interrupt-cells = <2>; | |
| 553 | clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; | |
| 554 | clock-names = "apb_pclk"; | |
| 555 | }; | |
| 556 | ||
| 557 | gpio10: gpio@e8a15000 { | |
| 558 | compatible = "arm,pl061", "arm,primecell"; | |
| 559 | reg = <0 0xe8a15000 0 0x1000>; | |
| 560 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
| 561 | gpio-controller; | |
| 562 | #gpio-cells = <2>; | |
| 563 | gpio-ranges = <&pmx0 0 78 8>; | |
| 564 | interrupt-controller; | |
| 565 | #interrupt-cells = <2>; | |
| 566 | clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; | |
| 567 | clock-names = "apb_pclk"; | |
| 568 | }; | |
| 569 | ||
| 570 | gpio11: gpio@e8a16000 { | |
| 571 | compatible = "arm,pl061", "arm,primecell"; | |
| 572 | reg = <0 0xe8a16000 0 0x1000>; | |
| 573 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
| 574 | gpio-controller; | |
| 575 | #gpio-cells = <2>; | |
| 576 | gpio-ranges = <&pmx0 0 86 8>; | |
| 577 | interrupt-controller; | |
| 578 | #interrupt-cells = <2>; | |
| 579 | clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; | |
| 580 | clock-names = "apb_pclk"; | |
| 581 | }; | |
| 582 | ||
| 583 | gpio12: gpio@e8a17000 { | |
| 584 | compatible = "arm,pl061", "arm,primecell"; | |
| 585 | reg = <0 0xe8a17000 0 0x1000>; | |
| 586 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| 587 | gpio-controller; | |
| 588 | #gpio-cells = <2>; | |
| 589 | gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; | |
| 590 | interrupt-controller; | |
| 591 | #interrupt-cells = <2>; | |
| 592 | clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; | |
| 593 | clock-names = "apb_pclk"; | |
| 594 | }; | |
| 595 | ||
| 596 | gpio13: gpio@e8a18000 { | |
| 597 | compatible = "arm,pl061", "arm,primecell"; | |
| 598 | reg = <0 0xe8a18000 0 0x1000>; | |
| 599 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| 600 | gpio-controller; | |
| 601 | #gpio-cells = <2>; | |
| 602 | gpio-ranges = <&pmx0 0 102 8>; | |
| 603 | interrupt-controller; | |
| 604 | #interrupt-cells = <2>; | |
| 605 | clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; | |
| 606 | clock-names = "apb_pclk"; | |
| 607 | }; | |
| 608 | ||
| 609 | gpio14: gpio@e8a19000 { | |
| 610 | compatible = "arm,pl061", "arm,primecell"; | |
| 611 | reg = <0 0xe8a19000 0 0x1000>; | |
| 612 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 613 | gpio-controller; | |
| 614 | #gpio-cells = <2>; | |
| 615 | gpio-ranges = <&pmx0 0 110 8>; | |
| 616 | interrupt-controller; | |
| 617 | #interrupt-cells = <2>; | |
| 618 | clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; | |
| 619 | clock-names = "apb_pclk"; | |
| 620 | }; | |
| 621 | ||
| 622 | gpio15: gpio@e8a1a000 { | |
| 623 | compatible = "arm,pl061", "arm,primecell"; | |
| 624 | reg = <0 0xe8a1a000 0 0x1000>; | |
| 625 | interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; | |
| 626 | gpio-controller; | |
| 627 | #gpio-cells = <2>; | |
| 628 | gpio-ranges = <&pmx0 0 118 6>; | |
| 629 | interrupt-controller; | |
| 630 | #interrupt-cells = <2>; | |
| 631 | clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; | |
| 632 | clock-names = "apb_pclk"; | |
| 633 | }; | |
| 634 | ||
| 635 | gpio16: gpio@e8a1b000 { | |
| 636 | compatible = "arm,pl061", "arm,primecell"; | |
| 637 | reg = <0 0xe8a1b000 0 0x1000>; | |
| 638 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 639 | gpio-controller; | |
| 640 | #gpio-cells = <2>; | |
| 641 | interrupt-controller; | |
| 642 | #interrupt-cells = <2>; | |
| 643 | clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; | |
| 644 | clock-names = "apb_pclk"; | |
| 645 | }; | |
| 646 | ||
| 647 | gpio17: gpio@e8a1c000 { | |
| 648 | compatible = "arm,pl061", "arm,primecell"; | |
| 649 | reg = <0 0xe8a1c000 0 0x1000>; | |
| 650 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 651 | gpio-controller; | |
| 652 | #gpio-cells = <2>; | |
| 653 | interrupt-controller; | |
| 654 | #interrupt-cells = <2>; | |
| 655 | clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; | |
| 656 | clock-names = "apb_pclk"; | |
| 657 | }; | |
| 658 | ||
| 659 | gpio18: gpio@ff3b4000 { | |
| 660 | compatible = "arm,pl061", "arm,primecell"; | |
| 661 | reg = <0 0xff3b4000 0 0x1000>; | |
| 662 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
| 663 | gpio-controller; | |
| 664 | #gpio-cells = <2>; | |
| 665 | gpio-ranges = <&pmx2 0 0 8>; | |
| 666 | interrupt-controller; | |
| 667 | #interrupt-cells = <2>; | |
| 668 | clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; | |
| 669 | clock-names = "apb_pclk"; | |
| 670 | }; | |
| 671 | ||
| 672 | gpio19: gpio@ff3b5000 { | |
| 673 | compatible = "arm,pl061", "arm,primecell"; | |
| 674 | reg = <0 0xff3b5000 0 0x1000>; | |
| 675 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; | |
| 676 | gpio-controller; | |
| 677 | #gpio-cells = <2>; | |
| 678 | gpio-ranges = <&pmx2 0 8 4>; | |
| 679 | interrupt-controller; | |
| 680 | #interrupt-cells = <2>; | |
| 681 | clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; | |
| 682 | clock-names = "apb_pclk"; | |
| 683 | }; | |
| 684 | ||
| 685 | gpio20: gpio@e8a1f000 { | |
| 686 | compatible = "arm,pl061", "arm,primecell"; | |
| 687 | reg = <0 0xe8a1f000 0 0x1000>; | |
| 688 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; | |
| 689 | gpio-controller; | |
| 690 | #gpio-cells = <2>; | |
| 691 | gpio-ranges = <&pmx1 0 0 6>; | |
| 692 | interrupt-controller; | |
| 693 | #interrupt-cells = <2>; | |
| 694 | clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; | |
| 695 | clock-names = "apb_pclk"; | |
| 696 | }; | |
| 697 | ||
| 698 | gpio21: gpio@e8a20000 { | |
| 699 | compatible = "arm,pl061", "arm,primecell"; | |
| 700 | reg = <0 0xe8a20000 0 0x1000>; | |
| 701 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
| 702 | gpio-controller; | |
| 703 | #gpio-cells = <2>; | |
| 704 | interrupt-controller; | |
| 705 | #interrupt-cells = <2>; | |
| 706 | gpio-ranges = <&pmx3 0 0 6>; | |
| 707 | clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; | |
| 708 | clock-names = "apb_pclk"; | |
| 709 | }; | |
| 710 | ||
| 711 | gpio22: gpio@fff0b000 { | |
| 712 | compatible = "arm,pl061", "arm,primecell"; | |
| 713 | reg = <0 0xfff0b000 0 0x1000>; | |
| 714 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
| 715 | gpio-controller; | |
| 716 | #gpio-cells = <2>; | |
| 717 | /* GPIO176 */ | |
| 718 | gpio-ranges = <&pmx4 2 0 6>; | |
| 719 | interrupt-controller; | |
| 720 | #interrupt-cells = <2>; | |
| 721 | clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; | |
| 722 | clock-names = "apb_pclk"; | |
| 723 | }; | |
| 724 | ||
| 725 | gpio23: gpio@fff0c000 { | |
| 726 | compatible = "arm,pl061", "arm,primecell"; | |
| 727 | reg = <0 0xfff0c000 0 0x1000>; | |
| 728 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
| 729 | gpio-controller; | |
| 730 | #gpio-cells = <2>; | |
| 731 | /* GPIO184 */ | |
| 732 | gpio-ranges = <&pmx4 0 6 7>; | |
| 733 | interrupt-controller; | |
| 734 | #interrupt-cells = <2>; | |
| 735 | clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; | |
| 736 | clock-names = "apb_pclk"; | |
| 737 | }; | |
| 738 | ||
| 739 | gpio24: gpio@fff0d000 { | |
| 740 | compatible = "arm,pl061", "arm,primecell"; | |
| 741 | reg = <0 0xfff0d000 0 0x1000>; | |
| 742 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 743 | gpio-controller; | |
| 744 | #gpio-cells = <2>; | |
| 745 | /* GPIO192 */ | |
| 746 | gpio-ranges = <&pmx4 0 13 8>; | |
| 747 | interrupt-controller; | |
| 748 | #interrupt-cells = <2>; | |
| 749 | clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; | |
| 750 | clock-names = "apb_pclk"; | |
| 751 | }; | |
| 752 | ||
| 753 | gpio25: gpio@fff0e000 { | |
| 754 | compatible = "arm,pl061", "arm,primecell"; | |
| 755 | reg = <0 0xfff0e000 0 0x1000>; | |
| 756 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
| 757 | gpio-controller; | |
| 758 | #gpio-cells = <2>; | |
| 759 | /* GPIO200 */ | |
| 760 | gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; | |
| 761 | interrupt-controller; | |
| 762 | #interrupt-cells = <2>; | |
| 763 | clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; | |
| 764 | clock-names = "apb_pclk"; | |
| 765 | }; | |
| 766 | ||
| 767 | gpio26: gpio@fff0f000 { | |
| 768 | compatible = "arm,pl061", "arm,primecell"; | |
| 769 | reg = <0 0xfff0f000 0 0x1000>; | |
| 770 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
| 771 | gpio-controller; | |
| 772 | #gpio-cells = <2>; | |
| 773 | /* GPIO208 */ | |
| 774 | gpio-ranges = <&pmx4 0 28 8>; | |
| 775 | interrupt-controller; | |
| 776 | #interrupt-cells = <2>; | |
| 777 | clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; | |
| 778 | clock-names = "apb_pclk"; | |
| 779 | }; | |
| 780 | ||
| 781 | gpio27: gpio@fff10000 { | |
| 782 | compatible = "arm,pl061", "arm,primecell"; | |
| 783 | reg = <0 0xfff10000 0 0x1000>; | |
| 784 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
| 785 | gpio-controller; | |
| 786 | #gpio-cells = <2>; | |
| 787 | /* GPIO216 */ | |
| 788 | gpio-ranges = <&pmx4 0 36 6>; | |
| 789 | interrupt-controller; | |
| 790 | #interrupt-cells = <2>; | |
| 791 | clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; | |
| 792 | clock-names = "apb_pclk"; | |
| 793 | }; | |
| 794 | ||
| 795 | gpio28: gpio@fff1d000 { | |
| 796 | compatible = "arm,pl061", "arm,primecell"; | |
| 797 | reg = <0 0xfff1d000 0 0x1000>; | |
| 798 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; | |
| 799 | gpio-controller; | |
| 800 | #gpio-cells = <2>; | |
| 801 | interrupt-controller; | |
| 802 | #interrupt-cells = <2>; | |
| 803 | clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; | |
| 804 | clock-names = "apb_pclk"; | |
| 805 | }; | |
| 38810497 WX |
806 | |
| 807 | spi2: spi@ffd68000 { | |
| 808 | compatible = "arm,pl022", "arm,primecell"; | |
| 809 | reg = <0x0 0xffd68000 0x0 0x1000>; | |
| 810 | #address-cells = <1>; | |
| 811 | #size-cells = <0>; | |
| 812 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 813 | clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; | |
| 814 | clock-names = "apb_pclk"; | |
| 815 | pinctrl-names = "default"; | |
| 816 | pinctrl-0 = <&spi2_pmx_func>; | |
| 817 | num-cs = <1>; | |
| 818 | cs-gpios = <&gpio27 2 0>; | |
| 819 | status = "disabled"; | |
| 820 | }; | |
| 821 | ||
| 822 | spi3: spi@ff3b3000 { | |
| 823 | compatible = "arm,pl022", "arm,primecell"; | |
| 824 | reg = <0x0 0xff3b3000 0x0 0x1000>; | |
| 825 | #address-cells = <1>; | |
| 826 | #size-cells = <0>; | |
| 827 | interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; | |
| 828 | clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; | |
| 829 | clock-names = "apb_pclk"; | |
| 830 | pinctrl-names = "default"; | |
| 831 | pinctrl-0 = <&spi3_pmx_func>; | |
| 832 | num-cs = <1>; | |
| 833 | cs-gpios = <&gpio18 5 0>; | |
| 834 | status = "disabled"; | |
| 835 | }; | |
| 96909778 XS |
836 | |
| 837 | pcie@f4000000 { | |
| 838 | compatible = "hisilicon,kirin960-pcie"; | |
| 839 | reg = <0x0 0xf4000000 0x0 0x1000>, | |
| 840 | <0x0 0xff3fe000 0x0 0x1000>, | |
| 841 | <0x0 0xf3f20000 0x0 0x40000>, | |
| 842 | <0x0 0xf5000000 0x0 0x2000>; | |
| 843 | reg-names = "dbi", "apb", "phy", "config"; | |
| 844 | bus-range = <0x0 0x1>; | |
| 845 | #address-cells = <3>; | |
| 846 | #size-cells = <2>; | |
| 847 | device_type = "pci"; | |
| 848 | ranges = <0x02000000 0x0 0x00000000 | |
| 849 | 0x0 0xf6000000 | |
| 850 | 0x0 0x02000000>; | |
| 851 | num-lanes = <1>; | |
| 852 | #interrupt-cells = <1>; | |
| 853 | interrupt-map-mask = <0xf800 0 0 7>; | |
| 854 | interrupt-map = <0x0 0 0 1 | |
| 855 | &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, | |
| 856 | <0x0 0 0 2 | |
| 857 | &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, | |
| 858 | <0x0 0 0 3 | |
| 859 | &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, | |
| 860 | <0x0 0 0 4 | |
| 861 | &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; | |
| 862 | clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, | |
| 863 | <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, | |
| 864 | <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, | |
| 865 | <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, | |
| 866 | <&crg_ctrl HI3660_ACLK_GATE_PCIE>; | |
| 867 | clock-names = "pcie_phy_ref", "pcie_aux", | |
| 868 | "pcie_apb_phy", "pcie_apb_sys", | |
| 869 | "pcie_aclk"; | |
| 870 | reset-gpios = <&gpio11 1 0 >; | |
| 871 | }; | |
| 804d7d7a LW |
872 | |
| 873 | /* SD */ | |
| 874 | dwmmc1: dwmmc1@ff37f000 { | |
| 875 | #address-cells = <1>; | |
| 876 | #size-cells = <0>; | |
| 877 | cd-inverted; | |
| 878 | compatible = "hisilicon,hi3660-dw-mshc"; | |
| 879 | num-slots = <1>; | |
| 880 | bus-width = <0x4>; | |
| 881 | disable-wp; | |
| 882 | cap-sd-highspeed; | |
| 883 | supports-highspeed; | |
| 884 | card-detect-delay = <200>; | |
| 885 | reg = <0x0 0xff37f000 0x0 0x1000>; | |
| 886 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; | |
| 887 | clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, | |
| 888 | <&crg_ctrl HI3660_HCLK_GATE_SD>; | |
| 889 | clock-names = "ciu", "biu"; | |
| 890 | clock-frequency = <3200000>; | |
| 891 | resets = <&crg_rst 0x94 18>; | |
| 892 | cd-gpios = <&gpio25 3 0>; | |
| 893 | hisilicon,peripheral-syscon = <&sctrl>; | |
| 894 | pinctrl-names = "default"; | |
| 895 | pinctrl-0 = <&sd_pmx_func | |
| 896 | &sd_clk_cfg_func | |
| 897 | &sd_cfg_func>; | |
| 898 | sd-uhs-sdr12; | |
| 899 | sd-uhs-sdr25; | |
| 900 | sd-uhs-sdr50; | |
| 901 | sd-uhs-sdr104; | |
| 902 | status = "disabled"; | |
| 903 | ||
| 904 | slot@0 { | |
| 905 | reg = <0x0>; | |
| 906 | bus-width = <4>; | |
| 907 | disable-wp; | |
| 908 | }; | |
| 909 | }; | |
| 910 | ||
| 911 | /* SDIO */ | |
| 912 | dwmmc2: dwmmc2@ff3ff000 { | |
| 913 | compatible = "hisilicon,hi3660-dw-mshc"; | |
| 914 | reg = <0x0 0xff3ff000 0x0 0x1000>; | |
| 915 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; | |
| 916 | num-slots = <1>; | |
| 917 | clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, | |
| 918 | <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; | |
| 919 | clock-names = "ciu", "biu"; | |
| 920 | resets = <&crg_rst 0x94 20>; | |
| 921 | card-detect-delay = <200>; | |
| 922 | supports-highspeed; | |
| 923 | keep-power-in-suspend; | |
| 924 | pinctrl-names = "default"; | |
| 925 | pinctrl-0 = <&sdio_pmx_func | |
| 926 | &sdio_clk_cfg_func | |
| 927 | &sdio_cfg_func>; | |
| 928 | status = "disabled"; | |
| 929 | }; | |
| 35ca8168 CF |
930 | }; |
| 931 | }; |