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arm64: dts: hi3660: add bindings for DMA
[linux-2.6-block.git] / arch / arm64 / boot / dts / hisilicon / hi3660.dtsi
CommitLineData
35ca8168
CF		 1/*
2 * dts file for Hisilicon Hi3660 SoC
3 *
4 * Copyright (C) 2016, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
a4e36ae0 8#include <dt-bindings/clock/hi3660-clock.h>
35ca8168
CF		 9
10/ {
11 compatible = "hisilicon,hi3660";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 psci {
17 compatible = "arm,psci-0.2";
18 method = "smc";
19 };
20
21 cpus {
22 #address-cells = <2>;
23 #size-cells = <0>;
24
25 cpu-map {
26 cluster0 {
27 core0 {
28 cpu = <&cpu0>;
29 };
30 core1 {
31 cpu = <&cpu1>;
32 };
33 core2 {
34 cpu = <&cpu2>;
35 };
36 core3 {
37 cpu = <&cpu3>;
38 };
39 };
40 cluster1 {
41 core0 {
42 cpu = <&cpu4>;
43 };
44 core1 {
45 cpu = <&cpu5>;
46 };
47 core2 {
48 cpu = <&cpu6>;
49 };
50 core3 {
51 cpu = <&cpu7>;
52 };
53 };
54 };
55
56 cpu0: cpu@0 {
57 compatible = "arm,cortex-a53", "arm,armv8";
58 device_type = "cpu";
59 reg = <0x0 0x0>;
60 enable-method = "psci";
a6d08344 61 next-level-cache = <&A53_L2>;
30fec826 62 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
35ca8168
CF		 63 };
64
65 cpu1: cpu@1 {
66 compatible = "arm,cortex-a53", "arm,armv8";
67 device_type = "cpu";
68 reg = <0x0 0x1>;
69 enable-method = "psci";
a6d08344 70 next-level-cache = <&A53_L2>;
30fec826 71 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
35ca8168
CF		 72 };
73
74 cpu2: cpu@2 {
75 compatible = "arm,cortex-a53", "arm,armv8";
76 device_type = "cpu";
77 reg = <0x0 0x2>;
78 enable-method = "psci";
a6d08344 79 next-level-cache = <&A53_L2>;
30fec826 80 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
35ca8168
CF		 81 };
82
83 cpu3: cpu@3 {
84 compatible = "arm,cortex-a53", "arm,armv8";
85 device_type = "cpu";
86 reg = <0x0 0x3>;
87 enable-method = "psci";
a6d08344 88 next-level-cache = <&A53_L2>;
30fec826 89 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
35ca8168
CF		 90 };
91
92 cpu4: cpu@100 {
93 compatible = "arm,cortex-a73", "arm,armv8";
94 device_type = "cpu";
95 reg = <0x0 0x100>;
96 enable-method = "psci";
a6d08344 97 next-level-cache = <&A73_L2>;
30fec826
LY		 98 cpu-idle-states = <
99 &CPU_NAP
100 &CPU_SLEEP
101 &CLUSTER_SLEEP_1
102 >;
35ca8168
CF		 103 };
104
105 cpu5: cpu@101 {
106 compatible = "arm,cortex-a73", "arm,armv8";
107 device_type = "cpu";
108 reg = <0x0 0x101>;
109 enable-method = "psci";
a6d08344 110 next-level-cache = <&A73_L2>;
30fec826
LY		 111 cpu-idle-states = <
112 &CPU_NAP
113 &CPU_SLEEP
114 &CLUSTER_SLEEP_1
115 >;
35ca8168
CF		 116 };
117
118 cpu6: cpu@102 {
119 compatible = "arm,cortex-a73", "arm,armv8";
120 device_type = "cpu";
121 reg = <0x0 0x102>;
122 enable-method = "psci";
a6d08344 123 next-level-cache = <&A73_L2>;
30fec826
LY		 124 cpu-idle-states = <
125 &CPU_NAP
126 &CPU_SLEEP
127 &CLUSTER_SLEEP_1
128 >;
35ca8168
CF		 129 };
130
131 cpu7: cpu@103 {
132 compatible = "arm,cortex-a73", "arm,armv8";
133 device_type = "cpu";
134 reg = <0x0 0x103>;
135 enable-method = "psci";
a6d08344 136 next-level-cache = <&A73_L2>;
30fec826
LY		 137 cpu-idle-states = <
138 &CPU_NAP
139 &CPU_SLEEP
140 &CLUSTER_SLEEP_1
141 >;
142 };
143
144 idle-states {
145 entry-method = "psci";
146
147 CPU_NAP: cpu-nap {
148 compatible = "arm,idle-state";
149 arm,psci-suspend-param = <0x0000001>;
150 entry-latency-us = <7>;
151 exit-latency-us = <2>;
152 min-residency-us = <15>;
153 };
154
155 CPU_SLEEP: cpu-sleep {
156 compatible = "arm,idle-state";
157 local-timer-stop;
158 arm,psci-suspend-param = <0x0010000>;
159 entry-latency-us = <40>;
160 exit-latency-us = <70>;
161 min-residency-us = <3000>;
162 };
163
164 CLUSTER_SLEEP_0: cluster-sleep-0 {
165 compatible = "arm,idle-state";
166 local-timer-stop;
167 arm,psci-suspend-param = <0x1010000>;
168 entry-latency-us = <500>;
169 exit-latency-us = <5000>;
170 min-residency-us = <20000>;
171 };
172
173 CLUSTER_SLEEP_1: cluster-sleep-1 {
174 compatible = "arm,idle-state";
175 local-timer-stop;
176 arm,psci-suspend-param = <0x1010000>;
177 entry-latency-us = <1000>;
178 exit-latency-us = <5000>;
179 min-residency-us = <20000>;
180 };
35ca8168 181 };
a6d08344
LY		 182
183 A53_L2: l2-cache0 {
184 compatible = "cache";
185 };
186
187 A73_L2: l2-cache1 {
188 compatible = "cache";
189 };
35ca8168
CF		 190 };
191
192 gic: interrupt-controller@e82b0000 {
193 compatible = "arm,gic-400";
194 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
195 <0x0 0xe82b2000 0 0x2000>, /* GICC */
196 <0x0 0xe82b4000 0 0x2000>, /* GICH */
197 <0x0 0xe82b6000 0 0x2000>; /* GICV */
198 #address-cells = <0>;
199 #interrupt-cells = <3>;
200 interrupt-controller;
201 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
202 IRQ_TYPE_LEVEL_HIGH)>;
203 };
204
f8054fb8
YX		 205 pmu {
206 compatible = "arm,armv8-pmuv3";
207 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-affinity = <&cpu0>,
216 <&cpu1>,
217 <&cpu2>,
218 <&cpu3>,
219 <&cpu4>,
220 <&cpu5>,
221 <&cpu6>,
222 <&cpu7>;
223 };
224
35ca8168
CF		 225 timer {
226 compatible = "arm,armv8-timer";
227 interrupt-parent = <&gic>;
228 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
229 IRQ_TYPE_LEVEL_LOW)>,
230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
231 IRQ_TYPE_LEVEL_LOW)>,
232 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
233 IRQ_TYPE_LEVEL_LOW)>,
234 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
235 IRQ_TYPE_LEVEL_LOW)>;
236 };
237
238 soc {
239 compatible = "simple-bus";
240 #address-cells = <2>;
241 #size-cells = <2>;
242 ranges;
243
a4e36ae0
ZG		 244 crg_ctrl: crg_ctrl@fff35000 {
245 compatible = "hisilicon,hi3660-crgctrl", "syscon";
246 reg = <0x0 0xfff35000 0x0 0x1000>;
247 #clock-cells = <1>;
35ca8168
CF		 248 };
249
a4e36ae0
ZG		 250 crg_rst: crg_rst_controller {
251 compatible = "hisilicon,hi3660-reset";
252 #reset-cells = <2>;
253 hisi,rst-syscon = <&crg_ctrl>;
254 };
255
256
257 pctrl: pctrl@e8a09000 {
258 compatible = "hisilicon,hi3660-pctrl", "syscon";
259 reg = <0x0 0xe8a09000 0x0 0x2000>;
260 #clock-cells = <1>;
261 };
262
263 pmuctrl: crg_ctrl@fff34000 {
264 compatible = "hisilicon,hi3660-pmuctrl", "syscon";
265 reg = <0x0 0xfff34000 0x0 0x1000>;
266 #clock-cells = <1>;
267 };
268
269 sctrl: sctrl@fff0a000 {
270 compatible = "hisilicon,hi3660-sctrl", "syscon";
271 reg = <0x0 0xfff0a000 0x0 0x1000>;
272 #clock-cells = <1>;
273 };
274
275 iomcu: iomcu@ffd7e000 {
276 compatible = "hisilicon,hi3660-iomcu", "syscon";
277 reg = <0x0 0xffd7e000 0x0 0x1000>;
278 #clock-cells = <1>;
279
280 };
281
282 iomcu_rst: reset {
283 compatible = "hisilicon,hi3660-reset";
284 hisi,rst-syscon = <&iomcu>;
285 #reset-cells = <2>;
286 };
287
75196330
LY		 288 dual_timer0: timer@fff14000 {
289 compatible = "arm,sp804", "arm,primecell";
290 reg = <0x0 0xfff14000 0x0 0x1000>;
291 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&crg_ctrl HI3660_OSC32K>,
294 <&crg_ctrl HI3660_OSC32K>,
295 <&crg_ctrl HI3660_OSC32K>;
296 clock-names = "timer1", "timer2", "apb_pclk";
297 };
298
5f8a3b77
ZG		 299 i2c0: i2c@ffd71000 {
300 compatible = "snps,designware-i2c";
301 reg = <0x0 0xffd71000 0x0 0x1000>;
302 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 clock-frequency = <400000>;
306 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
307 resets = <&iomcu_rst 0x20 3>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
310 status = "disabled";
311 };
312
313 i2c1: i2c@ffd72000 {
314 compatible = "snps,designware-i2c";
315 reg = <0x0 0xffd72000 0x0 0x1000>;
316 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 clock-frequency = <400000>;
320 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
321 resets = <&iomcu_rst 0x20 4>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
324 status = "disabled";
325 };
326
327 i2c3: i2c@fdf0c000 {
328 compatible = "snps,designware-i2c";
329 reg = <0x0 0xfdf0c000 0x0 0x1000>;
330 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
331 #address-cells = <1>;
332 #size-cells = <0>;
333 clock-frequency = <400000>;
334 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
335 resets = <&crg_rst 0x78 7>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
338 status = "disabled";
339 };
340
341 i2c7: i2c@fdf0b000 {
342 compatible = "snps,designware-i2c";
343 reg = <0x0 0xfdf0b000 0x0 0x1000>;
344 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 clock-frequency = <400000>;
348 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
349 resets = <&crg_rst 0x60 14>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
352 status = "disabled";
353 };
354
254b07b2
CF		 355 uart0: serial@fdf02000 {
356 compatible = "arm,pl011", "arm,primecell";
357 reg = <0x0 0xfdf02000 0x0 0x1000>;
358 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
360 <&crg_ctrl HI3660_PCLK>;
361 clock-names = "uartclk", "apb_pclk";
362 pinctrl-names = "default";
363 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
364 status = "disabled";
365 };
366
367 uart1: serial@fdf00000 {
368 compatible = "arm,pl011", "arm,primecell";
369 reg = <0x0 0xfdf00000 0x0 0x1000>;
370 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
372 <&crg_ctrl HI3660_CLK_GATE_UART1>;
373 clock-names = "uartclk", "apb_pclk";
374 pinctrl-names = "default";
375 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
376 status = "disabled";
377 };
378
379 uart2: serial@fdf03000 {
380 compatible = "arm,pl011", "arm,primecell";
381 reg = <0x0 0xfdf03000 0x0 0x1000>;
382 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
384 <&crg_ctrl HI3660_PCLK>;
385 clock-names = "uartclk", "apb_pclk";
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
388 status = "disabled";
389 };
390
391 uart3: serial@ffd74000 {
392 compatible = "arm,pl011", "arm,primecell";
393 reg = <0x0 0xffd74000 0x0 0x1000>;
394 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
396 <&crg_ctrl HI3660_PCLK>;
397 clock-names = "uartclk", "apb_pclk";
398 pinctrl-names = "default";
399 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
400 status = "disabled";
401 };
402
403 uart4: serial@fdf01000 {
404 compatible = "arm,pl011", "arm,primecell";
405 reg = <0x0 0xfdf01000 0x0 0x1000>;
406 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
408 <&crg_ctrl HI3660_CLK_GATE_UART4>;
409 clock-names = "uartclk", "apb_pclk";
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
412 status = "disabled";
413 };
414
a4e36ae0 415 uart5: serial@fdf05000 {
35ca8168
CF		 416 compatible = "arm,pl011", "arm,primecell";
417 reg = <0x0 0xfdf05000 0x0 0x1000>;
418 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
a4e36ae0
ZG		 419 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
420 <&crg_ctrl HI3660_CLK_GATE_UART5>;
35ca8168 421 clock-names = "uartclk", "apb_pclk";
254b07b2
CF		 422 pinctrl-names = "default";
423 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
424 status = "disabled";
425 };
426
427 uart6: serial@fff32000 {
428 compatible = "arm,pl011", "arm,primecell";
429 reg = <0x0 0xfff32000 0x0 0x1000>;
430 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&crg_ctrl HI3660_CLK_UART6>,
432 <&crg_ctrl HI3660_PCLK>;
433 clock-names = "uartclk", "apb_pclk";
434 pinctrl-names = "default";
435 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
35ca8168
CF		 436 status = "disabled";
437 };
d94eab86 438
0b507e91
WR		 439 dma0: dma@fdf30000 {
440 compatible = "hisilicon,k3-dma-1.0";
441 reg = <0x0 0xfdf30000 0x0 0x1000>;
442 #dma-cells = <1>;
443 dma-channels = <16>;
444 dma-requests = <32>;
445 dma-min-chan = <1>;
446 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
448 dma-no-cci;
449 dma-type = "hi3660_dma";
450 };
451
0a0698f6
CF		 452 rtc0: rtc@fff04000 {
453 compatible = "arm,pl031", "arm,primecell";
454 reg = <0x0 0Xfff04000 0x0 0x1000>;
455 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&crg_ctrl HI3660_PCLK>;
457 clock-names = "apb_pclk";
458 };
459
d94eab86
WX		 460 gpio0: gpio@e8a0b000 {
461 compatible = "arm,pl061", "arm,primecell";
462 reg = <0 0xe8a0b000 0 0x1000>;
463 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
464 gpio-controller;
465 #gpio-cells = <2>;
466 gpio-ranges = <&pmx0 1 0 7>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
470 clock-names = "apb_pclk";
471 };
472
473 gpio1: gpio@e8a0c000 {
474 compatible = "arm,pl061", "arm,primecell";
475 reg = <0 0xe8a0c000 0 0x1000>;
476 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 gpio-ranges = <&pmx0 1 7 7>;
480 interrupt-controller;
481 #interrupt-cells = <2>;
482 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
483 clock-names = "apb_pclk";
484 };
485
486 gpio2: gpio@e8a0d000 {
487 compatible = "arm,pl061", "arm,primecell";
488 reg = <0 0xe8a0d000 0 0x1000>;
489 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
490 gpio-controller;
491 #gpio-cells = <2>;
492 gpio-ranges = <&pmx0 0 14 8>;
493 interrupt-controller;
494 #interrupt-cells = <2>;
495 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
496 clock-names = "apb_pclk";
497 };
498
499 gpio3: gpio@e8a0e000 {
500 compatible = "arm,pl061", "arm,primecell";
501 reg = <0 0xe8a0e000 0 0x1000>;
502 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
503 gpio-controller;
504 #gpio-cells = <2>;
505 gpio-ranges = <&pmx0 0 22 8>;
506 interrupt-controller;
507 #interrupt-cells = <2>;
508 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
509 clock-names = "apb_pclk";
510 };
511
512 gpio4: gpio@e8a0f000 {
513 compatible = "arm,pl061", "arm,primecell";
514 reg = <0 0xe8a0f000 0 0x1000>;
515 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
516 gpio-controller;
517 #gpio-cells = <2>;
518 gpio-ranges = <&pmx0 0 30 8>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
521 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
522 clock-names = "apb_pclk";
523 };
524
525 gpio5: gpio@e8a10000 {
526 compatible = "arm,pl061", "arm,primecell";
527 reg = <0 0xe8a10000 0 0x1000>;
528 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
529 gpio-controller;
530 #gpio-cells = <2>;
531 gpio-ranges = <&pmx0 0 38 8>;
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
535 clock-names = "apb_pclk";
536 };
537
538 gpio6: gpio@e8a11000 {
539 compatible = "arm,pl061", "arm,primecell";
540 reg = <0 0xe8a11000 0 0x1000>;
541 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
542 gpio-controller;
543 #gpio-cells = <2>;
544 gpio-ranges = <&pmx0 0 46 8>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
548 clock-names = "apb_pclk";
549 };
550
551 gpio7: gpio@e8a12000 {
552 compatible = "arm,pl061", "arm,primecell";
553 reg = <0 0xe8a12000 0 0x1000>;
554 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
555 gpio-controller;
556 #gpio-cells = <2>;
557 gpio-ranges = <&pmx0 0 54 8>;
558 interrupt-controller;
559 #interrupt-cells = <2>;
560 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
561 clock-names = "apb_pclk";
562 };
563
564 gpio8: gpio@e8a13000 {
565 compatible = "arm,pl061", "arm,primecell";
566 reg = <0 0xe8a13000 0 0x1000>;
567 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
568 gpio-controller;
569 #gpio-cells = <2>;
570 gpio-ranges = <&pmx0 0 62 8>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
574 clock-names = "apb_pclk";
575 };
576
577 gpio9: gpio@e8a14000 {
578 compatible = "arm,pl061", "arm,primecell";
579 reg = <0 0xe8a14000 0 0x1000>;
580 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
581 gpio-controller;
582 #gpio-cells = <2>;
583 gpio-ranges = <&pmx0 0 70 8>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
587 clock-names = "apb_pclk";
588 };
589
590 gpio10: gpio@e8a15000 {
591 compatible = "arm,pl061", "arm,primecell";
592 reg = <0 0xe8a15000 0 0x1000>;
593 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
594 gpio-controller;
595 #gpio-cells = <2>;
596 gpio-ranges = <&pmx0 0 78 8>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
600 clock-names = "apb_pclk";
601 };
602
603 gpio11: gpio@e8a16000 {
604 compatible = "arm,pl061", "arm,primecell";
605 reg = <0 0xe8a16000 0 0x1000>;
606 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
607 gpio-controller;
608 #gpio-cells = <2>;
609 gpio-ranges = <&pmx0 0 86 8>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
612 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
613 clock-names = "apb_pclk";
614 };
615
616 gpio12: gpio@e8a17000 {
617 compatible = "arm,pl061", "arm,primecell";
618 reg = <0 0xe8a17000 0 0x1000>;
619 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
620 gpio-controller;
621 #gpio-cells = <2>;
622 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
625 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
626 clock-names = "apb_pclk";
627 };
628
629 gpio13: gpio@e8a18000 {
630 compatible = "arm,pl061", "arm,primecell";
631 reg = <0 0xe8a18000 0 0x1000>;
632 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
633 gpio-controller;
634 #gpio-cells = <2>;
635 gpio-ranges = <&pmx0 0 102 8>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
638 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
639 clock-names = "apb_pclk";
640 };
641
642 gpio14: gpio@e8a19000 {
643 compatible = "arm,pl061", "arm,primecell";
644 reg = <0 0xe8a19000 0 0x1000>;
645 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
646 gpio-controller;
647 #gpio-cells = <2>;
648 gpio-ranges = <&pmx0 0 110 8>;
649 interrupt-controller;
650 #interrupt-cells = <2>;
651 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
652 clock-names = "apb_pclk";
653 };
654
655 gpio15: gpio@e8a1a000 {
656 compatible = "arm,pl061", "arm,primecell";
657 reg = <0 0xe8a1a000 0 0x1000>;
658 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
659 gpio-controller;
660 #gpio-cells = <2>;
661 gpio-ranges = <&pmx0 0 118 6>;
662 interrupt-controller;
663 #interrupt-cells = <2>;
664 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
665 clock-names = "apb_pclk";
666 };
667
668 gpio16: gpio@e8a1b000 {
669 compatible = "arm,pl061", "arm,primecell";
670 reg = <0 0xe8a1b000 0 0x1000>;
671 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
672 gpio-controller;
673 #gpio-cells = <2>;
674 interrupt-controller;
675 #interrupt-cells = <2>;
676 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
677 clock-names = "apb_pclk";
678 };
679
680 gpio17: gpio@e8a1c000 {
681 compatible = "arm,pl061", "arm,primecell";
682 reg = <0 0xe8a1c000 0 0x1000>;
683 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
684 gpio-controller;
685 #gpio-cells = <2>;
686 interrupt-controller;
687 #interrupt-cells = <2>;
688 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
689 clock-names = "apb_pclk";
690 };
691
692 gpio18: gpio@ff3b4000 {
693 compatible = "arm,pl061", "arm,primecell";
694 reg = <0 0xff3b4000 0 0x1000>;
695 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
696 gpio-controller;
697 #gpio-cells = <2>;
698 gpio-ranges = <&pmx2 0 0 8>;
699 interrupt-controller;
700 #interrupt-cells = <2>;
701 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
702 clock-names = "apb_pclk";
703 };
704
705 gpio19: gpio@ff3b5000 {
706 compatible = "arm,pl061", "arm,primecell";
707 reg = <0 0xff3b5000 0 0x1000>;
708 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
709 gpio-controller;
710 #gpio-cells = <2>;
711 gpio-ranges = <&pmx2 0 8 4>;
712 interrupt-controller;
713 #interrupt-cells = <2>;
714 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
715 clock-names = "apb_pclk";
716 };
717
718 gpio20: gpio@e8a1f000 {
719 compatible = "arm,pl061", "arm,primecell";
720 reg = <0 0xe8a1f000 0 0x1000>;
721 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
722 gpio-controller;
723 #gpio-cells = <2>;
724 gpio-ranges = <&pmx1 0 0 6>;
725 interrupt-controller;
726 #interrupt-cells = <2>;
727 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
728 clock-names = "apb_pclk";
729 };
730
731 gpio21: gpio@e8a20000 {
732 compatible = "arm,pl061", "arm,primecell";
733 reg = <0 0xe8a20000 0 0x1000>;
734 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
735 gpio-controller;
736 #gpio-cells = <2>;
737 interrupt-controller;
738 #interrupt-cells = <2>;
739 gpio-ranges = <&pmx3 0 0 6>;
740 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
741 clock-names = "apb_pclk";
742 };
743
744 gpio22: gpio@fff0b000 {
745 compatible = "arm,pl061", "arm,primecell";
746 reg = <0 0xfff0b000 0 0x1000>;
747 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
748 gpio-controller;
749 #gpio-cells = <2>;
750 /* GPIO176 */
751 gpio-ranges = <&pmx4 2 0 6>;
752 interrupt-controller;
753 #interrupt-cells = <2>;
754 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
755 clock-names = "apb_pclk";
756 };
757
758 gpio23: gpio@fff0c000 {
759 compatible = "arm,pl061", "arm,primecell";
760 reg = <0 0xfff0c000 0 0x1000>;
761 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
762 gpio-controller;
763 #gpio-cells = <2>;
764 /* GPIO184 */
765 gpio-ranges = <&pmx4 0 6 7>;
766 interrupt-controller;
767 #interrupt-cells = <2>;
768 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
769 clock-names = "apb_pclk";
770 };
771
772 gpio24: gpio@fff0d000 {
773 compatible = "arm,pl061", "arm,primecell";
774 reg = <0 0xfff0d000 0 0x1000>;
775 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-controller;
777 #gpio-cells = <2>;
778 /* GPIO192 */
779 gpio-ranges = <&pmx4 0 13 8>;
780 interrupt-controller;
781 #interrupt-cells = <2>;
782 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
783 clock-names = "apb_pclk";
784 };
785
786 gpio25: gpio@fff0e000 {
787 compatible = "arm,pl061", "arm,primecell";
788 reg = <0 0xfff0e000 0 0x1000>;
789 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
790 gpio-controller;
791 #gpio-cells = <2>;
792 /* GPIO200 */
793 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
794 interrupt-controller;
795 #interrupt-cells = <2>;
796 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
797 clock-names = "apb_pclk";
798 };
799
800 gpio26: gpio@fff0f000 {
801 compatible = "arm,pl061", "arm,primecell";
802 reg = <0 0xfff0f000 0 0x1000>;
803 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
804 gpio-controller;
805 #gpio-cells = <2>;
806 /* GPIO208 */
807 gpio-ranges = <&pmx4 0 28 8>;
808 interrupt-controller;
809 #interrupt-cells = <2>;
810 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
811 clock-names = "apb_pclk";
812 };
813
814 gpio27: gpio@fff10000 {
815 compatible = "arm,pl061", "arm,primecell";
816 reg = <0 0xfff10000 0 0x1000>;
817 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
818 gpio-controller;
819 #gpio-cells = <2>;
820 /* GPIO216 */
821 gpio-ranges = <&pmx4 0 36 6>;
822 interrupt-controller;
823 #interrupt-cells = <2>;
824 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
825 clock-names = "apb_pclk";
826 };
827
828 gpio28: gpio@fff1d000 {
829 compatible = "arm,pl061", "arm,primecell";
830 reg = <0 0xfff1d000 0 0x1000>;
831 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
832 gpio-controller;
833 #gpio-cells = <2>;
834 interrupt-controller;
835 #interrupt-cells = <2>;
836 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
837 clock-names = "apb_pclk";
838 };
38810497
WX		 839
840 spi2: spi@ffd68000 {
841 compatible = "arm,pl022", "arm,primecell";
842 reg = <0x0 0xffd68000 0x0 0x1000>;
843 #address-cells = <1>;
844 #size-cells = <0>;
845 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
847 clock-names = "apb_pclk";
848 pinctrl-names = "default";
849 pinctrl-0 = <&spi2_pmx_func>;
850 num-cs = <1>;
851 cs-gpios = <&gpio27 2 0>;
852 status = "disabled";
853 };
854
855 spi3: spi@ff3b3000 {
856 compatible = "arm,pl022", "arm,primecell";
857 reg = <0x0 0xff3b3000 0x0 0x1000>;
858 #address-cells = <1>;
859 #size-cells = <0>;
860 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
862 clock-names = "apb_pclk";
863 pinctrl-names = "default";
864 pinctrl-0 = <&spi3_pmx_func>;
865 num-cs = <1>;
866 cs-gpios = <&gpio18 5 0>;
867 status = "disabled";
868 };
96909778
XS		 869
870 pcie@f4000000 {
871 compatible = "hisilicon,kirin960-pcie";
872 reg = <0x0 0xf4000000 0x0 0x1000>,
873 <0x0 0xff3fe000 0x0 0x1000>,
874 <0x0 0xf3f20000 0x0 0x40000>,
875 <0x0 0xf5000000 0x0 0x2000>;
876 reg-names = "dbi", "apb", "phy", "config";
877 bus-range = <0x0 0x1>;
878 #address-cells = <3>;
879 #size-cells = <2>;
880 device_type = "pci";
881 ranges = <0x02000000 0x0 0x00000000
882 0x0 0xf6000000
883 0x0 0x02000000>;
884 num-lanes = <1>;
885 #interrupt-cells = <1>;
886 interrupt-map-mask = <0xf800 0 0 7>;
887 interrupt-map = <0x0 0 0 1
888 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
889 <0x0 0 0 2
890 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
891 <0x0 0 0 3
892 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
893 <0x0 0 0 4
894 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
896 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
897 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
898 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
899 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
900 clock-names = "pcie_phy_ref", "pcie_aux",
901 "pcie_apb_phy", "pcie_apb_sys",
902 "pcie_aclk";
903 reset-gpios = <&gpio11 1 0 >;
904 };
804d7d7a
LW		 905
906 /* SD */
907 dwmmc1: dwmmc1@ff37f000 {
908 #address-cells = <1>;
909 #size-cells = <0>;
910 cd-inverted;
911 compatible = "hisilicon,hi3660-dw-mshc";
912 num-slots = <1>;
913 bus-width = <0x4>;
914 disable-wp;
915 cap-sd-highspeed;
916 supports-highspeed;
917 card-detect-delay = <200>;
918 reg = <0x0 0xff37f000 0x0 0x1000>;
919 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
921 <&crg_ctrl HI3660_HCLK_GATE_SD>;
922 clock-names = "ciu", "biu";
923 clock-frequency = <3200000>;
924 resets = <&crg_rst 0x94 18>;
996707d7 925 reset-names = "reset";
804d7d7a
LW		 926 cd-gpios = <&gpio25 3 0>;
927 hisilicon,peripheral-syscon = <&sctrl>;
928 pinctrl-names = "default";
929 pinctrl-0 = <&sd_pmx_func
930 &sd_clk_cfg_func
931 &sd_cfg_func>;
932 sd-uhs-sdr12;
933 sd-uhs-sdr25;
934 sd-uhs-sdr50;
935 sd-uhs-sdr104;
936 status = "disabled";
937
938 slot@0 {
939 reg = <0x0>;
940 bus-width = <4>;
941 disable-wp;
942 };
943 };
944
945 /* SDIO */
946 dwmmc2: dwmmc2@ff3ff000 {
947 compatible = "hisilicon,hi3660-dw-mshc";
948 reg = <0x0 0xff3ff000 0x0 0x1000>;
949 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
950 num-slots = <1>;
951 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
952 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
953 clock-names = "ciu", "biu";
954 resets = <&crg_rst 0x94 20>;
996707d7 955 reset-names = "reset";
804d7d7a
LW		 956 card-detect-delay = <200>;
957 supports-highspeed;
958 keep-power-in-suspend;
959 pinctrl-names = "default";
960 pinctrl-0 = <&sdio_pmx_func
961 &sdio_clk_cfg_func
962 &sdio_cfg_func>;
963 status = "disabled";
964 };
35ca8168
CF		 965 };
966};
Linux 6.x block layer and io_uring tree(s)