[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / fsl-ls2080a.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
 *
 * Copyright 2014-2016 Freescale Semiconductor, Inc.
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
 *
 */

#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls208xa.dtsi"

/ {
	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};
};

&cpu {
	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x0>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x1>;
		clocks = <&clockgen QORIQ_CLK_CMUX 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x100>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x101>;
		clocks = <&clockgen QORIQ_CLK_CMUX 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu4: cpu@200 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x200>;
		clocks = <&clockgen QORIQ_CLK_CMUX 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
	};

	cpu5: cpu@201 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x201>;
		clocks = <&clockgen QORIQ_CLK_CMUX 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
		#cooling-cells = <2>;
	};

	cpu6: cpu@300 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x300>;
		clocks = <&clockgen QORIQ_CLK_CMUX 3>;
		next-level-cache = <&cluster3_l2>;
		cpu-idle-states = <&CPU_PW20>;
		#cooling-cells = <2>;
	};

	cpu7: cpu@301 {
		device_type = "cpu";
		compatible = "arm,cortex-a57";
		reg = <0x301>;
		clocks = <&clockgen QORIQ_CLK_CMUX 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

	cluster0_l2: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
	};

	cluster1_l2: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
	};

	cluster2_l2: l2-cache2 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
	};

	cluster3_l2: l2-cache3 {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
	};

	CPU_PW20: cpu-pw20 {
		compatible = "arm,idle-state";
		idle-state-name = "PW20";
		arm,psci-suspend-param = <0x00010000>;
		entry-latency-us = <2000>;
		exit-latency-us = <2000>;
		min-residency-us = <6000>;
	};
};

&pcie1 {
	reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
	      <0x10 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&pcie2 {
	reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
	      <0x12 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&pcie3 {
	reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
	      <0x14 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&pcie4 {
	reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
	      <0x16 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
		  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};

&timer {
	fsl,erratum-a008585;
};
Commit	Line	Data
7a2aeb91	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
747c84d0	2	/*
f43a4b85	3	* Device Tree Include file for Freescale Layerscape-2080A family SoC.
747c84d0	4	*
8637f58b	5	* Copyright 2014-2016 Freescale Semiconductor, Inc.
747c84d0	6	*
c2f6a472	7	* Abhimanyu Saini <abhimanyu.saini@nxp.com>
747c84d0 BS	8	* Bhupesh Sharma <bhupesh.sharma@freescale.com>
747c84d0 BS	9	*
747c84d0 BS	10	*/
747c84d0 BS	11
b0ccb208	12	#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
c2f6a472	13	#include "fsl-ls208xa.dtsi"
236f794e	14
8b40a469 RH	15	/ {
	16	pmu {
	17	compatible = "arm,cortex-a57-pmu";
0943d92c	18	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
8b40a469 RH	19	};
	20	};
	21
c2f6a472 AS	22	&cpu {
	23	cpu0: cpu@0 {
	24	device_type = "cpu";
	25	compatible = "arm,cortex-a57";
	26	reg = <0x0>;
b0ccb208	27	clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39a71db1	28	cpu-idle-states = <&CPU_PW20>;
c2f6a472 AS	29	next-level-cache = <&cluster0_l2>;
c2f6a472 AS	30	#cooling-cells = <2>;
747c84d0 BS	31	};
747c84d0 BS	32
c2f6a472 AS	33	cpu1: cpu@1 {
	34	device_type = "cpu";
	35	compatible = "arm,cortex-a57";
	36	reg = <0x1>;
b0ccb208	37	clocks = <&clockgen QORIQ_CLK_CMUX 0>;
39a71db1	38	cpu-idle-states = <&CPU_PW20>;
c2f6a472	39	next-level-cache = <&cluster0_l2>;
346f5976	40	#cooling-cells = <2>;
747c84d0 BS	41	};
747c84d0 BS	42
c2f6a472 AS	43	cpu2: cpu@100 {
	44	device_type = "cpu";
	45	compatible = "arm,cortex-a57";
	46	reg = <0x100>;
b0ccb208	47	clocks = <&clockgen QORIQ_CLK_CMUX 1>;
39a71db1	48	cpu-idle-states = <&CPU_PW20>;
c2f6a472 AS	49	next-level-cache = <&cluster1_l2>;
c2f6a472 AS	50	#cooling-cells = <2>;
5461597f BS	51	};
5461597f BS	52
c2f6a472 AS	53	cpu3: cpu@101 {
	54	device_type = "cpu";
	55	compatible = "arm,cortex-a57";
	56	reg = <0x101>;
b0ccb208	57	clocks = <&clockgen QORIQ_CLK_CMUX 1>;
39a71db1	58	cpu-idle-states = <&CPU_PW20>;
c2f6a472	59	next-level-cache = <&cluster1_l2>;
346f5976	60	#cooling-cells = <2>;
747c84d0 BS	61	};
747c84d0 BS	62
c2f6a472 AS	63	cpu4: cpu@200 {
	64	device_type = "cpu";
	65	compatible = "arm,cortex-a57";
	66	reg = <0x200>;
b0ccb208	67	clocks = <&clockgen QORIQ_CLK_CMUX 2>;
39a71db1	68	cpu-idle-states = <&CPU_PW20>;
c2f6a472 AS	69	next-level-cache = <&cluster2_l2>;
c2f6a472 AS	70	#cooling-cells = <2>;
c7a5675f GR	71	};
c7a5675f GR	72
c2f6a472 AS	73	cpu5: cpu@201 {
	74	device_type = "cpu";
	75	compatible = "arm,cortex-a57";
	76	reg = <0x201>;
b0ccb208	77	clocks = <&clockgen QORIQ_CLK_CMUX 2>;
39a71db1	78	cpu-idle-states = <&CPU_PW20>;
c2f6a472	79	next-level-cache = <&cluster2_l2>;
346f5976	80	#cooling-cells = <2>;
c7a5675f GR	81	};
c7a5675f GR	82
c2f6a472 AS	83	cpu6: cpu@300 {
	84	device_type = "cpu";
	85	compatible = "arm,cortex-a57";
	86	reg = <0x300>;
b0ccb208	87	clocks = <&clockgen QORIQ_CLK_CMUX 3>;
c2f6a472	88	next-level-cache = <&cluster3_l2>;
39a71db1	89	cpu-idle-states = <&CPU_PW20>;
c2f6a472	90	#cooling-cells = <2>;
747c84d0 BS	91	};
747c84d0 BS	92
c2f6a472 AS	93	cpu7: cpu@301 {
	94	device_type = "cpu";
	95	compatible = "arm,cortex-a57";
	96	reg = <0x301>;
b0ccb208	97	clocks = <&clockgen QORIQ_CLK_CMUX 3>;
39a71db1	98	cpu-idle-states = <&CPU_PW20>;
c2f6a472	99	next-level-cache = <&cluster3_l2>;
346f5976	100	#cooling-cells = <2>;
747c84d0 BS	101	};
747c84d0 BS	102
c2f6a472 AS	103	cluster0_l2: l2-cache0 {
c2f6a472 AS	104	compatible = "cache";
3b450831	105	cache-level = <2>;
c290d09a	106	cache-unified;
c2f6a472	107	};
5461597f	108
c2f6a472 AS	109	cluster1_l2: l2-cache1 {
c2f6a472 AS	110	compatible = "cache";
3b450831	111	cache-level = <2>;
c290d09a	112	cache-unified;
c2f6a472	113	};
5461597f	114
c2f6a472 AS	115	cluster2_l2: l2-cache2 {
c2f6a472 AS	116	compatible = "cache";
3b450831	117	cache-level = <2>;
c290d09a	118	cache-unified;
c2f6a472	119	};
5461597f	120
c2f6a472 AS	121	cluster3_l2: l2-cache3 {
c2f6a472 AS	122	compatible = "cache";
3b450831	123	cache-level = <2>;
c290d09a	124	cache-unified;
c2f6a472	125	};
39a71db1 YT	126
	127	CPU_PW20: cpu-pw20 {
	128	compatible = "arm,idle-state";
	129	idle-state-name = "PW20";
	130	arm,psci-suspend-param = <0x00010000>;
	131	entry-latency-us = <2000>;
	132	exit-latency-us = <2000>;
	133	min-residency-us = <6000>;
	134	};
c2f6a472	135	};
5461597f	136
c2f6a472	137	&pcie1 {
ce87d936 ZL	138	reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
ce87d936 ZL	139	<0x10 0x00000000 0x0 0x00002000>; /* configuration space */
5461597f	140
c2f6a472 AS	141	ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
	142	0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	143	};
5461597f	144
c2f6a472	145	&pcie2 {
ce87d936 ZL	146	reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
ce87d936 ZL	147	<0x12 0x00000000 0x0 0x00002000>; /* configuration space */
5461597f	148
c2f6a472 AS	149	ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
	150	0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	151	};
5461597f	152
c2f6a472	153	&pcie3 {
ce87d936 ZL	154	reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
ce87d936 ZL	155	<0x14 0x00000000 0x0 0x00002000>; /* configuration space */
5461597f	156
c2f6a472 AS	157	ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
	158	0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	159	};
30062fb0	160
c2f6a472	161	&pcie4 {
ce87d936 ZL	162	reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
ce87d936 ZL	163	<0x16 0x00000000 0x0 0x00002000>; /* configuration space */
30062fb0	164
c2f6a472 AS	165	ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
c2f6a472 AS	166	0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
747c84d0	167	};
4dede987 PB	168
	169	&timer {
	170	fsl,erratum-a008585;
	171	};