[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / fsl-ls2080a.dtsi

/*
 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
 *
 * Copyright (C) 2014-2015, Freescale Semiconductor
 *
 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	compatible = "fsl,ls2080a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/*
		 * We expect the enable-method for cpu's to be "psci", but this
		 * is dependent on the SoC FW, which will fill this in.
		 *
		 * Currently supported enable-method is psci v0.2
		 */

		/* We have 4 clusters having 2 Cortex-A57 cores each */
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x0>;
			clocks = <&clockgen 1 0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x1>;
			clocks = <&clockgen 1 0>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x100>;
			clocks = <&clockgen 1 1>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x101>;
			clocks = <&clockgen 1 1>;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x200>;
			clocks = <&clockgen 1 2>;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x201>;
			clocks = <&clockgen 1 2>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x300>;
			clocks = <&clockgen 1 3>;
		};

		cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x301>;
			clocks = <&clockgen 1 3>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x80000000>;
		      /* DRAM space - 1, size : 2 GB DRAM */
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	gic: interrupt-controller@6000000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;
		interrupts = <1 9 0x4>;

		its: gic-its@6020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x6020000 0 0x20000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
			     <1 11 0x8>, /* Virtual PPI, active-low */
			     <1 10 0x8>; /* Hypervisor PPI, active-low */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clockgen: clocking@1300000 {
			compatible = "fsl,ls2080a-clockgen";
			reg = <0 0x1300000 0 0xa0000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		serial0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21c0500 0x0 0x100>;
			clocks = <&clockgen 4 3>;
			interrupts = <0 32 0x4>; /* Level high type */
		};

		serial1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21c0600 0x0 0x100>;
			clocks = <&clockgen 4 3>;
			interrupts = <0 32 0x4>; /* Level high type */
		};

		fsl_mc: fsl-mc@80c000000 {
			compatible = "fsl,qoriq-mc";
			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
		};

		smmu: iommu@5000000 {
			compatible = "arm,mmu-500";
			reg = <0 0x5000000 0 0x800000>;
			#global-interrupts = <12>;
			interrupts = <0 13 4>, /* global secure fault */
				     <0 14 4>, /* combined secure interrupt */
				     <0 15 4>, /* global non-secure fault */
				     <0 16 4>, /* combined non-secure interrupt */
				/* performance counter interrupts 0-7 */
				     <0 211 4>, <0 212 4>,
				     <0 213 4>, <0 214 4>,
				     <0 215 4>, <0 216 4>,
				     <0 217 4>, <0 218 4>,
				/* per context interrupt, 64 interrupts */
				     <0 146 4>, <0 147 4>,
				     <0 148 4>, <0 149 4>,
				     <0 150 4>, <0 151 4>,
				     <0 152 4>, <0 153 4>,
				     <0 154 4>, <0 155 4>,
				     <0 156 4>, <0 157 4>,
				     <0 158 4>, <0 159 4>,
				     <0 160 4>, <0 161 4>,
				     <0 162 4>, <0 163 4>,
				     <0 164 4>, <0 165 4>,
				     <0 166 4>, <0 167 4>,
				     <0 168 4>, <0 169 4>,
				     <0 170 4>, <0 171 4>,
				     <0 172 4>, <0 173 4>,
				     <0 174 4>, <0 175 4>,
				     <0 176 4>, <0 177 4>,
				     <0 178 4>, <0 179 4>,
				     <0 180 4>, <0 181 4>,
				     <0 182 4>, <0 183 4>,
				     <0 184 4>, <0 185 4>,
				     <0 186 4>, <0 187 4>,
				     <0 188 4>, <0 189 4>,
				     <0 190 4>, <0 191 4>,
				     <0 192 4>, <0 193 4>,
				     <0 194 4>, <0 195 4>,
				     <0 196 4>, <0 197 4>,
				     <0 198 4>, <0 199 4>,
				     <0 200 4>, <0 201 4>,
				     <0 202 4>, <0 203 4>,
				     <0 204 4>, <0 205 4>,
				     <0 206 4>, <0 207 4>,
				     <0 208 4>, <0 209 4>;
			mmu-masters = <&fsl_mc 0x300 0>;
		};

		dspi: dspi@2100000 {
			status = "disabled";
			compatible = "fsl,vf610-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 26 0x4>; /* Level high type */
			clocks = <&clockgen 4 3>;
			clock-names = "dspi";
			spi-num-chipselects = <5>;
			bus-num = <0>;
		};

		esdhc: esdhc@2140000 {
			status = "disabled";
			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
			reg = <0x0 0x2140000 0x0 0x10000>;
			interrupts = <0 28 0x4>; /* Level high type */
			clock-frequency = <0>;	/* Updated by bootloader */
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			little-endian;
			bus-width = <4>;
		};

		gpio0: gpio@2300000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 36 0x4>; /* Level high type */
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@2310000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 36 0x4>; /* Level high type */
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2320000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 37 0x4>; /* Level high type */
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2330000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 37 0x4>; /* Level high type */
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		i2c0: i2c@2000000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts = <0 34 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen 4 3>;
		};

		i2c1: i2c@2010000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2010000 0x0 0x10000>;
			interrupts = <0 34 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen 4 3>;
		};

		i2c2: i2c@2020000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2020000 0x0 0x10000>;
			interrupts = <0 35 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen 4 3>;
		};

		i2c3: i2c@2030000 {
			status = "disabled";
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2030000 0x0 0x10000>;
			interrupts = <0 35 0x4>; /* Level high type */
			clock-names = "i2c";
			clocks = <&clockgen 4 3>;
		};

		ifc: ifc@2240000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x2240000 0x0 0x20000>;
			interrupts = <0 21 0x4>; /* Level high type */
			little-endian;
			#address-cells = <2>;
			#size-cells = <1>;

			ranges = <0 0 0x5 0x80000000 0x08000000
				  2 0 0x5 0x30000000 0x00010000
				  3 0 0x5 0x20000000 0x00010000>;
		};

		qspi: quadspi@20c0000 {
			status = "disabled";
			compatible = "fsl,vf610-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x20c0000 0x0 0x10000>,
			      <0x0 0x20000000 0x0 0x10000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <0 25 0x4>; /* Level high type */
			clocks = <&clockgen 4 3>, <&clockgen 4 3>;
			clock-names = "qspi_en", "qspi";
		};

		pcie@3400000 {
			compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
			       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 108 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <4>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
					<0000 0 0 2 &gic 0 0 0 110 4>,
					<0000 0 0 3 &gic 0 0 0 111 4>,
					<0000 0 0 4 &gic 0 0 0 112 4>;
		};

		pcie@3500000 {
			compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
			       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 113 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <4>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
					<0000 0 0 2 &gic 0 0 0 115 4>,
					<0000 0 0 3 &gic 0 0 0 116 4>,
					<0000 0 0 4 &gic 0 0 0 117 4>;
		};

		pcie@3600000 {
			compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
			       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 118 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <8>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
					<0000 0 0 2 &gic 0 0 0 120 4>,
					<0000 0 0 3 &gic 0 0 0 121 4>,
					<0000 0 0 4 &gic 0 0 0 122 4>;
		};

		pcie@3700000 {
			compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
			       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 123 0x4>; /* Level high type */
			interrupt-names = "intr";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <4>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&its>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
					<0000 0 0 2 &gic 0 0 0 125 4>,
					<0000 0 0 3 &gic 0 0 0 126 4>,
					<0000 0 0 4 &gic 0 0 0 127 4>;
		};

		sata0: sata@3200000 {
			status = "disabled";
			compatible = "fsl,ls2080a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>;
			interrupts = <0 133 0x4>; /* Level high type */
			clocks = <&clockgen 4 3>;
		};

		sata1: sata@3210000 {
			status = "disabled";
			compatible = "fsl,ls2080a-ahci";
			reg = <0x0 0x3210000 0x0 0x10000>;
			interrupts = <0 136 0x4>; /* Level high type */
			clocks = <&clockgen 4 3>;
		};

		usb0: usb3@3100000 {
			status = "disabled";
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 80 0x4>; /* Level high type */
			dr_mode = "host";
		};

		usb1: usb3@3110000 {
			status = "disabled";
			compatible = "snps,dwc3";
			reg = <0x0 0x3110000 0x0 0x10000>;
			interrupts = <0 81 0x4>; /* Level high type */
			dr_mode = "host";
		};

		ccn@4000000 {
			compatible = "arm,ccn-504";
			reg = <0x0 0x04000000 0x0 0x01000000>;
			interrupts = <0 12 4>;
		};
	};
};
Commit	Line	Data
747c84d0	1	/*
f43a4b85	2	* Device Tree Include file for Freescale Layerscape-2080A family SoC.
747c84d0	3	*
f43a4b85	4	* Copyright (C) 2014-2015, Freescale Semiconductor
747c84d0 BS	5	*
	6	* Bhupesh Sharma <bhupesh.sharma@freescale.com>
	7	*
	8	* This file is dual-licensed: you can use it either under the terms
	9	* of the GPLv2 or the X11 license, at your option. Note that this dual
	10	* licensing only applies to this file, and not this project as a
	11	* whole.
	12	*
	13	* a) This library is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of the
	16	* License, or (at your option) any later version.
	17	*
	18	* This library is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
747c84d0 BS	23	* Or, alternatively,
	24	*
	25	* b) Permission is hereby granted, free of charge, to any person
	26	* obtaining a copy of this software and associated documentation
	27	* files (the "Software"), to deal in the Software without
	28	* restriction, including without limitation the rights to use,
	29	* copy, modify, merge, publish, distribute, sublicense, and/or
	30	* sell copies of the Software, and to permit persons to whom the
	31	* Software is furnished to do so, subject to the following
	32	* conditions:
	33	*
	34	* The above copyright notice and this permission notice shall be
	35	* included in all copies or substantial portions of the Software.
	36	*
	37	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	38	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	39	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	40	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	41	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	42	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	43	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	44	* OTHER DEALINGS IN THE SOFTWARE.
	45	*/
	46
	47	/ {
f43a4b85	48	compatible = "fsl,ls2080a";
747c84d0 BS	49	interrupt-parent = <&gic>;
	50	#address-cells = <2>;
	51	#size-cells = <2>;
	52
	53	cpus {
	54	#address-cells = <2>;
	55	#size-cells = <0>;
	56
	57	/*
	58	* We expect the enable-method for cpu's to be "psci", but this
	59	* is dependent on the SoC FW, which will fill this in.
	60	*
	61	* Currently supported enable-method is psci v0.2
	62	*/
	63
	64	/* We have 4 clusters having 2 Cortex-A57 cores each */
	65	cpu@0 {
	66	device_type = "cpu";
	67	compatible = "arm,cortex-a57";
	68	reg = <0x0 0x0>;
5461597f	69	clocks = <&clockgen 1 0>;
747c84d0 BS	70	};
	71
	72	cpu@1 {
	73	device_type = "cpu";
	74	compatible = "arm,cortex-a57";
	75	reg = <0x0 0x1>;
5461597f	76	clocks = <&clockgen 1 0>;
747c84d0 BS	77	};
	78
	79	cpu@100 {
	80	device_type = "cpu";
	81	compatible = "arm,cortex-a57";
	82	reg = <0x0 0x100>;
5461597f	83	clocks = <&clockgen 1 1>;
747c84d0 BS	84	};
	85
	86	cpu@101 {
	87	device_type = "cpu";
	88	compatible = "arm,cortex-a57";
	89	reg = <0x0 0x101>;
5461597f	90	clocks = <&clockgen 1 1>;
747c84d0 BS	91	};
	92
	93	cpu@200 {
	94	device_type = "cpu";
	95	compatible = "arm,cortex-a57";
	96	reg = <0x0 0x200>;
5461597f	97	clocks = <&clockgen 1 2>;
747c84d0 BS	98	};
	99
	100	cpu@201 {
	101	device_type = "cpu";
	102	compatible = "arm,cortex-a57";
	103	reg = <0x0 0x201>;
5461597f	104	clocks = <&clockgen 1 2>;
747c84d0 BS	105	};
	106
	107	cpu@300 {
	108	device_type = "cpu";
	109	compatible = "arm,cortex-a57";
	110	reg = <0x0 0x300>;
5461597f	111	clocks = <&clockgen 1 3>;
747c84d0 BS	112	};
	113
	114	cpu@301 {
	115	device_type = "cpu";
	116	compatible = "arm,cortex-a57";
	117	reg = <0x0 0x301>;
5461597f	118	clocks = <&clockgen 1 3>;
747c84d0 BS	119	};
	120	};
	121
	122	memory@80000000 {
	123	device_type = "memory";
	124	reg = <0x00000000 0x80000000 0 0x80000000>;
	125	/* DRAM space - 1, size : 2 GB DRAM */
	126	};
	127
5461597f BS	128	sysclk: sysclk {
	129	compatible = "fixed-clock";
	130	#clock-cells = <0>;
	131	clock-frequency = <100000000>;
	132	clock-output-names = "sysclk";
	133	};
	134
747c84d0 BS	135	gic: interrupt-controller@6000000 {
	136	compatible = "arm,gic-v3";
	137	reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5461597f BS	138	<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
	139	<0x0 0x0c0c0000 0 0x2000>, /* GICC */
	140	<0x0 0x0c0d0000 0 0x1000>, /* GICH */
	141	<0x0 0x0c0e0000 0 0x20000>; /* GICV */
747c84d0	142	#interrupt-cells = <3>;
5461597f BS	143	#address-cells = <2>;
	144	#size-cells = <2>;
	145	ranges;
747c84d0 BS	146	interrupt-controller;
747c84d0 BS	147	interrupts = <1 9 0x4>;
5461597f BS	148
	149	its: gic-its@6020000 {
	150	compatible = "arm,gic-v3-its";
	151	msi-controller;
	152	reg = <0x0 0x6020000 0 0x20000>;
	153	};
747c84d0 BS	154	};
	155
	156	timer {
	157	compatible = "arm,armv8-timer";
	158	interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
	159	<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
	160	<1 11 0x8>, /* Virtual PPI, active-low */
	161	<1 10 0x8>; /* Hypervisor PPI, active-low */
	162	};
	163
5461597f BS	164	pmu {
	165	compatible = "arm,armv8-pmuv3";
	166	interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
747c84d0 BS	167	};
747c84d0 BS	168
5461597f BS	169	soc {
	170	compatible = "simple-bus";
	171	#address-cells = <2>;
	172	#size-cells = <2>;
	173	ranges;
	174
	175	clockgen: clocking@1300000 {
	176	compatible = "fsl,ls2080a-clockgen";
	177	reg = <0 0x1300000 0 0xa0000>;
	178	#clock-cells = <2>;
	179	clocks = <&sysclk>;
	180	};
	181
	182	serial0: serial@21c0500 {
	183	compatible = "fsl,ns16550", "ns16550a";
	184	reg = <0x0 0x21c0500 0x0 0x100>;
	185	clocks = <&clockgen 4 3>;
	186	interrupts = <0 32 0x4>; /* Level high type */
	187	};
	188
	189	serial1: serial@21c0600 {
	190	compatible = "fsl,ns16550", "ns16550a";
	191	reg = <0x0 0x21c0600 0x0 0x100>;
	192	clocks = <&clockgen 4 3>;
	193	interrupts = <0 32 0x4>; /* Level high type */
	194	};
	195
	196	fsl_mc: fsl-mc@80c000000 {
	197	compatible = "fsl,qoriq-mc";
	198	reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
	199	<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
	200	};
747c84d0	201
5461597f BS	202	smmu: iommu@5000000 {
	203	compatible = "arm,mmu-500";
	204	reg = <0 0x5000000 0 0x800000>;
	205	#global-interrupts = <12>;
	206	interrupts = <0 13 4>, /* global secure fault */
	207	<0 14 4>, /* combined secure interrupt */
	208	<0 15 4>, /* global non-secure fault */
	209	<0 16 4>, /* combined non-secure interrupt */
	210	/* performance counter interrupts 0-7 */
	211	<0 211 4>, <0 212 4>,
	212	<0 213 4>, <0 214 4>,
	213	<0 215 4>, <0 216 4>,
	214	<0 217 4>, <0 218 4>,
	215	/* per context interrupt, 64 interrupts */
	216	<0 146 4>, <0 147 4>,
	217	<0 148 4>, <0 149 4>,
	218	<0 150 4>, <0 151 4>,
	219	<0 152 4>, <0 153 4>,
	220	<0 154 4>, <0 155 4>,
	221	<0 156 4>, <0 157 4>,
	222	<0 158 4>, <0 159 4>,
	223	<0 160 4>, <0 161 4>,
	224	<0 162 4>, <0 163 4>,
	225	<0 164 4>, <0 165 4>,
	226	<0 166 4>, <0 167 4>,
	227	<0 168 4>, <0 169 4>,
	228	<0 170 4>, <0 171 4>,
	229	<0 172 4>, <0 173 4>,
	230	<0 174 4>, <0 175 4>,
	231	<0 176 4>, <0 177 4>,
	232	<0 178 4>, <0 179 4>,
	233	<0 180 4>, <0 181 4>,
	234	<0 182 4>, <0 183 4>,
	235	<0 184 4>, <0 185 4>,
	236	<0 186 4>, <0 187 4>,
	237	<0 188 4>, <0 189 4>,
	238	<0 190 4>, <0 191 4>,
	239	<0 192 4>, <0 193 4>,
	240	<0 194 4>, <0 195 4>,
	241	<0 196 4>, <0 197 4>,
	242	<0 198 4>, <0 199 4>,
	243	<0 200 4>, <0 201 4>,
	244	<0 202 4>, <0 203 4>,
	245	<0 204 4>, <0 205 4>,
	246	<0 206 4>, <0 207 4>,
	247	<0 208 4>, <0 209 4>;
	248	mmu-masters = <&fsl_mc 0x300 0>;
	249	};
	250
	251	dspi: dspi@2100000 {
	252	status = "disabled";
	253	compatible = "fsl,vf610-dspi";
	254	#address-cells = <1>;
	255	#size-cells = <0>;
	256	reg = <0x0 0x2100000 0x0 0x10000>;
	257	interrupts = <0 26 0x4>; /* Level high type */
	258	clocks = <&clockgen 4 3>;
	259	clock-names = "dspi";
	260	spi-num-chipselects = <5>;
	261	bus-num = <0>;
	262	};
	263
	264	esdhc: esdhc@2140000 {
	265	status = "disabled";
266	compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
267	reg = <0x0 0x2140000 0x0 0x10000>;
268	interrupts = <0 28 0x4>; /* Level high type */
269	clock-frequency = <0>; /* Updated by bootloader */
270	voltage-ranges = <1800 1800 3300 3300>;
271	sdhci,auto-cmd12;
2dd2e4d1	272	little-endian;
5461597f BS	273	bus-width = <4>;
	274	};
	275
	276	gpio0: gpio@2300000 {
	277	compatible = "fsl,qoriq-gpio";
	278	reg = <0x0 0x2300000 0x0 0x10000>;
	279	interrupts = <0 36 0x4>; /* Level high type */
	280	gpio-controller;
	281	#gpio-cells = <2>;
	282	interrupt-controller;
	283	#interrupt-cells = <2>;
	284	};
	285
	286	gpio1: gpio@2310000 {
	287	compatible = "fsl,qoriq-gpio";
	288	reg = <0x0 0x2310000 0x0 0x10000>;
	289	interrupts = <0 36 0x4>; /* Level high type */
	290	gpio-controller;
	291	#gpio-cells = <2>;
	292	interrupt-controller;
	293	#interrupt-cells = <2>;
	294	};
	295
	296	gpio2: gpio@2320000 {
	297	compatible = "fsl,qoriq-gpio";
	298	reg = <0x0 0x2320000 0x0 0x10000>;
	299	interrupts = <0 37 0x4>; /* Level high type */
	300	gpio-controller;
	301	#gpio-cells = <2>;
	302	interrupt-controller;
	303	#interrupt-cells = <2>;
	304	};
	305
	306	gpio3: gpio@2330000 {
	307	compatible = "fsl,qoriq-gpio";
	308	reg = <0x0 0x2330000 0x0 0x10000>;
	309	interrupts = <0 37 0x4>; /* Level high type */
	310	gpio-controller;
	311	#gpio-cells = <2>;
	312	interrupt-controller;
	313	#interrupt-cells = <2>;
	314	};
	315
	316	i2c0: i2c@2000000 {
	317	status = "disabled";
	318	compatible = "fsl,vf610-i2c";
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321	reg = <0x0 0x2000000 0x0 0x10000>;
	322	interrupts = <0 34 0x4>; /* Level high type */
	323	clock-names = "i2c";
	324	clocks = <&clockgen 4 3>;
	325	};
	326
	327	i2c1: i2c@2010000 {
	328	status = "disabled";
	329	compatible = "fsl,vf610-i2c";
	330	#address-cells = <1>;
	331	#size-cells = <0>;
	332	reg = <0x0 0x2010000 0x0 0x10000>;
	333	interrupts = <0 34 0x4>; /* Level high type */
	334	clock-names = "i2c";
	335	clocks = <&clockgen 4 3>;
	336	};
337
338	i2c2: i2c@2020000 {
339	status = "disabled";
340	compatible = "fsl,vf610-i2c";
341	#address-cells = <1>;
342	#size-cells = <0>;
343	reg = <0x0 0x2020000 0x0 0x10000>;
344	interrupts = <0 35 0x4>; /* Level high type */
345	clock-names = "i2c";
346	clocks = <&clockgen 4 3>;
347	};
348
349	i2c3: i2c@2030000 {
350	status = "disabled";
351	compatible = "fsl,vf610-i2c";
352	#address-cells = <1>;
353	#size-cells = <0>;
354	reg = <0x0 0x2030000 0x0 0x10000>;
355	interrupts = <0 35 0x4>; /* Level high type */
356	clock-names = "i2c";
357	clocks = <&clockgen 4 3>;
358	};
359
360	ifc: ifc@2240000 {
361	compatible = "fsl,ifc", "simple-bus";
362	reg = <0x0 0x2240000 0x0 0x20000>;
363	interrupts = <0 21 0x4>; /* Level high type */
364	little-endian;
365	#address-cells = <2>;
366	#size-cells = <1>;
367
368	ranges = <0 0 0x5 0x80000000 0x08000000
369	2 0 0x5 0x30000000 0x00010000
370	3 0 0x5 0x20000000 0x00010000>;
371	};
372
373	qspi: quadspi@20c0000 {
374	status = "disabled";
375	compatible = "fsl,vf610-qspi";
376	#address-cells = <1>;
377	#size-cells = <0>;
378	reg = <0x0 0x20c0000 0x0 0x10000>,
379	<0x0 0x20000000 0x0 0x10000000>;
380	reg-names = "QuadSPI", "QuadSPI-memory";
381	interrupts = <0 25 0x4>; /* Level high type */
382	clocks = <&clockgen 4 3>, <&clockgen 4 3>;
383	clock-names = "qspi_en", "qspi";
384	};
385
386	pcie@3400000 {
387	compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
388	reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
389	0x10 0x00000000 0x0 0x00002000>; /* configuration space */
390	reg-names = "regs", "config";
391	interrupts = <0 108 0x4>; /* Level high type */
392	interrupt-names = "intr";
393	#address-cells = <3>;
394	#size-cells = <2>;
395	device_type = "pci";
396	num-lanes = <4>;
397	bus-range = <0x0 0xff>;
398	ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
399	0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
400	msi-parent = <&its>;
401	#interrupt-cells = <1>;
402	interrupt-map-mask = <0 0 0 7>;
403	interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
404	<0000 0 0 2 &gic 0 0 0 110 4>,
405	<0000 0 0 3 &gic 0 0 0 111 4>,
406	<0000 0 0 4 &gic 0 0 0 112 4>;
407	};
408
409	pcie@3500000 {
410	compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
411	reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
412	0x12 0x00000000 0x0 0x00002000>; /* configuration space */
413	reg-names = "regs", "config";
414	interrupts = <0 113 0x4>; /* Level high type */
415	interrupt-names = "intr";
416	#address-cells = <3>;
417	#size-cells = <2>;
418	device_type = "pci";
419	num-lanes = <4>;
420	bus-range = <0x0 0xff>;
421	ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
422	0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
423	msi-parent = <&its>;
424	#interrupt-cells = <1>;
425	interrupt-map-mask = <0 0 0 7>;
426	interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
427	<0000 0 0 2 &gic 0 0 0 115 4>,
428	<0000 0 0 3 &gic 0 0 0 116 4>,
429	<0000 0 0 4 &gic 0 0 0 117 4>;
430	};
431
432	pcie@3600000 {
433	compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
434	reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
435	0x14 0x00000000 0x0 0x00002000>; /* configuration space */
436	reg-names = "regs", "config";
437	interrupts = <0 118 0x4>; /* Level high type */
438	interrupt-names = "intr";
439	#address-cells = <3>;
440	#size-cells = <2>;
441	device_type = "pci";
442	num-lanes = <8>;
443	bus-range = <0x0 0xff>;
444	ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
445	0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
446	msi-parent = <&its>;
447	#interrupt-cells = <1>;
448	interrupt-map-mask = <0 0 0 7>;
449	interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
450	<0000 0 0 2 &gic 0 0 0 120 4>,
451	<0000 0 0 3 &gic 0 0 0 121 4>,
452	<0000 0 0 4 &gic 0 0 0 122 4>;
453	};
454
455	pcie@3700000 {
456	compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
457	reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
458	0x16 0x00000000 0x0 0x00002000>; /* configuration space */
459	reg-names = "regs", "config";
460	interrupts = <0 123 0x4>; /* Level high type */
461	interrupt-names = "intr";
462	#address-cells = <3>;
463	#size-cells = <2>;
464	device_type = "pci";
465	num-lanes = <4>;
466	bus-range = <0x0 0xff>;
467	ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
468	0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
469	msi-parent = <&its>;
470	#interrupt-cells = <1>;
471	interrupt-map-mask = <0 0 0 7>;
472	interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
473	<0000 0 0 2 &gic 0 0 0 125 4>,
474	<0000 0 0 3 &gic 0 0 0 126 4>,
475	<0000 0 0 4 &gic 0 0 0 127 4>;
476	};
477
478	sata0: sata@3200000 {
479	status = "disabled";
480	compatible = "fsl,ls2080a-ahci";
481	reg = <0x0 0x3200000 0x0 0x10000>;
482	interrupts = <0 133 0x4>; /* Level high type */
483	clocks = <&clockgen 4 3>;
484	};
485
486	sata1: sata@3210000 {
487	status = "disabled";
488	compatible = "fsl,ls2080a-ahci";
489	reg = <0x0 0x3210000 0x0 0x10000>;
490	interrupts = <0 136 0x4>; /* Level high type */
491	clocks = <&clockgen 4 3>;
492	};
493
494	usb0: usb3@3100000 {
495	status = "disabled";
496	compatible = "snps,dwc3";
497	reg = <0x0 0x3100000 0x0 0x10000>;
498	interrupts = <0 80 0x4>; /* Level high type */
499	dr_mode = "host";
500	};
501
502	usb1: usb3@3110000 {
503	status = "disabled";
504	compatible = "snps,dwc3";
505	reg = <0x0 0x3110000 0x0 0x10000>;
506	interrupts = <0 81 0x4>; /* Level high type */
507	dr_mode = "host";
508	};
509
510	ccn@4000000 {
511	compatible = "arm,ccn-504";
512	reg = <0x0 0x04000000 0x0 0x01000000>;
513	interrupts = <0 12 4>;
514	};
747c84d0 BS	515	};
747c84d0 BS	516	};