[linux-2.6-block.git] / arch / arm64 / boot / dts / freescale / fsl-ls1043a.dtsi

/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright 2014-2015, Freescale Semiconductor
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	compatible = "fsl,ls1043a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		/*
		 * We expect the enable-method for cpu's to be "psci", but this
		 * is dependent on the SoC FW, which will fill this in.
		 *
		 * Currently supported enable-method is psci v0.2
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			clocks = <&clockgen 1 0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			clocks = <&clockgen 1 0>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			clocks = <&clockgen 1 0>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			clocks = <&clockgen 1 0>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0 0x80000000>;
		      /* DRAM space 1, size: 2GiB DRAM */
	};

	sysclk: sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible ="syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0x1>, /* Physical Secure PPI */
			     <1 14 0x1>, /* Physical Non-Secure PPI */
			     <1 11 0x1>, /* Virtual PPI */
			     <1 10 0x1>; /* Hypervisor PPI */
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 106 0x4>,
			     <0 107 0x4>,
			     <0 95 0x4>,
			     <0 97 0x4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	gic: interrupt-controller@1400000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
		      <0x0 0x1402000 0 0x2000>, /* GICC */
		      <0x0 0x1404000 0 0x2000>, /* GICH */
		      <0x0 0x1406000 0 0x2000>; /* GICV */
		interrupts = <1 9 0xf08>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clockgen: clocking@1ee1000 {
			compatible = "fsl,ls1043a-clockgen";
			reg = <0x0 0x1ee1000 0x0 0x1000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		scfg: scfg@1570000 {
			compatible = "fsl,ls1043a-scfg", "syscon";
			reg = <0x0 0x1570000 0x0 0x10000>;
			big-endian;
		};

		crypto: crypto@1700000 {
			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
				     "fsl,sec-v4.0";
			fsl,sec-era = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x00 0x1700000 0x100000>;
			reg = <0x00 0x1700000 0x0 0x100000>;
			interrupts = <0 75 0x4>;

			sec_jr0: jr@10000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x10000 0x10000>;
				interrupts = <0 71 0x4>;
			};

			sec_jr1: jr@20000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x20000 0x10000>;
				interrupts = <0 72 0x4>;
			};

			sec_jr2: jr@30000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x30000 0x10000>;
				interrupts = <0 73 0x4>;
			};

			sec_jr3: jr@40000 {
				compatible = "fsl,sec-v5.4-job-ring",
					     "fsl,sec-v5.0-job-ring",
					     "fsl,sec-v4.0-job-ring";
				reg	   = <0x40000 0x10000>;
				interrupts = <0 74 0x4>;
			};
		};

		dcfg: dcfg@1ee0000 {
			compatible = "fsl,ls1043a-dcfg", "syscon";
			reg = <0x0 0x1ee0000 0x0 0x10000>;
			big-endian;
		};

		ifc: ifc@1530000 {
			compatible = "fsl,ifc", "simple-bus";
			reg = <0x0 0x1530000 0x0 0x10000>;
			interrupts = <0 43 0x4>;
		};

		qspi: quadspi@1550000 {
			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x1550000 0x0 0x10000>,
				<0x0 0x40000000 0x0 0x4000000>;
			reg-names = "QuadSPI", "QuadSPI-memory";
			interrupts = <0 99 0x4>;
			clock-names = "qspi_en", "qspi";
			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
			big-endian;
			status = "disabled";
		};

		esdhc: esdhc@1560000 {
			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
			reg = <0x0 0x1560000 0x0 0x10000>;
			interrupts = <0 62 0x4>;
			clock-frequency = <0>;
			voltage-ranges = <1800 1800 3300 3300>;
			sdhci,auto-cmd12;
			big-endian;
			bus-width = <4>;
		};

		dspi0: dspi@2100000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2100000 0x0 0x10000>;
			interrupts = <0 64 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		dspi1: dspi@2110000 {
			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2110000 0x0 0x10000>;
			interrupts = <0 65 0x4>;
			clock-names = "dspi";
			clocks = <&clockgen 4 0>;
			spi-num-chipselects = <5>;
			big-endian;
			status = "disabled";
		};

		i2c0: i2c@2180000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2180000 0x0 0x10000>;
			interrupts = <0 56 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			dmas = <&edma0 1 39>,
			       <&edma0 1 38>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		i2c1: i2c@2190000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2190000 0x0 0x10000>;
			interrupts = <0 57 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c2: i2c@21a0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21a0000 0x0 0x10000>;
			interrupts = <0 58 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		i2c3: i2c@21b0000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x21b0000 0x0 0x10000>;
			interrupts = <0 59 0x4>;
			clock-names = "i2c";
			clocks = <&clockgen 4 0>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <0 54 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart2: serial@21d0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0500 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		duart3: serial@21d0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x0 0x21d0600 0x0 0x100>;
			interrupts = <0 55 0x4>;
			clocks = <&clockgen 4 0>;
		};

		gpio1: gpio@2300000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <0 66 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <0 67 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <0 68 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@2330000 {
			compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
			reg = <0x0 0x2330000 0x0 0x10000>;
			interrupts = <0 134 0x4>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		lpuart0: serial@2950000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2950000 0x0 0x1000>;
			interrupts = <0 48 0x4>;
			clocks = <&clockgen 0 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart1: serial@2960000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2960000 0x0 0x1000>;
			interrupts = <0 49 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart2: serial@2970000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2970000 0x0 0x1000>;
			interrupts = <0 50 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart3: serial@2980000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2980000 0x0 0x1000>;
			interrupts = <0 51 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart4: serial@2990000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x2990000 0x0 0x1000>;
			interrupts = <0 52 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		lpuart5: serial@29a0000 {
			compatible = "fsl,ls1021a-lpuart";
			reg = <0x0 0x29a0000 0x0 0x1000>;
			interrupts = <0 53 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "ipg";
			status = "disabled";
		};

		wdog0: wdog@2ad0000 {
			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
			reg = <0x0 0x2ad0000 0x0 0x10000>;
			interrupts = <0 83 0x4>;
			clocks = <&clockgen 4 0>;
			clock-names = "wdog";
			big-endian;
		};

		edma0: edma@2c00000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x2c00000 0x0 0x10000>,
			      <0x0 0x2c10000 0x0 0x10000>,
			      <0x0 0x2c20000 0x0 0x10000>;
			interrupts = <0 103 0x4>,
				     <0 103 0x4>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			big-endian;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen 4 0>,
				 <&clockgen 4 0>;
		};

		usb0: usb3@2f00000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x2f00000 0x0 0x10000>;
			interrupts = <0 60 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
		};

		usb1: usb3@3000000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3000000 0x0 0x10000>;
			interrupts = <0 61 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
		};

		usb2: usb3@3100000 {
			compatible = "snps,dwc3";
			reg = <0x0 0x3100000 0x0 0x10000>;
			interrupts = <0 63 0x4>;
			dr_mode = "host";
			snps,quirk-frame-length-adjustment = <0x20>;
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>;
			interrupts = <0 69 0x4>;
			clocks = <&clockgen 4 0>;
		};

		msi1: msi-controller1@1571000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1571000 0x0 0x8>;
			msi-controller;
			interrupts = <0 116 0x4>;
		};

		msi2: msi-controller2@1572000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1572000 0x0 0x8>;
			msi-controller;
			interrupts = <0 126 0x4>;
		};

		msi3: msi-controller3@1573000 {
			compatible = "fsl,1s1043a-msi";
			reg = <0x0 0x1573000 0x0 0x8>;
			msi-controller;
			interrupts = <0 160 0x4>;
		};

		pcie@3400000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 118 0x4>, /* controller interrupt */
				     <0 117 0x4>; /* PME interrupt */
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <4>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi1>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
					<0000 0 0 2 &gic 0 111 0x4>,
					<0000 0 0 3 &gic 0 112 0x4>,
					<0000 0 0 4 &gic 0 113 0x4>;
		};

		pcie@3500000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 128 0x4>,
				     <0 127 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi2>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
					<0000 0 0 2 &gic 0 121 0x4>,
					<0000 0 0 3 &gic 0 122 0x4>,
					<0000 0 0 4 &gic 0 123 0x4>;
		};

		pcie@3600000 {
			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
			reg-names = "regs", "config";
			interrupts = <0 162 0x4>,
				     <0 161 0x4>;
			interrupt-names = "intr", "pme";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			num-lanes = <2>;
			bus-range = <0x0 0xff>;
			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
			msi-parent = <&msi3>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
					<0000 0 0 2 &gic 0 155 0x4>,
					<0000 0 0 3 &gic 0 156 0x4>,
					<0000 0 0 4 &gic 0 157 0x4>;
		};
	};

};
Commit	Line	Data
6d453cd2 MH	1	/*
	2	* Device Tree Include file for Freescale Layerscape-1043A family SoC.
	3	*
	4	* Copyright 2014-2015, Freescale Semiconductor
	5	*
	6	* Mingkai Hu <Mingkai.hu@freescale.com>
	7	*
	8	* This file is dual-licensed: you can use it either under the terms
	9	* of the GPLv2 or the X11 license, at your option. Note that this dual
	10	* licensing only applies to this file, and not this project as a
	11	* whole.
	12	*
	13	* a) This library is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of the
	16	* License, or (at your option) any later version.
	17	*
	18	* This library is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* Or, alternatively,
	24	*
	25	* b) Permission is hereby granted, free of charge, to any person
	26	* obtaining a copy of this software and associated documentation
	27	* files (the "Software"), to deal in the Software without
	28	* restriction, including without limitation the rights to use,
	29	* copy, modify, merge, publish, distribute, sublicense, and/or
	30	* sell copies of the Software, and to permit persons to whom the
	31	* Software is furnished to do so, subject to the following
	32	* conditions:
	33	*
	34	* The above copyright notice and this permission notice shall be
	35	* included in all copies or substantial portions of the Software.
	36	*
	37	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	38	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	39	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	40	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	41	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	42	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	43	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	44	* OTHER DEALINGS IN THE SOFTWARE.
	45	*/
	46
	47	/ {
	48	compatible = "fsl,ls1043a";
	49	interrupt-parent = <&gic>;
	50	#address-cells = <2>;
	51	#size-cells = <2>;
	52
	53	cpus {
	54	#address-cells = <2>;
	55	#size-cells = <0>;
	56
	57	/*
	58	* We expect the enable-method for cpu's to be "psci", but this
	59	* is dependent on the SoC FW, which will fill this in.
	60	*
	61	* Currently supported enable-method is psci v0.2
	62	*/
	63	cpu0: cpu@0 {
	64	device_type = "cpu";
65	compatible = "arm,cortex-a53";
66	reg = <0x0 0x0>;
67	clocks = <&clockgen 1 0>;
68	};
69
70	cpu1: cpu@1 {
71	device_type = "cpu";
72	compatible = "arm,cortex-a53";
73	reg = <0x0 0x1>;
74	clocks = <&clockgen 1 0>;
75	};
76
77	cpu2: cpu@2 {
78	device_type = "cpu";
79	compatible = "arm,cortex-a53";
80	reg = <0x0 0x2>;
81	clocks = <&clockgen 1 0>;
82	};
83
84	cpu3: cpu@3 {
85	device_type = "cpu";
86	compatible = "arm,cortex-a53";
87	reg = <0x0 0x3>;
88	clocks = <&clockgen 1 0>;
89	};
90	};
91
92	memory@80000000 {
93	device_type = "memory";
94	reg = <0x0 0x80000000 0 0x80000000>;
95	/* DRAM space 1, size: 2GiB DRAM */
96	};
97
98	sysclk: sysclk {
99	compatible = "fixed-clock";
100	#clock-cells = <0>;
101	clock-frequency = <100000000>;
102	clock-output-names = "sysclk";
103	};
104
105	reboot {
106	compatible ="syscon-reboot";
107	regmap = <&dcfg>;
108	offset = <0xb0>;
109	mask = <0x02>;
110	};
111
112	timer {
113	compatible = "arm,armv8-timer";
114	interrupts = <1 13 0x1>, /* Physical Secure PPI */
115	<1 14 0x1>, /* Physical Non-Secure PPI */
116	<1 11 0x1>, /* Virtual PPI */
117	<1 10 0x1>; /* Hypervisor PPI */
118	};
119
120	pmu {
121	compatible = "arm,armv8-pmuv3";
122	interrupts = <0 106 0x4>,
123	<0 107 0x4>,
124	<0 95 0x4>,
125	<0 97 0x4>;
126	interrupt-affinity = <&cpu0>,
127	<&cpu1>,
128	<&cpu2>,
129	<&cpu3>;
130	};
131
132	gic: interrupt-controller@1400000 {
133	compatible = "arm,gic-400";
134	#interrupt-cells = <3>;
135	interrupt-controller;
136	reg = <0x0 0x1401000 0 0x1000>, /* GICD */
137	<0x0 0x1402000 0 0x2000>, /* GICC */
138	<0x0 0x1404000 0 0x2000>, /* GICH */
139	<0x0 0x1406000 0 0x2000>; /* GICV */
140	interrupts = <1 9 0xf08>;
141	};
142
143	soc {
144	compatible = "simple-bus";
145	#address-cells = <2>;
146	#size-cells = <2>;
147	ranges;
148
149	clockgen: clocking@1ee1000 {
150	compatible = "fsl,ls1043a-clockgen";
151	reg = <0x0 0x1ee1000 0x0 0x1000>;
152	#clock-cells = <2>;
153	clocks = <&sysclk>;
154	};
155
156	scfg: scfg@1570000 {
157	compatible = "fsl,ls1043a-scfg", "syscon";
158	reg = <0x0 0x1570000 0x0 0x10000>;
159	big-endian;
160	};
161
63dac35b HG	162	crypto: crypto@1700000 {
	163	compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
	164	"fsl,sec-v4.0";
	165	fsl,sec-era = <3>;
	166	#address-cells = <1>;
	167	#size-cells = <1>;
	168	ranges = <0x0 0x00 0x1700000 0x100000>;
	169	reg = <0x00 0x1700000 0x0 0x100000>;
	170	interrupts = <0 75 0x4>;
	171
	172	sec_jr0: jr@10000 {
	173	compatible = "fsl,sec-v5.4-job-ring",
	174	"fsl,sec-v5.0-job-ring",
	175	"fsl,sec-v4.0-job-ring";
	176	reg = <0x10000 0x10000>;
	177	interrupts = <0 71 0x4>;
	178	};
	179
	180	sec_jr1: jr@20000 {
	181	compatible = "fsl,sec-v5.4-job-ring",
	182	"fsl,sec-v5.0-job-ring",
	183	"fsl,sec-v4.0-job-ring";
	184	reg = <0x20000 0x10000>;
	185	interrupts = <0 72 0x4>;
	186	};
	187
	188	sec_jr2: jr@30000 {
	189	compatible = "fsl,sec-v5.4-job-ring",
	190	"fsl,sec-v5.0-job-ring",
	191	"fsl,sec-v4.0-job-ring";
	192	reg = <0x30000 0x10000>;
	193	interrupts = <0 73 0x4>;
	194	};
	195
	196	sec_jr3: jr@40000 {
	197	compatible = "fsl,sec-v5.4-job-ring",
	198	"fsl,sec-v5.0-job-ring",
	199	"fsl,sec-v4.0-job-ring";
	200	reg = <0x40000 0x10000>;
	201	interrupts = <0 74 0x4>;
	202	};
	203	};
	204
6d453cd2 MH	205	dcfg: dcfg@1ee0000 {
	206	compatible = "fsl,ls1043a-dcfg", "syscon";
	207	reg = <0x0 0x1ee0000 0x0 0x10000>;
	208	big-endian;
	209	};
	210
	211	ifc: ifc@1530000 {
	212	compatible = "fsl,ifc", "simple-bus";
	213	reg = <0x0 0x1530000 0x0 0x10000>;
	214	interrupts = <0 43 0x4>;
	215	};
	216
e26e054b YY	217	qspi: quadspi@1550000 {
	218	compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
	219	#address-cells = <1>;
	220	#size-cells = <0>;
	221	reg = <0x0 0x1550000 0x0 0x10000>,
	222	<0x0 0x40000000 0x0 0x4000000>;
	223	reg-names = "QuadSPI", "QuadSPI-memory";
	224	interrupts = <0 99 0x4>;
	225	clock-names = "qspi_en", "qspi";
	226	clocks = <&clockgen 4 0>, <&clockgen 4 0>;
	227	big-endian;
	228	status = "disabled";
	229	};
	230
6d453cd2 MH	231	esdhc: esdhc@1560000 {
	232	compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
	233	reg = <0x0 0x1560000 0x0 0x10000>;
	234	interrupts = <0 62 0x4>;
	235	clock-frequency = <0>;
	236	voltage-ranges = <1800 1800 3300 3300>;
	237	sdhci,auto-cmd12;
	238	big-endian;
	239	bus-width = <4>;
	240	};
	241
	242	dspi0: dspi@2100000 {
	243	compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
	244	#address-cells = <1>;
	245	#size-cells = <0>;
	246	reg = <0x0 0x2100000 0x0 0x10000>;
	247	interrupts = <0 64 0x4>;
	248	clock-names = "dspi";
	249	clocks = <&clockgen 4 0>;
	250	spi-num-chipselects = <5>;
	251	big-endian;
	252	status = "disabled";
	253	};
	254
	255	dspi1: dspi@2110000 {
	256	compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
	257	#address-cells = <1>;
	258	#size-cells = <0>;
	259	reg = <0x0 0x2110000 0x0 0x10000>;
	260	interrupts = <0 65 0x4>;
	261	clock-names = "dspi";
	262	clocks = <&clockgen 4 0>;
	263	spi-num-chipselects = <5>;
	264	big-endian;
	265	status = "disabled";
	266	};
	267
	268	i2c0: i2c@2180000 {
	269	compatible = "fsl,vf610-i2c";
	270	#address-cells = <1>;
	271	#size-cells = <0>;
	272	reg = <0x0 0x2180000 0x0 0x10000>;
	273	interrupts = <0 56 0x4>;
	274	clock-names = "i2c";
	275	clocks = <&clockgen 4 0>;
	276	dmas = <&edma0 1 39>,
	277	<&edma0 1 38>;
	278	dma-names = "tx", "rx";
	279	status = "disabled";
	280	};
	281
	282	i2c1: i2c@2190000 {
	283	compatible = "fsl,vf610-i2c";
	284	#address-cells = <1>;
	285	#size-cells = <0>;
	286	reg = <0x0 0x2190000 0x0 0x10000>;
	287	interrupts = <0 57 0x4>;
	288	clock-names = "i2c";
	289	clocks = <&clockgen 4 0>;
	290	status = "disabled";
	291	};
	292
	293	i2c2: i2c@21a0000 {
	294	compatible = "fsl,vf610-i2c";
295	#address-cells = <1>;
296	#size-cells = <0>;
297	reg = <0x0 0x21a0000 0x0 0x10000>;
298	interrupts = <0 58 0x4>;
299	clock-names = "i2c";
300	clocks = <&clockgen 4 0>;
301	status = "disabled";
302	};
303
304	i2c3: i2c@21b0000 {
305	compatible = "fsl,vf610-i2c";
306	#address-cells = <1>;
307	#size-cells = <0>;
308	reg = <0x0 0x21b0000 0x0 0x10000>;
309	interrupts = <0 59 0x4>;
310	clock-names = "i2c";
311	clocks = <&clockgen 4 0>;
312	status = "disabled";
313	};
314
315	duart0: serial@21c0500 {
316	compatible = "fsl,ns16550", "ns16550a";
317	reg = <0x00 0x21c0500 0x0 0x100>;
318	interrupts = <0 54 0x4>;
319	clocks = <&clockgen 4 0>;
320	};
321
322	duart1: serial@21c0600 {
323	compatible = "fsl,ns16550", "ns16550a";
324	reg = <0x00 0x21c0600 0x0 0x100>;
325	interrupts = <0 54 0x4>;
326	clocks = <&clockgen 4 0>;
327	};
328
329	duart2: serial@21d0500 {
330	compatible = "fsl,ns16550", "ns16550a";
331	reg = <0x0 0x21d0500 0x0 0x100>;
332	interrupts = <0 55 0x4>;
333	clocks = <&clockgen 4 0>;
334	};
335
336	duart3: serial@21d0600 {
337	compatible = "fsl,ns16550", "ns16550a";
338	reg = <0x0 0x21d0600 0x0 0x100>;
339	interrupts = <0 55 0x4>;
340	clocks = <&clockgen 4 0>;
341	};
342
343	gpio1: gpio@2300000 {
c21de87d	344	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	345	reg = <0x0 0x2300000 0x0 0x10000>;
	346	interrupts = <0 66 0x4>;
	347	gpio-controller;
	348	#gpio-cells = <2>;
	349	interrupt-controller;
	350	#interrupt-cells = <2>;
	351	};
	352
	353	gpio2: gpio@2310000 {
c21de87d	354	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	355	reg = <0x0 0x2310000 0x0 0x10000>;
	356	interrupts = <0 67 0x4>;
	357	gpio-controller;
	358	#gpio-cells = <2>;
	359	interrupt-controller;
	360	#interrupt-cells = <2>;
	361	};
	362
	363	gpio3: gpio@2320000 {
c21de87d	364	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	365	reg = <0x0 0x2320000 0x0 0x10000>;
	366	interrupts = <0 68 0x4>;
	367	gpio-controller;
	368	#gpio-cells = <2>;
	369	interrupt-controller;
	370	#interrupt-cells = <2>;
	371	};
	372
	373	gpio4: gpio@2330000 {
c21de87d	374	compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
6d453cd2 MH	375	reg = <0x0 0x2330000 0x0 0x10000>;
	376	interrupts = <0 134 0x4>;
	377	gpio-controller;
	378	#gpio-cells = <2>;
	379	interrupt-controller;
	380	#interrupt-cells = <2>;
	381	};
	382
	383	lpuart0: serial@2950000 {
	384	compatible = "fsl,ls1021a-lpuart";
	385	reg = <0x0 0x2950000 0x0 0x1000>;
	386	interrupts = <0 48 0x4>;
	387	clocks = <&clockgen 0 0>;
	388	clock-names = "ipg";
	389	status = "disabled";
	390	};
	391
	392	lpuart1: serial@2960000 {
	393	compatible = "fsl,ls1021a-lpuart";
	394	reg = <0x0 0x2960000 0x0 0x1000>;
	395	interrupts = <0 49 0x4>;
	396	clocks = <&clockgen 4 0>;
	397	clock-names = "ipg";
	398	status = "disabled";
	399	};
	400
	401	lpuart2: serial@2970000 {
	402	compatible = "fsl,ls1021a-lpuart";
	403	reg = <0x0 0x2970000 0x0 0x1000>;
	404	interrupts = <0 50 0x4>;
	405	clocks = <&clockgen 4 0>;
	406	clock-names = "ipg";
	407	status = "disabled";
	408	};
	409
	410	lpuart3: serial@2980000 {
	411	compatible = "fsl,ls1021a-lpuart";
	412	reg = <0x0 0x2980000 0x0 0x1000>;
	413	interrupts = <0 51 0x4>;
	414	clocks = <&clockgen 4 0>;
	415	clock-names = "ipg";
	416	status = "disabled";
	417	};
	418
	419	lpuart4: serial@2990000 {
	420	compatible = "fsl,ls1021a-lpuart";
	421	reg = <0x0 0x2990000 0x0 0x1000>;
	422	interrupts = <0 52 0x4>;
	423	clocks = <&clockgen 4 0>;
	424	clock-names = "ipg";
	425	status = "disabled";
	426	};
	427
	428	lpuart5: serial@29a0000 {
	429	compatible = "fsl,ls1021a-lpuart";
	430	reg = <0x0 0x29a0000 0x0 0x1000>;
	431	interrupts = <0 53 0x4>;
	432	clocks = <&clockgen 4 0>;
	433	clock-names = "ipg";
	434	status = "disabled";
	435	};
	436
	437	wdog0: wdog@2ad0000 {
	438	compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
439	reg = <0x0 0x2ad0000 0x0 0x10000>;
440	interrupts = <0 83 0x4>;
441	clocks = <&clockgen 4 0>;
442	clock-names = "wdog";
443	big-endian;
444	};
445
446	edma0: edma@2c00000 {
447	#dma-cells = <2>;
448	compatible = "fsl,vf610-edma";
449	reg = <0x0 0x2c00000 0x0 0x10000>,
450	<0x0 0x2c10000 0x0 0x10000>,
451	<0x0 0x2c20000 0x0 0x10000>;
452	interrupts = <0 103 0x4>,
453	<0 103 0x4>;
454	interrupt-names = "edma-tx", "edma-err";
455	dma-channels = <32>;
456	big-endian;
457	clock-names = "dmamux0", "dmamux1";
458	clocks = <&clockgen 4 0>,
459	<&clockgen 4 0>;
460	};
461
462	usb0: usb3@2f00000 {
463	compatible = "snps,dwc3";
464	reg = <0x0 0x2f00000 0x0 0x10000>;
465	interrupts = <0 60 0x4>;
466	dr_mode = "host";
4c1d9ea7	467	snps,quirk-frame-length-adjustment = <0x20>;
6d453cd2 MH	468	};
	469
	470	usb1: usb3@3000000 {
	471	compatible = "snps,dwc3";
	472	reg = <0x0 0x3000000 0x0 0x10000>;
	473	interrupts = <0 61 0x4>;
	474	dr_mode = "host";
4c1d9ea7	475	snps,quirk-frame-length-adjustment = <0x20>;
6d453cd2 MH	476	};
	477
	478	usb2: usb3@3100000 {
	479	compatible = "snps,dwc3";
	480	reg = <0x0 0x3100000 0x0 0x10000>;
	481	interrupts = <0 63 0x4>;
	482	dr_mode = "host";
4c1d9ea7	483	snps,quirk-frame-length-adjustment = <0x20>;
6d453cd2 MH	484	};
	485
	486	sata: sata@3200000 {
	487	compatible = "fsl,ls1043a-ahci", "fsl,ls1021a-ahci";
	488	reg = <0x0 0x3200000 0x0 0x10000>;
	489	interrupts = <0 69 0x4>;
	490	clocks = <&clockgen 4 0>;
	491	};
	492
	493	msi1: msi-controller1@1571000 {
	494	compatible = "fsl,1s1043a-msi";
	495	reg = <0x0 0x1571000 0x0 0x8>;
	496	msi-controller;
	497	interrupts = <0 116 0x4>;
	498	};
	499
	500	msi2: msi-controller2@1572000 {
	501	compatible = "fsl,1s1043a-msi";
	502	reg = <0x0 0x1572000 0x0 0x8>;
	503	msi-controller;
	504	interrupts = <0 126 0x4>;
	505	};
	506
	507	msi3: msi-controller3@1573000 {
	508	compatible = "fsl,1s1043a-msi";
	509	reg = <0x0 0x1573000 0x0 0x8>;
	510	msi-controller;
	511	interrupts = <0 160 0x4>;
	512	};
	513
	514	pcie@3400000 {
	515	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
	516	reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
	517	0x40 0x00000000 0x0 0x00002000>; /* configuration space */
	518	reg-names = "regs", "config";
	519	interrupts = <0 118 0x4>, /* controller interrupt */
	520	<0 117 0x4>; /* PME interrupt */
	521	interrupt-names = "intr", "pme";
	522	#address-cells = <3>;
	523	#size-cells = <2>;
	524	device_type = "pci";
	525	num-lanes = <4>;
	526	bus-range = <0x0 0xff>;
	527	ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
	528	0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
	529	msi-parent = <&msi1>;
	530	#interrupt-cells = <1>;
	531	interrupt-map-mask = <0 0 0 7>;
	532	interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
	533	<0000 0 0 2 &gic 0 111 0x4>,
	534	<0000 0 0 3 &gic 0 112 0x4>,
	535	<0000 0 0 4 &gic 0 113 0x4>;
	536	};
	537
	538	pcie@3500000 {
	539	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
	540	reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
	541	0x48 0x00000000 0x0 0x00002000>; /* configuration space */
	542	reg-names = "regs", "config";
	543	interrupts = <0 128 0x4>,
	544	<0 127 0x4>;
	545	interrupt-names = "intr", "pme";
	546	#address-cells = <3>;
	547	#size-cells = <2>;
548	device_type = "pci";
549	num-lanes = <2>;
550	bus-range = <0x0 0xff>;
551	ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
552	0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
553	msi-parent = <&msi2>;
554	#interrupt-cells = <1>;
555	interrupt-map-mask = <0 0 0 7>;
556	interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
557	<0000 0 0 2 &gic 0 121 0x4>,
558	<0000 0 0 3 &gic 0 122 0x4>,
559	<0000 0 0 4 &gic 0 123 0x4>;
560	};
561
562	pcie@3600000 {
563	compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
564	reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
565	0x50 0x00000000 0x0 0x00002000>; /* configuration space */
566	reg-names = "regs", "config";
567	interrupts = <0 162 0x4>,
568	<0 161 0x4>;
569	interrupt-names = "intr", "pme";
570	#address-cells = <3>;
571	#size-cells = <2>;
572	device_type = "pci";
573	num-lanes = <2>;
574	bus-range = <0x0 0xff>;
575	ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
576	0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
577	msi-parent = <&msi3>;
578	#interrupt-cells = <1>;
579	interrupt-map-mask = <0 0 0 7>;
580	interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
581	<0000 0 0 2 &gic 0 155 0x4>,
582	<0000 0 0 3 &gic 0 156 0x4>,
583	<0000 0 0 4 &gic 0 157 0x4>;
584	};
585	};
586
587	};