projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| ee877b53 VK |
1 | /* |
| 2 | * dts file for AppliedMicro (APM) X-Gene Storm SOC | |
| 3 | * | |
| 4 | * Copyright (C) 2013, Applied Micro Circuits Corporation | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation; either version 2 of | |
| 9 | * the License, or (at your option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | / { | |
| 13 | compatible = "apm,xgene-storm"; | |
| 14 | interrupt-parent = <&gic>; | |
| 15 | #address-cells = <2>; | |
| 16 | #size-cells = <2>; | |
| 17 | ||
| 18 | cpus { | |
| 19 | #address-cells = <2>; | |
| 20 | #size-cells = <0>; | |
| 21 | ||
| 22 | cpu@000 { | |
| 23 | device_type = "cpu"; | |
| 24 | compatible = "apm,potenza", "arm,armv8"; | |
| 25 | reg = <0x0 0x000>; | |
| 26 | enable-method = "spin-table"; | |
| 27 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 28 | }; | |
| 29 | cpu@001 { | |
| 30 | device_type = "cpu"; | |
| 31 | compatible = "apm,potenza", "arm,armv8"; | |
| 32 | reg = <0x0 0x001>; | |
| 33 | enable-method = "spin-table"; | |
| 34 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 35 | }; | |
| 36 | cpu@100 { | |
| 37 | device_type = "cpu"; | |
| 38 | compatible = "apm,potenza", "arm,armv8"; | |
| 39 | reg = <0x0 0x100>; | |
| 40 | enable-method = "spin-table"; | |
| 41 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 42 | }; | |
| 43 | cpu@101 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "apm,potenza", "arm,armv8"; | |
| 46 | reg = <0x0 0x101>; | |
| 47 | enable-method = "spin-table"; | |
| 48 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 49 | }; | |
| 50 | cpu@200 { | |
| 51 | device_type = "cpu"; | |
| 52 | compatible = "apm,potenza", "arm,armv8"; | |
| 53 | reg = <0x0 0x200>; | |
| 54 | enable-method = "spin-table"; | |
| 55 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 56 | }; | |
| 57 | cpu@201 { | |
| 58 | device_type = "cpu"; | |
| 59 | compatible = "apm,potenza", "arm,armv8"; | |
| 60 | reg = <0x0 0x201>; | |
| 61 | enable-method = "spin-table"; | |
| 62 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 63 | }; | |
| 64 | cpu@300 { | |
| 65 | device_type = "cpu"; | |
| 66 | compatible = "apm,potenza", "arm,armv8"; | |
| 67 | reg = <0x0 0x300>; | |
| 68 | enable-method = "spin-table"; | |
| 69 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 70 | }; | |
| 71 | cpu@301 { | |
| 72 | device_type = "cpu"; | |
| 73 | compatible = "apm,potenza", "arm,armv8"; | |
| 74 | reg = <0x0 0x301>; | |
| 75 | enable-method = "spin-table"; | |
| 76 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 77 | }; | |
| 78 | }; | |
| 79 | ||
| 80 | gic: interrupt-controller@78010000 { | |
| 81 | compatible = "arm,cortex-a15-gic"; | |
| 82 | #interrupt-cells = <3>; | |
| 83 | interrupt-controller; | |
| 84 | reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ | |
| 85 | <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ | |
| 86 | <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ | |
| 87 | <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ | |
| 88 | interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ | |
| 89 | }; | |
| 90 | ||
| 91 | timer { | |
| 92 | compatible = "arm,armv8-timer"; | |
| 93 | interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ | |
| 94 | <1 13 0xff01>, /* Non-secure Phys IRQ */ | |
| 95 | <1 14 0xff01>, /* Virt IRQ */ | |
| 96 | <1 15 0xff01>; /* Hyp IRQ */ | |
| 97 | clock-frequency = <50000000>; | |
| 98 | }; | |
| 99 | ||
| 100 | soc { | |
| 101 | compatible = "simple-bus"; | |
| 102 | #address-cells = <2>; | |
| 103 | #size-cells = <2>; | |
| 104 | ranges; | |
| 105 | ||
| 3eb15d84 LH |
106 | clocks { |
| 107 | #address-cells = <2>; | |
| 108 | #size-cells = <2>; | |
| 109 | ranges; | |
| 110 | refclk: refclk { | |
| 111 | compatible = "fixed-clock"; | |
| 112 | #clock-cells = <1>; | |
| 113 | clock-frequency = <100000000>; | |
| 114 | clock-output-names = "refclk"; | |
| 115 | }; | |
| 116 | ||
| 117 | pcppll: pcppll@17000100 { | |
| 118 | compatible = "apm,xgene-pcppll-clock"; | |
| 119 | #clock-cells = <1>; | |
| 120 | clocks = <&refclk 0>; | |
| 121 | clock-names = "pcppll"; | |
| 122 | reg = <0x0 0x17000100 0x0 0x1000>; | |
| 123 | clock-output-names = "pcppll"; | |
| 124 | type = <0>; | |
| 125 | }; | |
| 126 | ||
| 127 | socpll: socpll@17000120 { | |
| 128 | compatible = "apm,xgene-socpll-clock"; | |
| 129 | #clock-cells = <1>; | |
| 130 | clocks = <&refclk 0>; | |
| 131 | clock-names = "socpll"; | |
| 132 | reg = <0x0 0x17000120 0x0 0x1000>; | |
| 133 | clock-output-names = "socpll"; | |
| 134 | type = <1>; | |
| 135 | }; | |
| 136 | ||
| 137 | socplldiv2: socplldiv2 { | |
| 138 | compatible = "fixed-factor-clock"; | |
| 139 | #clock-cells = <1>; | |
| 140 | clocks = <&socpll 0>; | |
| 141 | clock-names = "socplldiv2"; | |
| 142 | clock-mult = <1>; | |
| 143 | clock-div = <2>; | |
| 144 | clock-output-names = "socplldiv2"; | |
| 145 | }; | |
| 146 | ||
| 147 | qmlclk: qmlclk { | |
| 148 | compatible = "apm,xgene-device-clock"; | |
| 149 | #clock-cells = <1>; | |
| 150 | clocks = <&socplldiv2 0>; | |
| 151 | clock-names = "qmlclk"; | |
| 152 | reg = <0x0 0x1703C000 0x0 0x1000>; | |
| 153 | reg-names = "csr-reg"; | |
| 154 | clock-output-names = "qmlclk"; | |
| 155 | }; | |
| 156 | ||
| 157 | ethclk: ethclk { | |
| 158 | compatible = "apm,xgene-device-clock"; | |
| 159 | #clock-cells = <1>; | |
| 160 | clocks = <&socplldiv2 0>; | |
| 161 | clock-names = "ethclk"; | |
| 162 | reg = <0x0 0x17000000 0x0 0x1000>; | |
| 163 | reg-names = "div-reg"; | |
| 164 | divider-offset = <0x238>; | |
| 165 | divider-width = <0x9>; | |
| 166 | divider-shift = <0x0>; | |
| 167 | clock-output-names = "ethclk"; | |
| 168 | }; | |
| 169 | ||
| 3d390425 | 170 | menetclk: menetclk { |
| 3eb15d84 LH |
171 | compatible = "apm,xgene-device-clock"; |
| 172 | #clock-cells = <1>; | |
| 173 | clocks = <ðclk 0>; | |
| 3eb15d84 LH |
174 | reg = <0x0 0x1702C000 0x0 0x1000>; |
| 175 | reg-names = "csr-reg"; | |
| 3d390425 | 176 | clock-output-names = "menetclk"; |
| 3eb15d84 | 177 | }; |
| 71b70ee9 | 178 | |
| 4c2e7f09 IS |
179 | sge0clk: sge0clk@1f21c000 { |
| 180 | compatible = "apm,xgene-device-clock"; | |
| 181 | #clock-cells = <1>; | |
| 182 | clocks = <&socplldiv2 0>; | |
| 183 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 184 | reg-names = "csr-reg"; | |
| 185 | csr-mask = <0x3>; | |
| 186 | clock-output-names = "sge0clk"; | |
| 187 | }; | |
| 188 | ||
| 5fb32417 IS |
189 | xge0clk: xge0clk@1f61c000 { |
| 190 | compatible = "apm,xgene-device-clock"; | |
| 191 | #clock-cells = <1>; | |
| 192 | clocks = <&socplldiv2 0>; | |
| 193 | reg = <0x0 0x1f61c000 0x0 0x1000>; | |
| 194 | reg-names = "csr-reg"; | |
| 195 | csr-mask = <0x3>; | |
| 196 | clock-output-names = "xge0clk"; | |
| 197 | }; | |
| 198 | ||
| 71b70ee9 LH |
199 | sataphy1clk: sataphy1clk@1f21c000 { |
| 200 | compatible = "apm,xgene-device-clock"; | |
| 201 | #clock-cells = <1>; | |
| 202 | clocks = <&socplldiv2 0>; | |
| 203 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 204 | reg-names = "csr-reg"; | |
| 205 | clock-output-names = "sataphy1clk"; | |
| 206 | status = "disabled"; | |
| 207 | csr-offset = <0x4>; | |
| 208 | csr-mask = <0x00>; | |
| 209 | enable-offset = <0x0>; | |
| 210 | enable-mask = <0x06>; | |
| 211 | }; | |
| 212 | ||
| 213 | sataphy2clk: sataphy1clk@1f22c000 { | |
| 214 | compatible = "apm,xgene-device-clock"; | |
| 215 | #clock-cells = <1>; | |
| 216 | clocks = <&socplldiv2 0>; | |
| 217 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
| 218 | reg-names = "csr-reg"; | |
| 219 | clock-output-names = "sataphy2clk"; | |
| 220 | status = "ok"; | |
| 221 | csr-offset = <0x4>; | |
| 222 | csr-mask = <0x3a>; | |
| 223 | enable-offset = <0x0>; | |
| 224 | enable-mask = <0x06>; | |
| 225 | }; | |
| 226 | ||
| 227 | sataphy3clk: sataphy1clk@1f23c000 { | |
| 228 | compatible = "apm,xgene-device-clock"; | |
| 229 | #clock-cells = <1>; | |
| 230 | clocks = <&socplldiv2 0>; | |
| 231 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
| 232 | reg-names = "csr-reg"; | |
| 233 | clock-output-names = "sataphy3clk"; | |
| 234 | status = "ok"; | |
| 235 | csr-offset = <0x4>; | |
| 236 | csr-mask = <0x3a>; | |
| 237 | enable-offset = <0x0>; | |
| 238 | enable-mask = <0x06>; | |
| 239 | }; | |
| db8c0286 LH |
240 | |
| 241 | sata01clk: sata01clk@1f21c000 { | |
| 242 | compatible = "apm,xgene-device-clock"; | |
| 243 | #clock-cells = <1>; | |
| 244 | clocks = <&socplldiv2 0>; | |
| 245 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 246 | reg-names = "csr-reg"; | |
| 247 | clock-output-names = "sata01clk"; | |
| 248 | csr-offset = <0x4>; | |
| 249 | csr-mask = <0x05>; | |
| 250 | enable-offset = <0x0>; | |
| 251 | enable-mask = <0x39>; | |
| 252 | }; | |
| 253 | ||
| 254 | sata23clk: sata23clk@1f22c000 { | |
| 255 | compatible = "apm,xgene-device-clock"; | |
| 256 | #clock-cells = <1>; | |
| 257 | clocks = <&socplldiv2 0>; | |
| 258 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
| 259 | reg-names = "csr-reg"; | |
| 260 | clock-output-names = "sata23clk"; | |
| 261 | csr-offset = <0x4>; | |
| 262 | csr-mask = <0x05>; | |
| 263 | enable-offset = <0x0>; | |
| 264 | enable-mask = <0x39>; | |
| 265 | }; | |
| 266 | ||
| 267 | sata45clk: sata45clk@1f23c000 { | |
| 268 | compatible = "apm,xgene-device-clock"; | |
| 269 | #clock-cells = <1>; | |
| 270 | clocks = <&socplldiv2 0>; | |
| 271 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
| 272 | reg-names = "csr-reg"; | |
| 273 | clock-output-names = "sata45clk"; | |
| 274 | csr-offset = <0x4>; | |
| 275 | csr-mask = <0x05>; | |
| 276 | enable-offset = <0x0>; | |
| 277 | enable-mask = <0x39>; | |
| 278 | }; | |
| 652ba666 LH |
279 | |
| 280 | rtcclk: rtcclk@17000000 { | |
| 281 | compatible = "apm,xgene-device-clock"; | |
| 282 | #clock-cells = <1>; | |
| 283 | clocks = <&socplldiv2 0>; | |
| 284 | reg = <0x0 0x17000000 0x0 0x2000>; | |
| 285 | reg-names = "csr-reg"; | |
| 286 | csr-offset = <0xc>; | |
| 287 | csr-mask = <0x2>; | |
| 288 | enable-offset = <0x10>; | |
| 289 | enable-mask = <0x2>; | |
| 290 | clock-output-names = "rtcclk"; | |
| 291 | }; | |
| ab818739 FK |
292 | |
| 293 | rngpkaclk: rngpkaclk@17000000 { | |
| 294 | compatible = "apm,xgene-device-clock"; | |
| 295 | #clock-cells = <1>; | |
| 296 | clocks = <&socplldiv2 0>; | |
| 297 | reg = <0x0 0x17000000 0x0 0x2000>; | |
| 298 | reg-names = "csr-reg"; | |
| 299 | csr-offset = <0xc>; | |
| 300 | csr-mask = <0x10>; | |
| 301 | enable-offset = <0x10>; | |
| 302 | enable-mask = <0x10>; | |
| 303 | clock-output-names = "rngpkaclk"; | |
| 304 | }; | |
| 80213c03 | 305 | |
| 767ebaff TI |
306 | pcie0clk: pcie0clk@1f2bc000 { |
| 307 | status = "disabled"; | |
| 308 | compatible = "apm,xgene-device-clock"; | |
| 309 | #clock-cells = <1>; | |
| 310 | clocks = <&socplldiv2 0>; | |
| 311 | reg = <0x0 0x1f2bc000 0x0 0x1000>; | |
| 312 | reg-names = "csr-reg"; | |
| 313 | clock-output-names = "pcie0clk"; | |
| 314 | }; | |
| 315 | ||
| 316 | pcie1clk: pcie1clk@1f2cc000 { | |
| 317 | status = "disabled"; | |
| 318 | compatible = "apm,xgene-device-clock"; | |
| 319 | #clock-cells = <1>; | |
| 320 | clocks = <&socplldiv2 0>; | |
| 321 | reg = <0x0 0x1f2cc000 0x0 0x1000>; | |
| 322 | reg-names = "csr-reg"; | |
| 323 | clock-output-names = "pcie1clk"; | |
| 324 | }; | |
| 325 | ||
| 326 | pcie2clk: pcie2clk@1f2dc000 { | |
| 327 | status = "disabled"; | |
| 328 | compatible = "apm,xgene-device-clock"; | |
| 329 | #clock-cells = <1>; | |
| 330 | clocks = <&socplldiv2 0>; | |
| 331 | reg = <0x0 0x1f2dc000 0x0 0x1000>; | |
| 332 | reg-names = "csr-reg"; | |
| 333 | clock-output-names = "pcie2clk"; | |
| 334 | }; | |
| 335 | ||
| 336 | pcie3clk: pcie3clk@1f50c000 { | |
| 337 | status = "disabled"; | |
| 338 | compatible = "apm,xgene-device-clock"; | |
| 339 | #clock-cells = <1>; | |
| 340 | clocks = <&socplldiv2 0>; | |
| 341 | reg = <0x0 0x1f50c000 0x0 0x1000>; | |
| 342 | reg-names = "csr-reg"; | |
| 343 | clock-output-names = "pcie3clk"; | |
| 344 | }; | |
| 345 | ||
| 346 | pcie4clk: pcie4clk@1f51c000 { | |
| 347 | status = "disabled"; | |
| 348 | compatible = "apm,xgene-device-clock"; | |
| 349 | #clock-cells = <1>; | |
| 350 | clocks = <&socplldiv2 0>; | |
| 351 | reg = <0x0 0x1f51c000 0x0 0x1000>; | |
| 352 | reg-names = "csr-reg"; | |
| 353 | clock-output-names = "pcie4clk"; | |
| 354 | }; | |
| 355 | }; | |
| 356 | ||
| 357 | pcie0: pcie@1f2b0000 { | |
| 358 | status = "disabled"; | |
| 359 | device_type = "pci"; | |
| 360 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 361 | #interrupt-cells = <1>; | |
| 362 | #size-cells = <2>; | |
| 363 | #address-cells = <3>; | |
| 364 | reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ | |
| 365 | 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 366 | reg-names = "csr", "cfg"; | |
| 367 | ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ | |
| 368 | 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ | |
| 369 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 | |
| 370 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 371 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 372 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 | |
| 373 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 | |
| 374 | 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 | |
| 375 | 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; | |
| 376 | dma-coherent; | |
| 377 | clocks = <&pcie0clk 0>; | |
| 378 | }; | |
| 379 | ||
| 380 | pcie1: pcie@1f2c0000 { | |
| 381 | status = "disabled"; | |
| 382 | device_type = "pci"; | |
| 383 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 384 | #interrupt-cells = <1>; | |
| 385 | #size-cells = <2>; | |
| 386 | #address-cells = <3>; | |
| 387 | reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ | |
| 388 | 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 389 | reg-names = "csr", "cfg"; | |
| 390 | ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ | |
| 391 | 0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */ | |
| 392 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 | |
| 393 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 394 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 395 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 | |
| 396 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 | |
| 397 | 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 | |
| 398 | 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; | |
| 399 | dma-coherent; | |
| 400 | clocks = <&pcie1clk 0>; | |
| 401 | }; | |
| 402 | ||
| 403 | pcie2: pcie@1f2d0000 { | |
| 404 | status = "disabled"; | |
| 405 | device_type = "pci"; | |
| 406 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 407 | #interrupt-cells = <1>; | |
| 408 | #size-cells = <2>; | |
| 409 | #address-cells = <3>; | |
| 410 | reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ | |
| 411 | 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 412 | reg-names = "csr", "cfg"; | |
| 413 | ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000 /* io */ | |
| 414 | 0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */ | |
| 415 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 | |
| 416 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 417 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 418 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 | |
| 419 | 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 | |
| 420 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 | |
| 421 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; | |
| 422 | dma-coherent; | |
| 423 | clocks = <&pcie2clk 0>; | |
| 424 | }; | |
| 425 | ||
| 426 | pcie3: pcie@1f500000 { | |
| 427 | status = "disabled"; | |
| 428 | device_type = "pci"; | |
| 429 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 430 | #interrupt-cells = <1>; | |
| 431 | #size-cells = <2>; | |
| 432 | #address-cells = <3>; | |
| 433 | reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ | |
| 434 | 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 435 | reg-names = "csr", "cfg"; | |
| 436 | ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000 /* io */ | |
| 437 | 0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem */ | |
| 438 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 | |
| 439 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 440 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 441 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 | |
| 442 | 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 | |
| 443 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 | |
| 444 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; | |
| 445 | dma-coherent; | |
| 446 | clocks = <&pcie3clk 0>; | |
| 447 | }; | |
| 448 | ||
| 449 | pcie4: pcie@1f510000 { | |
| 450 | status = "disabled"; | |
| 451 | device_type = "pci"; | |
| 452 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 453 | #interrupt-cells = <1>; | |
| 454 | #size-cells = <2>; | |
| 455 | #address-cells = <3>; | |
| 456 | reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ | |
| 457 | 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ | |
| 458 | reg-names = "csr", "cfg"; | |
| 459 | ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000 /* io */ | |
| 460 | 0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */ | |
| 461 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 | |
| 462 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 463 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 464 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 | |
| 465 | 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 | |
| 466 | 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 | |
| 467 | 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; | |
| 468 | dma-coherent; | |
| 469 | clocks = <&pcie4clk 0>; | |
| 3eb15d84 LH |
470 | }; |
| 471 | ||
| ee877b53 | 472 | serial0: serial@1c020000 { |
| 457ced84 | 473 | status = "disabled"; |
| ee877b53 | 474 | device_type = "serial"; |
| 457ced84 | 475 | compatible = "ns16550a"; |
| ee877b53 VK |
476 | reg = <0 0x1c020000 0x0 0x1000>; |
| 477 | reg-shift = <2>; | |
| 478 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 479 | interrupt-parent = <&gic>; | |
| 480 | interrupts = <0x0 0x4c 0x4>; | |
| 481 | }; | |
| 71b70ee9 | 482 | |
| 457ced84 VK |
483 | serial1: serial@1c021000 { |
| 484 | status = "disabled"; | |
| 485 | device_type = "serial"; | |
| 486 | compatible = "ns16550a"; | |
| 487 | reg = <0 0x1c021000 0x0 0x1000>; | |
| 488 | reg-shift = <2>; | |
| 489 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 490 | interrupt-parent = <&gic>; | |
| 491 | interrupts = <0x0 0x4d 0x4>; | |
| 492 | }; | |
| 493 | ||
| 494 | serial2: serial@1c022000 { | |
| 495 | status = "disabled"; | |
| 496 | device_type = "serial"; | |
| 497 | compatible = "ns16550a"; | |
| 498 | reg = <0 0x1c022000 0x0 0x1000>; | |
| 499 | reg-shift = <2>; | |
| 500 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 501 | interrupt-parent = <&gic>; | |
| 502 | interrupts = <0x0 0x4e 0x4>; | |
| 503 | }; | |
| 504 | ||
| 505 | serial3: serial@1c023000 { | |
| 506 | status = "disabled"; | |
| 507 | device_type = "serial"; | |
| 508 | compatible = "ns16550a"; | |
| 509 | reg = <0 0x1c023000 0x0 0x1000>; | |
| 510 | reg-shift = <2>; | |
| 511 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 512 | interrupt-parent = <&gic>; | |
| 513 | interrupts = <0x0 0x4f 0x4>; | |
| 514 | }; | |
| 515 | ||
| 71b70ee9 LH |
516 | phy1: phy@1f21a000 { |
| 517 | compatible = "apm,xgene-phy"; | |
| 518 | reg = <0x0 0x1f21a000 0x0 0x100>; | |
| 519 | #phy-cells = <1>; | |
| 520 | clocks = <&sataphy1clk 0>; | |
| 521 | status = "disabled"; | |
| 522 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
| 523 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
| 524 | }; | |
| 525 | ||
| 526 | phy2: phy@1f22a000 { | |
| 527 | compatible = "apm,xgene-phy"; | |
| 528 | reg = <0x0 0x1f22a000 0x0 0x100>; | |
| 529 | #phy-cells = <1>; | |
| 530 | clocks = <&sataphy2clk 0>; | |
| 531 | status = "ok"; | |
| 532 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
| 533 | apm,tx-eye-tuning = <1 10 10 2 10 10>; | |
| 534 | }; | |
| 535 | ||
| 536 | phy3: phy@1f23a000 { | |
| 537 | compatible = "apm,xgene-phy"; | |
| 538 | reg = <0x0 0x1f23a000 0x0 0x100>; | |
| 539 | #phy-cells = <1>; | |
| 540 | clocks = <&sataphy3clk 0>; | |
| 541 | status = "ok"; | |
| 542 | apm,tx-boost-gain = <31 31 31 31 31 31>; | |
| 543 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
| 544 | }; | |
| db8c0286 LH |
545 | |
| 546 | sata1: sata@1a000000 { | |
| 547 | compatible = "apm,xgene-ahci"; | |
| 548 | reg = <0x0 0x1a000000 0x0 0x1000>, | |
| 549 | <0x0 0x1f210000 0x0 0x1000>, | |
| 550 | <0x0 0x1f21d000 0x0 0x1000>, | |
| 551 | <0x0 0x1f21e000 0x0 0x1000>, | |
| 552 | <0x0 0x1f217000 0x0 0x1000>; | |
| 553 | interrupts = <0x0 0x86 0x4>; | |
| 7a8d1ec1 | 554 | dma-coherent; |
| db8c0286 LH |
555 | status = "disabled"; |
| 556 | clocks = <&sata01clk 0>; | |
| 557 | phys = <&phy1 0>; | |
| 558 | phy-names = "sata-phy"; | |
| 559 | }; | |
| 560 | ||
| 561 | sata2: sata@1a400000 { | |
| 562 | compatible = "apm,xgene-ahci"; | |
| 563 | reg = <0x0 0x1a400000 0x0 0x1000>, | |
| 564 | <0x0 0x1f220000 0x0 0x1000>, | |
| 565 | <0x0 0x1f22d000 0x0 0x1000>, | |
| 566 | <0x0 0x1f22e000 0x0 0x1000>, | |
| 567 | <0x0 0x1f227000 0x0 0x1000>; | |
| 568 | interrupts = <0x0 0x87 0x4>; | |
| 7a8d1ec1 | 569 | dma-coherent; |
| db8c0286 LH |
570 | status = "ok"; |
| 571 | clocks = <&sata23clk 0>; | |
| 572 | phys = <&phy2 0>; | |
| 573 | phy-names = "sata-phy"; | |
| 574 | }; | |
| 575 | ||
| 576 | sata3: sata@1a800000 { | |
| 577 | compatible = "apm,xgene-ahci"; | |
| 578 | reg = <0x0 0x1a800000 0x0 0x1000>, | |
| 579 | <0x0 0x1f230000 0x0 0x1000>, | |
| 580 | <0x0 0x1f23d000 0x0 0x1000>, | |
| 581 | <0x0 0x1f23e000 0x0 0x1000>; | |
| 582 | interrupts = <0x0 0x88 0x4>; | |
| 7a8d1ec1 | 583 | dma-coherent; |
| db8c0286 LH |
584 | status = "ok"; |
| 585 | clocks = <&sata45clk 0>; | |
| 586 | phys = <&phy3 0>; | |
| 587 | phy-names = "sata-phy"; | |
| 588 | }; | |
| 652ba666 LH |
589 | |
| 590 | rtc: rtc@10510000 { | |
| 591 | compatible = "apm,xgene-rtc"; | |
| 592 | reg = <0x0 0x10510000 0x0 0x400>; | |
| 593 | interrupts = <0x0 0x46 0x4>; | |
| 594 | #clock-cells = <1>; | |
| 595 | clocks = <&rtcclk 0>; | |
| 596 | }; | |
| 3d390425 IS |
597 | |
| 598 | menet: ethernet@17020000 { | |
| 599 | compatible = "apm,xgene-enet"; | |
| 600 | status = "disabled"; | |
| 601 | reg = <0x0 0x17020000 0x0 0xd100>, | |
| 09c9e059 | 602 | <0x0 0X17030000 0x0 0Xc300>, |
| 3d390425 IS |
603 | <0x0 0X10000000 0x0 0X200>; |
| 604 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
| 605 | interrupts = <0x0 0x3c 0x4>; | |
| 606 | dma-coherent; | |
| 607 | clocks = <&menetclk 0>; | |
| 5fb32417 IS |
608 | /* mac address will be overwritten by the bootloader */ |
| 609 | local-mac-address = [00 00 00 00 00 00]; | |
| 3d390425 IS |
610 | phy-connection-type = "rgmii"; |
| 611 | phy-handle = <&menetphy>; | |
| 612 | mdio { | |
| 613 | compatible = "apm,xgene-mdio"; | |
| 614 | #address-cells = <1>; | |
| 615 | #size-cells = <0>; | |
| 616 | menetphy: menetphy@3 { | |
| 617 | compatible = "ethernet-phy-id001c.c915"; | |
| 618 | reg = <0x3>; | |
| 619 | }; | |
| 620 | ||
| 621 | }; | |
| 622 | }; | |
| ab818739 | 623 | |
| 4c2e7f09 IS |
624 | sgenet0: ethernet@1f210000 { |
| 625 | compatible = "apm,xgene-enet"; | |
| 626 | status = "disabled"; | |
| 09c9e059 IS |
627 | reg = <0x0 0x1f210000 0x0 0xd100>, |
| 628 | <0x0 0x1f200000 0x0 0Xc300>, | |
| 629 | <0x0 0x1B000000 0x0 0X200>; | |
| 4c2e7f09 IS |
630 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
| 631 | interrupts = <0x0 0xA0 0x4>; | |
| 632 | dma-coherent; | |
| 633 | clocks = <&sge0clk 0>; | |
| 634 | local-mac-address = [00 00 00 00 00 00]; | |
| 635 | phy-connection-type = "sgmii"; | |
| 636 | }; | |
| 637 | ||
| 5fb32417 IS |
638 | xgenet: ethernet@1f610000 { |
| 639 | compatible = "apm,xgene-enet"; | |
| 640 | status = "disabled"; | |
| 641 | reg = <0x0 0x1f610000 0x0 0xd100>, | |
| 09c9e059 | 642 | <0x0 0x1f600000 0x0 0Xc300>, |
| 5fb32417 IS |
643 | <0x0 0x18000000 0x0 0X200>; |
| 644 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
| 645 | interrupts = <0x0 0x60 0x4>; | |
| 646 | dma-coherent; | |
| 647 | clocks = <&xge0clk 0>; | |
| 648 | /* mac address will be overwritten by the bootloader */ | |
| 649 | local-mac-address = [00 00 00 00 00 00]; | |
| 650 | phy-connection-type = "xgmii"; | |
| 651 | }; | |
| 652 | ||
| ab818739 FK |
653 | rng: rng@10520000 { |
| 654 | compatible = "apm,xgene-rng"; | |
| 655 | reg = <0x0 0x10520000 0x0 0x100>; | |
| 656 | interrupts = <0x0 0x41 0x4>; | |
| 657 | clocks = <&rngpkaclk 0>; | |
| 658 | }; | |
| ee877b53 VK |
659 | }; |
| 660 | }; |