Commit | Line | Data |
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ee877b53 VK |
1 | /* |
2 | * dts file for AppliedMicro (APM) X-Gene Storm SOC | |
3 | * | |
4 | * Copyright (C) 2013, Applied Micro Circuits Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | / { | |
13 | compatible = "apm,xgene-storm"; | |
14 | interrupt-parent = <&gic>; | |
15 | #address-cells = <2>; | |
16 | #size-cells = <2>; | |
17 | ||
18 | cpus { | |
19 | #address-cells = <2>; | |
20 | #size-cells = <0>; | |
21 | ||
22 | cpu@000 { | |
23 | device_type = "cpu"; | |
24 | compatible = "apm,potenza", "arm,armv8"; | |
25 | reg = <0x0 0x000>; | |
26 | enable-method = "spin-table"; | |
27 | cpu-release-addr = <0x1 0x0000fff8>; | |
28 | }; | |
29 | cpu@001 { | |
30 | device_type = "cpu"; | |
31 | compatible = "apm,potenza", "arm,armv8"; | |
32 | reg = <0x0 0x001>; | |
33 | enable-method = "spin-table"; | |
34 | cpu-release-addr = <0x1 0x0000fff8>; | |
35 | }; | |
36 | cpu@100 { | |
37 | device_type = "cpu"; | |
38 | compatible = "apm,potenza", "arm,armv8"; | |
39 | reg = <0x0 0x100>; | |
40 | enable-method = "spin-table"; | |
41 | cpu-release-addr = <0x1 0x0000fff8>; | |
42 | }; | |
43 | cpu@101 { | |
44 | device_type = "cpu"; | |
45 | compatible = "apm,potenza", "arm,armv8"; | |
46 | reg = <0x0 0x101>; | |
47 | enable-method = "spin-table"; | |
48 | cpu-release-addr = <0x1 0x0000fff8>; | |
49 | }; | |
50 | cpu@200 { | |
51 | device_type = "cpu"; | |
52 | compatible = "apm,potenza", "arm,armv8"; | |
53 | reg = <0x0 0x200>; | |
54 | enable-method = "spin-table"; | |
55 | cpu-release-addr = <0x1 0x0000fff8>; | |
56 | }; | |
57 | cpu@201 { | |
58 | device_type = "cpu"; | |
59 | compatible = "apm,potenza", "arm,armv8"; | |
60 | reg = <0x0 0x201>; | |
61 | enable-method = "spin-table"; | |
62 | cpu-release-addr = <0x1 0x0000fff8>; | |
63 | }; | |
64 | cpu@300 { | |
65 | device_type = "cpu"; | |
66 | compatible = "apm,potenza", "arm,armv8"; | |
67 | reg = <0x0 0x300>; | |
68 | enable-method = "spin-table"; | |
69 | cpu-release-addr = <0x1 0x0000fff8>; | |
70 | }; | |
71 | cpu@301 { | |
72 | device_type = "cpu"; | |
73 | compatible = "apm,potenza", "arm,armv8"; | |
74 | reg = <0x0 0x301>; | |
75 | enable-method = "spin-table"; | |
76 | cpu-release-addr = <0x1 0x0000fff8>; | |
77 | }; | |
78 | }; | |
79 | ||
80 | gic: interrupt-controller@78010000 { | |
81 | compatible = "arm,cortex-a15-gic"; | |
82 | #interrupt-cells = <3>; | |
83 | interrupt-controller; | |
84 | reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ | |
85 | <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ | |
86 | <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ | |
87 | <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ | |
88 | interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ | |
89 | }; | |
90 | ||
91 | timer { | |
92 | compatible = "arm,armv8-timer"; | |
93 | interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ | |
94 | <1 13 0xff01>, /* Non-secure Phys IRQ */ | |
95 | <1 14 0xff01>, /* Virt IRQ */ | |
96 | <1 15 0xff01>; /* Hyp IRQ */ | |
97 | clock-frequency = <50000000>; | |
98 | }; | |
99 | ||
7434f42b FK |
100 | pmu { |
101 | compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; | |
102 | interrupts = <1 12 0xff04>; | |
103 | }; | |
104 | ||
ee877b53 VK |
105 | soc { |
106 | compatible = "simple-bus"; | |
107 | #address-cells = <2>; | |
108 | #size-cells = <2>; | |
109 | ranges; | |
74e353e1 | 110 | dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; |
ee877b53 | 111 | |
3eb15d84 LH |
112 | clocks { |
113 | #address-cells = <2>; | |
114 | #size-cells = <2>; | |
115 | ranges; | |
116 | refclk: refclk { | |
117 | compatible = "fixed-clock"; | |
118 | #clock-cells = <1>; | |
119 | clock-frequency = <100000000>; | |
120 | clock-output-names = "refclk"; | |
121 | }; | |
122 | ||
123 | pcppll: pcppll@17000100 { | |
124 | compatible = "apm,xgene-pcppll-clock"; | |
125 | #clock-cells = <1>; | |
126 | clocks = <&refclk 0>; | |
127 | clock-names = "pcppll"; | |
128 | reg = <0x0 0x17000100 0x0 0x1000>; | |
129 | clock-output-names = "pcppll"; | |
130 | type = <0>; | |
131 | }; | |
132 | ||
133 | socpll: socpll@17000120 { | |
134 | compatible = "apm,xgene-socpll-clock"; | |
135 | #clock-cells = <1>; | |
136 | clocks = <&refclk 0>; | |
137 | clock-names = "socpll"; | |
138 | reg = <0x0 0x17000120 0x0 0x1000>; | |
139 | clock-output-names = "socpll"; | |
140 | type = <1>; | |
141 | }; | |
142 | ||
143 | socplldiv2: socplldiv2 { | |
144 | compatible = "fixed-factor-clock"; | |
145 | #clock-cells = <1>; | |
146 | clocks = <&socpll 0>; | |
147 | clock-names = "socplldiv2"; | |
148 | clock-mult = <1>; | |
149 | clock-div = <2>; | |
150 | clock-output-names = "socplldiv2"; | |
151 | }; | |
152 | ||
b0e7a85a | 153 | ahbclk: ahbclk@17000000 { |
8f74e861 ST |
154 | compatible = "apm,xgene-device-clock"; |
155 | #clock-cells = <1>; | |
156 | clocks = <&socplldiv2 0>; | |
b0e7a85a DD |
157 | reg = <0x0 0x17000000 0x0 0x2000>; |
158 | reg-names = "div-reg"; | |
8f74e861 ST |
159 | divider-offset = <0x164>; |
160 | divider-width = <0x5>; | |
161 | divider-shift = <0x0>; | |
162 | clock-output-names = "ahbclk"; | |
163 | }; | |
164 | ||
165 | sdioclk: sdioclk@1f2ac000 { | |
166 | compatible = "apm,xgene-device-clock"; | |
167 | #clock-cells = <1>; | |
168 | clocks = <&socplldiv2 0>; | |
169 | reg = <0x0 0x1f2ac000 0x0 0x1000 | |
170 | 0x0 0x17000000 0x0 0x2000>; | |
171 | reg-names = "csr-reg", "div-reg"; | |
172 | csr-offset = <0x0>; | |
173 | csr-mask = <0x2>; | |
174 | enable-offset = <0x8>; | |
175 | enable-mask = <0x2>; | |
176 | divider-offset = <0x178>; | |
177 | divider-width = <0x8>; | |
178 | divider-shift = <0x0>; | |
179 | clock-output-names = "sdioclk"; | |
180 | }; | |
181 | ||
3eb15d84 LH |
182 | qmlclk: qmlclk { |
183 | compatible = "apm,xgene-device-clock"; | |
184 | #clock-cells = <1>; | |
185 | clocks = <&socplldiv2 0>; | |
186 | clock-names = "qmlclk"; | |
187 | reg = <0x0 0x1703C000 0x0 0x1000>; | |
188 | reg-names = "csr-reg"; | |
189 | clock-output-names = "qmlclk"; | |
190 | }; | |
191 | ||
192 | ethclk: ethclk { | |
193 | compatible = "apm,xgene-device-clock"; | |
194 | #clock-cells = <1>; | |
195 | clocks = <&socplldiv2 0>; | |
196 | clock-names = "ethclk"; | |
197 | reg = <0x0 0x17000000 0x0 0x1000>; | |
198 | reg-names = "div-reg"; | |
199 | divider-offset = <0x238>; | |
200 | divider-width = <0x9>; | |
201 | divider-shift = <0x0>; | |
202 | clock-output-names = "ethclk"; | |
203 | }; | |
204 | ||
3d390425 | 205 | menetclk: menetclk { |
3eb15d84 LH |
206 | compatible = "apm,xgene-device-clock"; |
207 | #clock-cells = <1>; | |
208 | clocks = <ðclk 0>; | |
3eb15d84 LH |
209 | reg = <0x0 0x1702C000 0x0 0x1000>; |
210 | reg-names = "csr-reg"; | |
3d390425 | 211 | clock-output-names = "menetclk"; |
3eb15d84 | 212 | }; |
71b70ee9 | 213 | |
4c2e7f09 IS |
214 | sge0clk: sge0clk@1f21c000 { |
215 | compatible = "apm,xgene-device-clock"; | |
216 | #clock-cells = <1>; | |
217 | clocks = <&socplldiv2 0>; | |
218 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
219 | reg-names = "csr-reg"; | |
220 | csr-mask = <0x3>; | |
221 | clock-output-names = "sge0clk"; | |
222 | }; | |
223 | ||
2d33394e KC |
224 | sge1clk: sge1clk@1f21c000 { |
225 | compatible = "apm,xgene-device-clock"; | |
226 | #clock-cells = <1>; | |
227 | clocks = <&socplldiv2 0>; | |
228 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
229 | reg-names = "csr-reg"; | |
230 | csr-mask = <0xc>; | |
231 | clock-output-names = "sge1clk"; | |
232 | }; | |
233 | ||
5fb32417 IS |
234 | xge0clk: xge0clk@1f61c000 { |
235 | compatible = "apm,xgene-device-clock"; | |
236 | #clock-cells = <1>; | |
237 | clocks = <&socplldiv2 0>; | |
238 | reg = <0x0 0x1f61c000 0x0 0x1000>; | |
239 | reg-names = "csr-reg"; | |
240 | csr-mask = <0x3>; | |
241 | clock-output-names = "xge0clk"; | |
242 | }; | |
243 | ||
e63c7a09 IS |
244 | xge1clk: xge1clk@1f62c000 { |
245 | compatible = "apm,xgene-device-clock"; | |
246 | status = "disabled"; | |
247 | #clock-cells = <1>; | |
248 | clocks = <&socplldiv2 0>; | |
249 | reg = <0x0 0x1f62c000 0x0 0x1000>; | |
250 | reg-names = "csr-reg"; | |
251 | csr-mask = <0x3>; | |
252 | clock-output-names = "xge1clk"; | |
253 | }; | |
254 | ||
71b70ee9 LH |
255 | sataphy1clk: sataphy1clk@1f21c000 { |
256 | compatible = "apm,xgene-device-clock"; | |
257 | #clock-cells = <1>; | |
258 | clocks = <&socplldiv2 0>; | |
259 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
260 | reg-names = "csr-reg"; | |
261 | clock-output-names = "sataphy1clk"; | |
262 | status = "disabled"; | |
263 | csr-offset = <0x4>; | |
264 | csr-mask = <0x00>; | |
265 | enable-offset = <0x0>; | |
266 | enable-mask = <0x06>; | |
267 | }; | |
268 | ||
269 | sataphy2clk: sataphy1clk@1f22c000 { | |
270 | compatible = "apm,xgene-device-clock"; | |
271 | #clock-cells = <1>; | |
272 | clocks = <&socplldiv2 0>; | |
273 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
274 | reg-names = "csr-reg"; | |
275 | clock-output-names = "sataphy2clk"; | |
276 | status = "ok"; | |
277 | csr-offset = <0x4>; | |
278 | csr-mask = <0x3a>; | |
279 | enable-offset = <0x0>; | |
280 | enable-mask = <0x06>; | |
281 | }; | |
282 | ||
283 | sataphy3clk: sataphy1clk@1f23c000 { | |
284 | compatible = "apm,xgene-device-clock"; | |
285 | #clock-cells = <1>; | |
286 | clocks = <&socplldiv2 0>; | |
287 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
288 | reg-names = "csr-reg"; | |
289 | clock-output-names = "sataphy3clk"; | |
290 | status = "ok"; | |
291 | csr-offset = <0x4>; | |
292 | csr-mask = <0x3a>; | |
293 | enable-offset = <0x0>; | |
294 | enable-mask = <0x06>; | |
295 | }; | |
db8c0286 LH |
296 | |
297 | sata01clk: sata01clk@1f21c000 { | |
298 | compatible = "apm,xgene-device-clock"; | |
299 | #clock-cells = <1>; | |
300 | clocks = <&socplldiv2 0>; | |
301 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
302 | reg-names = "csr-reg"; | |
303 | clock-output-names = "sata01clk"; | |
304 | csr-offset = <0x4>; | |
305 | csr-mask = <0x05>; | |
306 | enable-offset = <0x0>; | |
307 | enable-mask = <0x39>; | |
308 | }; | |
309 | ||
310 | sata23clk: sata23clk@1f22c000 { | |
311 | compatible = "apm,xgene-device-clock"; | |
312 | #clock-cells = <1>; | |
313 | clocks = <&socplldiv2 0>; | |
314 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
315 | reg-names = "csr-reg"; | |
316 | clock-output-names = "sata23clk"; | |
317 | csr-offset = <0x4>; | |
318 | csr-mask = <0x05>; | |
319 | enable-offset = <0x0>; | |
320 | enable-mask = <0x39>; | |
321 | }; | |
322 | ||
323 | sata45clk: sata45clk@1f23c000 { | |
324 | compatible = "apm,xgene-device-clock"; | |
325 | #clock-cells = <1>; | |
326 | clocks = <&socplldiv2 0>; | |
327 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
328 | reg-names = "csr-reg"; | |
329 | clock-output-names = "sata45clk"; | |
330 | csr-offset = <0x4>; | |
331 | csr-mask = <0x05>; | |
332 | enable-offset = <0x0>; | |
333 | enable-mask = <0x39>; | |
334 | }; | |
652ba666 LH |
335 | |
336 | rtcclk: rtcclk@17000000 { | |
337 | compatible = "apm,xgene-device-clock"; | |
338 | #clock-cells = <1>; | |
339 | clocks = <&socplldiv2 0>; | |
340 | reg = <0x0 0x17000000 0x0 0x2000>; | |
341 | reg-names = "csr-reg"; | |
342 | csr-offset = <0xc>; | |
343 | csr-mask = <0x2>; | |
344 | enable-offset = <0x10>; | |
345 | enable-mask = <0x2>; | |
346 | clock-output-names = "rtcclk"; | |
347 | }; | |
ab818739 FK |
348 | |
349 | rngpkaclk: rngpkaclk@17000000 { | |
350 | compatible = "apm,xgene-device-clock"; | |
351 | #clock-cells = <1>; | |
352 | clocks = <&socplldiv2 0>; | |
353 | reg = <0x0 0x17000000 0x0 0x2000>; | |
354 | reg-names = "csr-reg"; | |
355 | csr-offset = <0xc>; | |
356 | csr-mask = <0x10>; | |
357 | enable-offset = <0x10>; | |
358 | enable-mask = <0x10>; | |
359 | clock-output-names = "rngpkaclk"; | |
360 | }; | |
80213c03 | 361 | |
767ebaff TI |
362 | pcie0clk: pcie0clk@1f2bc000 { |
363 | status = "disabled"; | |
364 | compatible = "apm,xgene-device-clock"; | |
365 | #clock-cells = <1>; | |
366 | clocks = <&socplldiv2 0>; | |
367 | reg = <0x0 0x1f2bc000 0x0 0x1000>; | |
368 | reg-names = "csr-reg"; | |
369 | clock-output-names = "pcie0clk"; | |
370 | }; | |
371 | ||
372 | pcie1clk: pcie1clk@1f2cc000 { | |
373 | status = "disabled"; | |
374 | compatible = "apm,xgene-device-clock"; | |
375 | #clock-cells = <1>; | |
376 | clocks = <&socplldiv2 0>; | |
377 | reg = <0x0 0x1f2cc000 0x0 0x1000>; | |
378 | reg-names = "csr-reg"; | |
379 | clock-output-names = "pcie1clk"; | |
380 | }; | |
381 | ||
382 | pcie2clk: pcie2clk@1f2dc000 { | |
383 | status = "disabled"; | |
384 | compatible = "apm,xgene-device-clock"; | |
385 | #clock-cells = <1>; | |
386 | clocks = <&socplldiv2 0>; | |
387 | reg = <0x0 0x1f2dc000 0x0 0x1000>; | |
388 | reg-names = "csr-reg"; | |
389 | clock-output-names = "pcie2clk"; | |
390 | }; | |
391 | ||
392 | pcie3clk: pcie3clk@1f50c000 { | |
393 | status = "disabled"; | |
394 | compatible = "apm,xgene-device-clock"; | |
395 | #clock-cells = <1>; | |
396 | clocks = <&socplldiv2 0>; | |
397 | reg = <0x0 0x1f50c000 0x0 0x1000>; | |
398 | reg-names = "csr-reg"; | |
399 | clock-output-names = "pcie3clk"; | |
400 | }; | |
401 | ||
402 | pcie4clk: pcie4clk@1f51c000 { | |
403 | status = "disabled"; | |
404 | compatible = "apm,xgene-device-clock"; | |
405 | #clock-cells = <1>; | |
406 | clocks = <&socplldiv2 0>; | |
407 | reg = <0x0 0x1f51c000 0x0 0x1000>; | |
408 | reg-names = "csr-reg"; | |
409 | clock-output-names = "pcie4clk"; | |
410 | }; | |
74e353e1 RPS |
411 | |
412 | dmaclk: dmaclk@1f27c000 { | |
413 | compatible = "apm,xgene-device-clock"; | |
414 | #clock-cells = <1>; | |
415 | clocks = <&socplldiv2 0>; | |
416 | reg = <0x0 0x1f27c000 0x0 0x1000>; | |
417 | reg-names = "csr-reg"; | |
418 | clock-output-names = "dmaclk"; | |
419 | }; | |
62ff9683 DD |
420 | |
421 | i2cclk: i2cclk@17000000 { | |
422 | status = "disabled"; | |
423 | compatible = "apm,xgene-device-clock"; | |
424 | #clock-cells = <1>; | |
425 | clocks = <&ahbclk 0>; | |
426 | reg = <0x0 0x17000000 0x0 0x2000>; | |
427 | reg-names = "csr-reg"; | |
428 | csr-offset = <0xc>; | |
429 | csr-mask = <0x4>; | |
430 | enable-offset = <0x10>; | |
431 | enable-mask = <0x4>; | |
432 | clock-output-names = "i2cclk"; | |
433 | }; | |
767ebaff TI |
434 | }; |
435 | ||
e1e6e5c4 DD |
436 | msi: msi@79000000 { |
437 | compatible = "apm,xgene1-msi"; | |
438 | msi-controller; | |
439 | reg = <0x00 0x79000000 0x0 0x900000>; | |
440 | interrupts = < 0x0 0x10 0x4 | |
441 | 0x0 0x11 0x4 | |
442 | 0x0 0x12 0x4 | |
443 | 0x0 0x13 0x4 | |
444 | 0x0 0x14 0x4 | |
445 | 0x0 0x15 0x4 | |
446 | 0x0 0x16 0x4 | |
447 | 0x0 0x17 0x4 | |
448 | 0x0 0x18 0x4 | |
449 | 0x0 0x19 0x4 | |
450 | 0x0 0x1a 0x4 | |
451 | 0x0 0x1b 0x4 | |
452 | 0x0 0x1c 0x4 | |
453 | 0x0 0x1d 0x4 | |
454 | 0x0 0x1e 0x4 | |
455 | 0x0 0x1f 0x4>; | |
456 | }; | |
457 | ||
5c3a87e3 FK |
458 | scu: system-clk-controller@17000000 { |
459 | compatible = "apm,xgene-scu","syscon"; | |
460 | reg = <0x0 0x17000000 0x0 0x400>; | |
461 | }; | |
462 | ||
463 | reboot: reboot@17000014 { | |
464 | compatible = "syscon-reboot"; | |
465 | regmap = <&scu>; | |
466 | offset = <0x14>; | |
467 | mask = <0x1>; | |
468 | }; | |
469 | ||
8f2ae6f3 LH |
470 | csw: csw@7e200000 { |
471 | compatible = "apm,xgene-csw", "syscon"; | |
472 | reg = <0x0 0x7e200000 0x0 0x1000>; | |
473 | }; | |
474 | ||
475 | mcba: mcba@7e700000 { | |
476 | compatible = "apm,xgene-mcb", "syscon"; | |
477 | reg = <0x0 0x7e700000 0x0 0x1000>; | |
478 | }; | |
479 | ||
480 | mcbb: mcbb@7e720000 { | |
481 | compatible = "apm,xgene-mcb", "syscon"; | |
482 | reg = <0x0 0x7e720000 0x0 0x1000>; | |
483 | }; | |
484 | ||
485 | efuse: efuse@1054a000 { | |
486 | compatible = "apm,xgene-efuse", "syscon"; | |
487 | reg = <0x0 0x1054a000 0x0 0x20>; | |
488 | }; | |
489 | ||
490 | edac@78800000 { | |
491 | compatible = "apm,xgene-edac"; | |
492 | #address-cells = <2>; | |
493 | #size-cells = <2>; | |
494 | ranges; | |
495 | regmap-csw = <&csw>; | |
496 | regmap-mcba = <&mcba>; | |
497 | regmap-mcbb = <&mcbb>; | |
498 | regmap-efuse = <&efuse>; | |
499 | reg = <0x0 0x78800000 0x0 0x100>; | |
500 | interrupts = <0x0 0x20 0x4>, | |
501 | <0x0 0x21 0x4>, | |
502 | <0x0 0x27 0x4>; | |
503 | ||
504 | edacmc@7e800000 { | |
505 | compatible = "apm,xgene-edac-mc"; | |
506 | reg = <0x0 0x7e800000 0x0 0x1000>; | |
507 | memory-controller = <0>; | |
508 | }; | |
509 | ||
510 | edacmc@7e840000 { | |
511 | compatible = "apm,xgene-edac-mc"; | |
512 | reg = <0x0 0x7e840000 0x0 0x1000>; | |
513 | memory-controller = <1>; | |
514 | }; | |
515 | ||
516 | edacmc@7e880000 { | |
517 | compatible = "apm,xgene-edac-mc"; | |
518 | reg = <0x0 0x7e880000 0x0 0x1000>; | |
519 | memory-controller = <2>; | |
520 | }; | |
521 | ||
522 | edacmc@7e8c0000 { | |
523 | compatible = "apm,xgene-edac-mc"; | |
524 | reg = <0x0 0x7e8c0000 0x0 0x1000>; | |
525 | memory-controller = <3>; | |
526 | }; | |
527 | ||
528 | edacpmd@7c000000 { | |
529 | compatible = "apm,xgene-edac-pmd"; | |
530 | reg = <0x0 0x7c000000 0x0 0x200000>; | |
531 | pmd-controller = <0>; | |
532 | }; | |
533 | ||
534 | edacpmd@7c200000 { | |
535 | compatible = "apm,xgene-edac-pmd"; | |
536 | reg = <0x0 0x7c200000 0x0 0x200000>; | |
537 | pmd-controller = <1>; | |
538 | }; | |
539 | ||
540 | edacpmd@7c400000 { | |
541 | compatible = "apm,xgene-edac-pmd"; | |
542 | reg = <0x0 0x7c400000 0x0 0x200000>; | |
543 | pmd-controller = <2>; | |
544 | }; | |
545 | ||
546 | edacpmd@7c600000 { | |
547 | compatible = "apm,xgene-edac-pmd"; | |
548 | reg = <0x0 0x7c600000 0x0 0x200000>; | |
549 | pmd-controller = <3>; | |
550 | }; | |
043cba96 LH |
551 | |
552 | edacl3@7e600000 { | |
553 | compatible = "apm,xgene-edac-l3"; | |
554 | reg = <0x0 0x7e600000 0x0 0x1000>; | |
555 | }; | |
556 | ||
557 | edacsoc@7e930000 { | |
558 | compatible = "apm,xgene-edac-soc-v1"; | |
559 | reg = <0x0 0x7e930000 0x0 0x1000>; | |
560 | }; | |
8f2ae6f3 LH |
561 | }; |
562 | ||
767ebaff TI |
563 | pcie0: pcie@1f2b0000 { |
564 | status = "disabled"; | |
565 | device_type = "pci"; | |
566 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
567 | #interrupt-cells = <1>; | |
568 | #size-cells = <2>; | |
569 | #address-cells = <3>; | |
570 | reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ | |
571 | 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
572 | reg-names = "csr", "cfg"; | |
573 | ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ | |
80bb3eda DD |
574 | 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ |
575 | 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ | |
767ebaff TI |
576 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
577 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
578 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
579 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 | |
580 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 | |
581 | 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 | |
582 | 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; | |
583 | dma-coherent; | |
584 | clocks = <&pcie0clk 0>; | |
e1e6e5c4 | 585 | msi-parent = <&msi>; |
767ebaff TI |
586 | }; |
587 | ||
588 | pcie1: pcie@1f2c0000 { | |
589 | status = "disabled"; | |
590 | device_type = "pci"; | |
591 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
592 | #interrupt-cells = <1>; | |
593 | #size-cells = <2>; | |
594 | #address-cells = <3>; | |
595 | reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ | |
596 | 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
597 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
598 | ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ |
599 | 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ | |
600 | 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ | |
767ebaff TI |
601 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
602 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
603 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
604 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 | |
605 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 | |
606 | 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 | |
607 | 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; | |
608 | dma-coherent; | |
609 | clocks = <&pcie1clk 0>; | |
e1e6e5c4 | 610 | msi-parent = <&msi>; |
767ebaff TI |
611 | }; |
612 | ||
613 | pcie2: pcie@1f2d0000 { | |
614 | status = "disabled"; | |
615 | device_type = "pci"; | |
616 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
617 | #interrupt-cells = <1>; | |
618 | #size-cells = <2>; | |
619 | #address-cells = <3>; | |
620 | reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ | |
621 | 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
622 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
623 | ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ |
624 | 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ | |
625 | 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ | |
767ebaff TI |
626 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
627 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
628 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
629 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 | |
630 | 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 | |
631 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 | |
632 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; | |
633 | dma-coherent; | |
634 | clocks = <&pcie2clk 0>; | |
e1e6e5c4 | 635 | msi-parent = <&msi>; |
767ebaff TI |
636 | }; |
637 | ||
638 | pcie3: pcie@1f500000 { | |
639 | status = "disabled"; | |
640 | device_type = "pci"; | |
641 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
642 | #interrupt-cells = <1>; | |
643 | #size-cells = <2>; | |
644 | #address-cells = <3>; | |
645 | reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ | |
646 | 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
647 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
648 | ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ |
649 | 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ | |
650 | 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ | |
767ebaff TI |
651 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
652 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
653 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
654 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 | |
655 | 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 | |
656 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 | |
657 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; | |
658 | dma-coherent; | |
659 | clocks = <&pcie3clk 0>; | |
e1e6e5c4 | 660 | msi-parent = <&msi>; |
767ebaff TI |
661 | }; |
662 | ||
663 | pcie4: pcie@1f510000 { | |
664 | status = "disabled"; | |
665 | device_type = "pci"; | |
666 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
667 | #interrupt-cells = <1>; | |
668 | #size-cells = <2>; | |
669 | #address-cells = <3>; | |
670 | reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ | |
671 | 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ | |
672 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
673 | ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ |
674 | 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ | |
675 | 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ | |
767ebaff TI |
676 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
677 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
678 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
679 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 | |
680 | 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 | |
681 | 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 | |
682 | 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; | |
683 | dma-coherent; | |
684 | clocks = <&pcie4clk 0>; | |
e1e6e5c4 | 685 | msi-parent = <&msi>; |
3eb15d84 LH |
686 | }; |
687 | ||
ee877b53 | 688 | serial0: serial@1c020000 { |
457ced84 | 689 | status = "disabled"; |
ee877b53 | 690 | device_type = "serial"; |
457ced84 | 691 | compatible = "ns16550a"; |
ee877b53 VK |
692 | reg = <0 0x1c020000 0x0 0x1000>; |
693 | reg-shift = <2>; | |
694 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
695 | interrupt-parent = <&gic>; | |
696 | interrupts = <0x0 0x4c 0x4>; | |
697 | }; | |
71b70ee9 | 698 | |
457ced84 VK |
699 | serial1: serial@1c021000 { |
700 | status = "disabled"; | |
701 | device_type = "serial"; | |
702 | compatible = "ns16550a"; | |
703 | reg = <0 0x1c021000 0x0 0x1000>; | |
704 | reg-shift = <2>; | |
705 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
706 | interrupt-parent = <&gic>; | |
707 | interrupts = <0x0 0x4d 0x4>; | |
708 | }; | |
709 | ||
710 | serial2: serial@1c022000 { | |
711 | status = "disabled"; | |
712 | device_type = "serial"; | |
713 | compatible = "ns16550a"; | |
714 | reg = <0 0x1c022000 0x0 0x1000>; | |
715 | reg-shift = <2>; | |
716 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
717 | interrupt-parent = <&gic>; | |
718 | interrupts = <0x0 0x4e 0x4>; | |
719 | }; | |
720 | ||
721 | serial3: serial@1c023000 { | |
722 | status = "disabled"; | |
723 | device_type = "serial"; | |
724 | compatible = "ns16550a"; | |
725 | reg = <0 0x1c023000 0x0 0x1000>; | |
726 | reg-shift = <2>; | |
727 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
728 | interrupt-parent = <&gic>; | |
729 | interrupts = <0x0 0x4f 0x4>; | |
730 | }; | |
731 | ||
8f74e861 ST |
732 | mmc0: mmc@1c000000 { |
733 | compatible = "arasan,sdhci-4.9a"; | |
734 | reg = <0x0 0x1c000000 0x0 0x100>; | |
735 | interrupts = <0x0 0x49 0x4>; | |
736 | dma-coherent; | |
737 | no-1-8-v; | |
738 | clock-names = "clk_xin", "clk_ahb"; | |
739 | clocks = <&sdioclk 0>, <&ahbclk 0>; | |
740 | }; | |
741 | ||
0a09223f DD |
742 | gfcgpio: gfcgpio0@1701c000 { |
743 | compatible = "apm,xgene-gpio"; | |
744 | reg = <0x0 0x1701c000 0x0 0x40>; | |
745 | gpio-controller; | |
746 | #gpio-cells = <2>; | |
747 | }; | |
748 | ||
e38ec5b9 DD |
749 | dwgpio: dwgpio@1c024000 { |
750 | compatible = "snps,dw-apb-gpio"; | |
751 | reg = <0x0 0x1c024000 0x0 0x1000>; | |
752 | reg-io-width = <4>; | |
753 | #address-cells = <1>; | |
754 | #size-cells = <0>; | |
755 | ||
756 | porta: gpio-controller@0 { | |
757 | compatible = "snps,dw-apb-gpio-port"; | |
758 | gpio-controller; | |
759 | snps,nr-gpios = <32>; | |
760 | reg = <0>; | |
761 | }; | |
762 | }; | |
763 | ||
62ff9683 DD |
764 | i2c0: i2c0@10512000 { |
765 | status = "disabled"; | |
766 | #address-cells = <1>; | |
767 | #size-cells = <0>; | |
768 | compatible = "snps,designware-i2c"; | |
769 | reg = <0x0 0x10512000 0x0 0x1000>; | |
770 | interrupts = <0 0x44 0x4>; | |
771 | #clock-cells = <1>; | |
772 | clocks = <&i2cclk 0>; | |
773 | bus_num = <0>; | |
774 | }; | |
775 | ||
71b70ee9 LH |
776 | phy1: phy@1f21a000 { |
777 | compatible = "apm,xgene-phy"; | |
778 | reg = <0x0 0x1f21a000 0x0 0x100>; | |
779 | #phy-cells = <1>; | |
780 | clocks = <&sataphy1clk 0>; | |
781 | status = "disabled"; | |
782 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
783 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
784 | }; | |
785 | ||
786 | phy2: phy@1f22a000 { | |
787 | compatible = "apm,xgene-phy"; | |
788 | reg = <0x0 0x1f22a000 0x0 0x100>; | |
789 | #phy-cells = <1>; | |
790 | clocks = <&sataphy2clk 0>; | |
791 | status = "ok"; | |
792 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
793 | apm,tx-eye-tuning = <1 10 10 2 10 10>; | |
794 | }; | |
795 | ||
796 | phy3: phy@1f23a000 { | |
797 | compatible = "apm,xgene-phy"; | |
798 | reg = <0x0 0x1f23a000 0x0 0x100>; | |
799 | #phy-cells = <1>; | |
800 | clocks = <&sataphy3clk 0>; | |
801 | status = "ok"; | |
802 | apm,tx-boost-gain = <31 31 31 31 31 31>; | |
803 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
804 | }; | |
db8c0286 LH |
805 | |
806 | sata1: sata@1a000000 { | |
807 | compatible = "apm,xgene-ahci"; | |
808 | reg = <0x0 0x1a000000 0x0 0x1000>, | |
809 | <0x0 0x1f210000 0x0 0x1000>, | |
810 | <0x0 0x1f21d000 0x0 0x1000>, | |
811 | <0x0 0x1f21e000 0x0 0x1000>, | |
812 | <0x0 0x1f217000 0x0 0x1000>; | |
813 | interrupts = <0x0 0x86 0x4>; | |
7a8d1ec1 | 814 | dma-coherent; |
db8c0286 LH |
815 | status = "disabled"; |
816 | clocks = <&sata01clk 0>; | |
817 | phys = <&phy1 0>; | |
818 | phy-names = "sata-phy"; | |
819 | }; | |
820 | ||
821 | sata2: sata@1a400000 { | |
822 | compatible = "apm,xgene-ahci"; | |
823 | reg = <0x0 0x1a400000 0x0 0x1000>, | |
824 | <0x0 0x1f220000 0x0 0x1000>, | |
825 | <0x0 0x1f22d000 0x0 0x1000>, | |
826 | <0x0 0x1f22e000 0x0 0x1000>, | |
827 | <0x0 0x1f227000 0x0 0x1000>; | |
828 | interrupts = <0x0 0x87 0x4>; | |
7a8d1ec1 | 829 | dma-coherent; |
db8c0286 LH |
830 | status = "ok"; |
831 | clocks = <&sata23clk 0>; | |
832 | phys = <&phy2 0>; | |
833 | phy-names = "sata-phy"; | |
834 | }; | |
835 | ||
836 | sata3: sata@1a800000 { | |
837 | compatible = "apm,xgene-ahci"; | |
838 | reg = <0x0 0x1a800000 0x0 0x1000>, | |
839 | <0x0 0x1f230000 0x0 0x1000>, | |
840 | <0x0 0x1f23d000 0x0 0x1000>, | |
841 | <0x0 0x1f23e000 0x0 0x1000>; | |
842 | interrupts = <0x0 0x88 0x4>; | |
7a8d1ec1 | 843 | dma-coherent; |
db8c0286 LH |
844 | status = "ok"; |
845 | clocks = <&sata45clk 0>; | |
846 | phys = <&phy3 0>; | |
847 | phy-names = "sata-phy"; | |
848 | }; | |
652ba666 | 849 | |
bd410233 DD |
850 | /* Do not change dwusb name, coded for backward compatibility */ |
851 | usb0: dwusb@19000000 { | |
852 | status = "disabled"; | |
853 | compatible = "snps,dwc3"; | |
854 | reg = <0x0 0x19000000 0x0 0x100000>; | |
855 | interrupts = <0x0 0x89 0x4>; | |
856 | dma-coherent; | |
857 | dr_mode = "host"; | |
858 | }; | |
859 | ||
860 | usb1: dwusb@19800000 { | |
861 | status = "disabled"; | |
862 | compatible = "snps,dwc3"; | |
863 | reg = <0x0 0x19800000 0x0 0x100000>; | |
864 | interrupts = <0x0 0x8a 0x4>; | |
865 | dma-coherent; | |
866 | dr_mode = "host"; | |
867 | }; | |
868 | ||
ea21feb3 V |
869 | sbgpio: sbgpio@17001000{ |
870 | compatible = "apm,xgene-gpio-sb"; | |
871 | reg = <0x0 0x17001000 0x0 0x400>; | |
872 | #gpio-cells = <2>; | |
873 | gpio-controller; | |
874 | interrupts = <0x0 0x28 0x1>, | |
875 | <0x0 0x29 0x1>, | |
876 | <0x0 0x2a 0x1>, | |
877 | <0x0 0x2b 0x1>, | |
878 | <0x0 0x2c 0x1>, | |
879 | <0x0 0x2d 0x1>; | |
880 | }; | |
881 | ||
652ba666 LH |
882 | rtc: rtc@10510000 { |
883 | compatible = "apm,xgene-rtc"; | |
884 | reg = <0x0 0x10510000 0x0 0x400>; | |
885 | interrupts = <0x0 0x46 0x4>; | |
886 | #clock-cells = <1>; | |
887 | clocks = <&rtcclk 0>; | |
888 | }; | |
3d390425 IS |
889 | |
890 | menet: ethernet@17020000 { | |
891 | compatible = "apm,xgene-enet"; | |
892 | status = "disabled"; | |
893 | reg = <0x0 0x17020000 0x0 0xd100>, | |
09c9e059 | 894 | <0x0 0X17030000 0x0 0Xc300>, |
3d390425 IS |
895 | <0x0 0X10000000 0x0 0X200>; |
896 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
897 | interrupts = <0x0 0x3c 0x4>; | |
898 | dma-coherent; | |
899 | clocks = <&menetclk 0>; | |
5fb32417 IS |
900 | /* mac address will be overwritten by the bootloader */ |
901 | local-mac-address = [00 00 00 00 00 00]; | |
3d390425 IS |
902 | phy-connection-type = "rgmii"; |
903 | phy-handle = <&menetphy>; | |
904 | mdio { | |
905 | compatible = "apm,xgene-mdio"; | |
906 | #address-cells = <1>; | |
907 | #size-cells = <0>; | |
908 | menetphy: menetphy@3 { | |
909 | compatible = "ethernet-phy-id001c.c915"; | |
910 | reg = <0x3>; | |
911 | }; | |
912 | ||
913 | }; | |
914 | }; | |
ab818739 | 915 | |
4c2e7f09 | 916 | sgenet0: ethernet@1f210000 { |
2a91eb72 | 917 | compatible = "apm,xgene1-sgenet"; |
4c2e7f09 | 918 | status = "disabled"; |
09c9e059 IS |
919 | reg = <0x0 0x1f210000 0x0 0xd100>, |
920 | <0x0 0x1f200000 0x0 0Xc300>, | |
921 | <0x0 0x1B000000 0x0 0X200>; | |
4c2e7f09 | 922 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
d3134649 IS |
923 | interrupts = <0x0 0xA0 0x4>, |
924 | <0x0 0xA1 0x4>; | |
4c2e7f09 IS |
925 | dma-coherent; |
926 | clocks = <&sge0clk 0>; | |
927 | local-mac-address = [00 00 00 00 00 00]; | |
928 | phy-connection-type = "sgmii"; | |
929 | }; | |
930 | ||
2d33394e KC |
931 | sgenet1: ethernet@1f210030 { |
932 | compatible = "apm,xgene1-sgenet"; | |
933 | status = "disabled"; | |
934 | reg = <0x0 0x1f210030 0x0 0xd100>, | |
935 | <0x0 0x1f200000 0x0 0Xc300>, | |
936 | <0x0 0x1B000000 0x0 0X8000>; | |
937 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
d3134649 IS |
938 | interrupts = <0x0 0xAC 0x4>, |
939 | <0x0 0xAD 0x4>; | |
2d33394e KC |
940 | port-id = <1>; |
941 | dma-coherent; | |
942 | clocks = <&sge1clk 0>; | |
943 | local-mac-address = [00 00 00 00 00 00]; | |
944 | phy-connection-type = "sgmii"; | |
945 | }; | |
946 | ||
5fb32417 | 947 | xgenet: ethernet@1f610000 { |
2a91eb72 | 948 | compatible = "apm,xgene1-xgenet"; |
5fb32417 IS |
949 | status = "disabled"; |
950 | reg = <0x0 0x1f610000 0x0 0xd100>, | |
09c9e059 | 951 | <0x0 0x1f600000 0x0 0Xc300>, |
5fb32417 IS |
952 | <0x0 0x18000000 0x0 0X200>; |
953 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
d3134649 IS |
954 | interrupts = <0x0 0x60 0x4>, |
955 | <0x0 0x61 0x4>; | |
5fb32417 IS |
956 | dma-coherent; |
957 | clocks = <&xge0clk 0>; | |
958 | /* mac address will be overwritten by the bootloader */ | |
959 | local-mac-address = [00 00 00 00 00 00]; | |
960 | phy-connection-type = "xgmii"; | |
961 | }; | |
962 | ||
e63c7a09 IS |
963 | xgenet1: ethernet@1f620000 { |
964 | compatible = "apm,xgene1-xgenet"; | |
965 | status = "disabled"; | |
966 | reg = <0x0 0x1f620000 0x0 0xd100>, | |
967 | <0x0 0x1f600000 0x0 0Xc300>, | |
968 | <0x0 0x18000000 0x0 0X8000>; | |
969 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
970 | interrupts = <0x0 0x6C 0x4>, | |
971 | <0x0 0x6D 0x4>; | |
972 | port-id = <1>; | |
973 | dma-coherent; | |
974 | clocks = <&xge1clk 0>; | |
975 | /* mac address will be overwritten by the bootloader */ | |
976 | local-mac-address = [00 00 00 00 00 00]; | |
977 | phy-connection-type = "xgmii"; | |
978 | }; | |
979 | ||
ab818739 FK |
980 | rng: rng@10520000 { |
981 | compatible = "apm,xgene-rng"; | |
982 | reg = <0x0 0x10520000 0x0 0x100>; | |
983 | interrupts = <0x0 0x41 0x4>; | |
984 | clocks = <&rngpkaclk 0>; | |
985 | }; | |
74e353e1 RPS |
986 | |
987 | dma: dma@1f270000 { | |
988 | compatible = "apm,xgene-storm-dma"; | |
989 | device_type = "dma"; | |
990 | reg = <0x0 0x1f270000 0x0 0x10000>, | |
991 | <0x0 0x1f200000 0x0 0x10000>, | |
cda8e937 | 992 | <0x0 0x1b000000 0x0 0x400000>, |
74e353e1 RPS |
993 | <0x0 0x1054a000 0x0 0x100>; |
994 | interrupts = <0x0 0x82 0x4>, | |
995 | <0x0 0xb8 0x4>, | |
996 | <0x0 0xb9 0x4>, | |
997 | <0x0 0xba 0x4>, | |
998 | <0x0 0xbb 0x4>; | |
999 | dma-coherent; | |
1000 | clocks = <&dmaclk 0>; | |
1001 | }; | |
ee877b53 VK |
1002 | }; |
1003 | }; |