projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| ee877b53 VK |
1 | /* |
| 2 | * dts file for AppliedMicro (APM) X-Gene Storm SOC | |
| 3 | * | |
| 4 | * Copyright (C) 2013, Applied Micro Circuits Corporation | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation; either version 2 of | |
| 9 | * the License, or (at your option) any later version. | |
| 10 | */ | |
| 11 | ||
| 12 | / { | |
| 13 | compatible = "apm,xgene-storm"; | |
| 14 | interrupt-parent = <&gic>; | |
| 15 | #address-cells = <2>; | |
| 16 | #size-cells = <2>; | |
| 17 | ||
| 18 | cpus { | |
| 19 | #address-cells = <2>; | |
| 20 | #size-cells = <0>; | |
| 21 | ||
| 22 | cpu@000 { | |
| 23 | device_type = "cpu"; | |
| 24 | compatible = "apm,potenza", "arm,armv8"; | |
| 25 | reg = <0x0 0x000>; | |
| 26 | enable-method = "spin-table"; | |
| 27 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 28 | }; | |
| 29 | cpu@001 { | |
| 30 | device_type = "cpu"; | |
| 31 | compatible = "apm,potenza", "arm,armv8"; | |
| 32 | reg = <0x0 0x001>; | |
| 33 | enable-method = "spin-table"; | |
| 34 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 35 | }; | |
| 36 | cpu@100 { | |
| 37 | device_type = "cpu"; | |
| 38 | compatible = "apm,potenza", "arm,armv8"; | |
| 39 | reg = <0x0 0x100>; | |
| 40 | enable-method = "spin-table"; | |
| 41 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 42 | }; | |
| 43 | cpu@101 { | |
| 44 | device_type = "cpu"; | |
| 45 | compatible = "apm,potenza", "arm,armv8"; | |
| 46 | reg = <0x0 0x101>; | |
| 47 | enable-method = "spin-table"; | |
| 48 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 49 | }; | |
| 50 | cpu@200 { | |
| 51 | device_type = "cpu"; | |
| 52 | compatible = "apm,potenza", "arm,armv8"; | |
| 53 | reg = <0x0 0x200>; | |
| 54 | enable-method = "spin-table"; | |
| 55 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 56 | }; | |
| 57 | cpu@201 { | |
| 58 | device_type = "cpu"; | |
| 59 | compatible = "apm,potenza", "arm,armv8"; | |
| 60 | reg = <0x0 0x201>; | |
| 61 | enable-method = "spin-table"; | |
| 62 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 63 | }; | |
| 64 | cpu@300 { | |
| 65 | device_type = "cpu"; | |
| 66 | compatible = "apm,potenza", "arm,armv8"; | |
| 67 | reg = <0x0 0x300>; | |
| 68 | enable-method = "spin-table"; | |
| 69 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 70 | }; | |
| 71 | cpu@301 { | |
| 72 | device_type = "cpu"; | |
| 73 | compatible = "apm,potenza", "arm,armv8"; | |
| 74 | reg = <0x0 0x301>; | |
| 75 | enable-method = "spin-table"; | |
| 76 | cpu-release-addr = <0x1 0x0000fff8>; | |
| 77 | }; | |
| 78 | }; | |
| 79 | ||
| 80 | gic: interrupt-controller@78010000 { | |
| 81 | compatible = "arm,cortex-a15-gic"; | |
| 82 | #interrupt-cells = <3>; | |
| 83 | interrupt-controller; | |
| 84 | reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ | |
| 85 | <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ | |
| 86 | <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ | |
| 87 | <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ | |
| 88 | interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ | |
| 89 | }; | |
| 90 | ||
| 91 | timer { | |
| 92 | compatible = "arm,armv8-timer"; | |
| 93 | interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ | |
| 94 | <1 13 0xff01>, /* Non-secure Phys IRQ */ | |
| 95 | <1 14 0xff01>, /* Virt IRQ */ | |
| 96 | <1 15 0xff01>; /* Hyp IRQ */ | |
| 97 | clock-frequency = <50000000>; | |
| 98 | }; | |
| 99 | ||
| 100 | soc { | |
| 101 | compatible = "simple-bus"; | |
| 102 | #address-cells = <2>; | |
| 103 | #size-cells = <2>; | |
| 104 | ranges; | |
| 74e353e1 | 105 | dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; |
| ee877b53 | 106 | |
| 3eb15d84 LH |
107 | clocks { |
| 108 | #address-cells = <2>; | |
| 109 | #size-cells = <2>; | |
| 110 | ranges; | |
| 111 | refclk: refclk { | |
| 112 | compatible = "fixed-clock"; | |
| 113 | #clock-cells = <1>; | |
| 114 | clock-frequency = <100000000>; | |
| 115 | clock-output-names = "refclk"; | |
| 116 | }; | |
| 117 | ||
| 118 | pcppll: pcppll@17000100 { | |
| 119 | compatible = "apm,xgene-pcppll-clock"; | |
| 120 | #clock-cells = <1>; | |
| 121 | clocks = <&refclk 0>; | |
| 122 | clock-names = "pcppll"; | |
| 123 | reg = <0x0 0x17000100 0x0 0x1000>; | |
| 124 | clock-output-names = "pcppll"; | |
| 125 | type = <0>; | |
| 126 | }; | |
| 127 | ||
| 128 | socpll: socpll@17000120 { | |
| 129 | compatible = "apm,xgene-socpll-clock"; | |
| 130 | #clock-cells = <1>; | |
| 131 | clocks = <&refclk 0>; | |
| 132 | clock-names = "socpll"; | |
| 133 | reg = <0x0 0x17000120 0x0 0x1000>; | |
| 134 | clock-output-names = "socpll"; | |
| 135 | type = <1>; | |
| 136 | }; | |
| 137 | ||
| 138 | socplldiv2: socplldiv2 { | |
| 139 | compatible = "fixed-factor-clock"; | |
| 140 | #clock-cells = <1>; | |
| 141 | clocks = <&socpll 0>; | |
| 142 | clock-names = "socplldiv2"; | |
| 143 | clock-mult = <1>; | |
| 144 | clock-div = <2>; | |
| 145 | clock-output-names = "socplldiv2"; | |
| 146 | }; | |
| 147 | ||
| 148 | qmlclk: qmlclk { | |
| 149 | compatible = "apm,xgene-device-clock"; | |
| 150 | #clock-cells = <1>; | |
| 151 | clocks = <&socplldiv2 0>; | |
| 152 | clock-names = "qmlclk"; | |
| 153 | reg = <0x0 0x1703C000 0x0 0x1000>; | |
| 154 | reg-names = "csr-reg"; | |
| 155 | clock-output-names = "qmlclk"; | |
| 156 | }; | |
| 157 | ||
| 158 | ethclk: ethclk { | |
| 159 | compatible = "apm,xgene-device-clock"; | |
| 160 | #clock-cells = <1>; | |
| 161 | clocks = <&socplldiv2 0>; | |
| 162 | clock-names = "ethclk"; | |
| 163 | reg = <0x0 0x17000000 0x0 0x1000>; | |
| 164 | reg-names = "div-reg"; | |
| 165 | divider-offset = <0x238>; | |
| 166 | divider-width = <0x9>; | |
| 167 | divider-shift = <0x0>; | |
| 168 | clock-output-names = "ethclk"; | |
| 169 | }; | |
| 170 | ||
| 3d390425 | 171 | menetclk: menetclk { |
| 3eb15d84 LH |
172 | compatible = "apm,xgene-device-clock"; |
| 173 | #clock-cells = <1>; | |
| 174 | clocks = <ðclk 0>; | |
| 3eb15d84 LH |
175 | reg = <0x0 0x1702C000 0x0 0x1000>; |
| 176 | reg-names = "csr-reg"; | |
| 3d390425 | 177 | clock-output-names = "menetclk"; |
| 3eb15d84 | 178 | }; |
| 71b70ee9 | 179 | |
| 4c2e7f09 IS |
180 | sge0clk: sge0clk@1f21c000 { |
| 181 | compatible = "apm,xgene-device-clock"; | |
| 182 | #clock-cells = <1>; | |
| 183 | clocks = <&socplldiv2 0>; | |
| 184 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 185 | reg-names = "csr-reg"; | |
| 186 | csr-mask = <0x3>; | |
| 187 | clock-output-names = "sge0clk"; | |
| 188 | }; | |
| 189 | ||
| 2d33394e KC |
190 | sge1clk: sge1clk@1f21c000 { |
| 191 | compatible = "apm,xgene-device-clock"; | |
| 192 | #clock-cells = <1>; | |
| 193 | clocks = <&socplldiv2 0>; | |
| 194 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 195 | reg-names = "csr-reg"; | |
| 196 | csr-mask = <0xc>; | |
| 197 | clock-output-names = "sge1clk"; | |
| 198 | }; | |
| 199 | ||
| 5fb32417 IS |
200 | xge0clk: xge0clk@1f61c000 { |
| 201 | compatible = "apm,xgene-device-clock"; | |
| 202 | #clock-cells = <1>; | |
| 203 | clocks = <&socplldiv2 0>; | |
| 204 | reg = <0x0 0x1f61c000 0x0 0x1000>; | |
| 205 | reg-names = "csr-reg"; | |
| 206 | csr-mask = <0x3>; | |
| 207 | clock-output-names = "xge0clk"; | |
| 208 | }; | |
| 209 | ||
| 71b70ee9 LH |
210 | sataphy1clk: sataphy1clk@1f21c000 { |
| 211 | compatible = "apm,xgene-device-clock"; | |
| 212 | #clock-cells = <1>; | |
| 213 | clocks = <&socplldiv2 0>; | |
| 214 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 215 | reg-names = "csr-reg"; | |
| 216 | clock-output-names = "sataphy1clk"; | |
| 217 | status = "disabled"; | |
| 218 | csr-offset = <0x4>; | |
| 219 | csr-mask = <0x00>; | |
| 220 | enable-offset = <0x0>; | |
| 221 | enable-mask = <0x06>; | |
| 222 | }; | |
| 223 | ||
| 224 | sataphy2clk: sataphy1clk@1f22c000 { | |
| 225 | compatible = "apm,xgene-device-clock"; | |
| 226 | #clock-cells = <1>; | |
| 227 | clocks = <&socplldiv2 0>; | |
| 228 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
| 229 | reg-names = "csr-reg"; | |
| 230 | clock-output-names = "sataphy2clk"; | |
| 231 | status = "ok"; | |
| 232 | csr-offset = <0x4>; | |
| 233 | csr-mask = <0x3a>; | |
| 234 | enable-offset = <0x0>; | |
| 235 | enable-mask = <0x06>; | |
| 236 | }; | |
| 237 | ||
| 238 | sataphy3clk: sataphy1clk@1f23c000 { | |
| 239 | compatible = "apm,xgene-device-clock"; | |
| 240 | #clock-cells = <1>; | |
| 241 | clocks = <&socplldiv2 0>; | |
| 242 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
| 243 | reg-names = "csr-reg"; | |
| 244 | clock-output-names = "sataphy3clk"; | |
| 245 | status = "ok"; | |
| 246 | csr-offset = <0x4>; | |
| 247 | csr-mask = <0x3a>; | |
| 248 | enable-offset = <0x0>; | |
| 249 | enable-mask = <0x06>; | |
| 250 | }; | |
| db8c0286 LH |
251 | |
| 252 | sata01clk: sata01clk@1f21c000 { | |
| 253 | compatible = "apm,xgene-device-clock"; | |
| 254 | #clock-cells = <1>; | |
| 255 | clocks = <&socplldiv2 0>; | |
| 256 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
| 257 | reg-names = "csr-reg"; | |
| 258 | clock-output-names = "sata01clk"; | |
| 259 | csr-offset = <0x4>; | |
| 260 | csr-mask = <0x05>; | |
| 261 | enable-offset = <0x0>; | |
| 262 | enable-mask = <0x39>; | |
| 263 | }; | |
| 264 | ||
| 265 | sata23clk: sata23clk@1f22c000 { | |
| 266 | compatible = "apm,xgene-device-clock"; | |
| 267 | #clock-cells = <1>; | |
| 268 | clocks = <&socplldiv2 0>; | |
| 269 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
| 270 | reg-names = "csr-reg"; | |
| 271 | clock-output-names = "sata23clk"; | |
| 272 | csr-offset = <0x4>; | |
| 273 | csr-mask = <0x05>; | |
| 274 | enable-offset = <0x0>; | |
| 275 | enable-mask = <0x39>; | |
| 276 | }; | |
| 277 | ||
| 278 | sata45clk: sata45clk@1f23c000 { | |
| 279 | compatible = "apm,xgene-device-clock"; | |
| 280 | #clock-cells = <1>; | |
| 281 | clocks = <&socplldiv2 0>; | |
| 282 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
| 283 | reg-names = "csr-reg"; | |
| 284 | clock-output-names = "sata45clk"; | |
| 285 | csr-offset = <0x4>; | |
| 286 | csr-mask = <0x05>; | |
| 287 | enable-offset = <0x0>; | |
| 288 | enable-mask = <0x39>; | |
| 289 | }; | |
| 652ba666 LH |
290 | |
| 291 | rtcclk: rtcclk@17000000 { | |
| 292 | compatible = "apm,xgene-device-clock"; | |
| 293 | #clock-cells = <1>; | |
| 294 | clocks = <&socplldiv2 0>; | |
| 295 | reg = <0x0 0x17000000 0x0 0x2000>; | |
| 296 | reg-names = "csr-reg"; | |
| 297 | csr-offset = <0xc>; | |
| 298 | csr-mask = <0x2>; | |
| 299 | enable-offset = <0x10>; | |
| 300 | enable-mask = <0x2>; | |
| 301 | clock-output-names = "rtcclk"; | |
| 302 | }; | |
| ab818739 FK |
303 | |
| 304 | rngpkaclk: rngpkaclk@17000000 { | |
| 305 | compatible = "apm,xgene-device-clock"; | |
| 306 | #clock-cells = <1>; | |
| 307 | clocks = <&socplldiv2 0>; | |
| 308 | reg = <0x0 0x17000000 0x0 0x2000>; | |
| 309 | reg-names = "csr-reg"; | |
| 310 | csr-offset = <0xc>; | |
| 311 | csr-mask = <0x10>; | |
| 312 | enable-offset = <0x10>; | |
| 313 | enable-mask = <0x10>; | |
| 314 | clock-output-names = "rngpkaclk"; | |
| 315 | }; | |
| 80213c03 | 316 | |
| 767ebaff TI |
317 | pcie0clk: pcie0clk@1f2bc000 { |
| 318 | status = "disabled"; | |
| 319 | compatible = "apm,xgene-device-clock"; | |
| 320 | #clock-cells = <1>; | |
| 321 | clocks = <&socplldiv2 0>; | |
| 322 | reg = <0x0 0x1f2bc000 0x0 0x1000>; | |
| 323 | reg-names = "csr-reg"; | |
| 324 | clock-output-names = "pcie0clk"; | |
| 325 | }; | |
| 326 | ||
| 327 | pcie1clk: pcie1clk@1f2cc000 { | |
| 328 | status = "disabled"; | |
| 329 | compatible = "apm,xgene-device-clock"; | |
| 330 | #clock-cells = <1>; | |
| 331 | clocks = <&socplldiv2 0>; | |
| 332 | reg = <0x0 0x1f2cc000 0x0 0x1000>; | |
| 333 | reg-names = "csr-reg"; | |
| 334 | clock-output-names = "pcie1clk"; | |
| 335 | }; | |
| 336 | ||
| 337 | pcie2clk: pcie2clk@1f2dc000 { | |
| 338 | status = "disabled"; | |
| 339 | compatible = "apm,xgene-device-clock"; | |
| 340 | #clock-cells = <1>; | |
| 341 | clocks = <&socplldiv2 0>; | |
| 342 | reg = <0x0 0x1f2dc000 0x0 0x1000>; | |
| 343 | reg-names = "csr-reg"; | |
| 344 | clock-output-names = "pcie2clk"; | |
| 345 | }; | |
| 346 | ||
| 347 | pcie3clk: pcie3clk@1f50c000 { | |
| 348 | status = "disabled"; | |
| 349 | compatible = "apm,xgene-device-clock"; | |
| 350 | #clock-cells = <1>; | |
| 351 | clocks = <&socplldiv2 0>; | |
| 352 | reg = <0x0 0x1f50c000 0x0 0x1000>; | |
| 353 | reg-names = "csr-reg"; | |
| 354 | clock-output-names = "pcie3clk"; | |
| 355 | }; | |
| 356 | ||
| 357 | pcie4clk: pcie4clk@1f51c000 { | |
| 358 | status = "disabled"; | |
| 359 | compatible = "apm,xgene-device-clock"; | |
| 360 | #clock-cells = <1>; | |
| 361 | clocks = <&socplldiv2 0>; | |
| 362 | reg = <0x0 0x1f51c000 0x0 0x1000>; | |
| 363 | reg-names = "csr-reg"; | |
| 364 | clock-output-names = "pcie4clk"; | |
| 365 | }; | |
| 74e353e1 RPS |
366 | |
| 367 | dmaclk: dmaclk@1f27c000 { | |
| 368 | compatible = "apm,xgene-device-clock"; | |
| 369 | #clock-cells = <1>; | |
| 370 | clocks = <&socplldiv2 0>; | |
| 371 | reg = <0x0 0x1f27c000 0x0 0x1000>; | |
| 372 | reg-names = "csr-reg"; | |
| 373 | clock-output-names = "dmaclk"; | |
| 374 | }; | |
| 767ebaff TI |
375 | }; |
| 376 | ||
| e1e6e5c4 DD |
377 | msi: msi@79000000 { |
| 378 | compatible = "apm,xgene1-msi"; | |
| 379 | msi-controller; | |
| 380 | reg = <0x00 0x79000000 0x0 0x900000>; | |
| 381 | interrupts = < 0x0 0x10 0x4 | |
| 382 | 0x0 0x11 0x4 | |
| 383 | 0x0 0x12 0x4 | |
| 384 | 0x0 0x13 0x4 | |
| 385 | 0x0 0x14 0x4 | |
| 386 | 0x0 0x15 0x4 | |
| 387 | 0x0 0x16 0x4 | |
| 388 | 0x0 0x17 0x4 | |
| 389 | 0x0 0x18 0x4 | |
| 390 | 0x0 0x19 0x4 | |
| 391 | 0x0 0x1a 0x4 | |
| 392 | 0x0 0x1b 0x4 | |
| 393 | 0x0 0x1c 0x4 | |
| 394 | 0x0 0x1d 0x4 | |
| 395 | 0x0 0x1e 0x4 | |
| 396 | 0x0 0x1f 0x4>; | |
| 397 | }; | |
| 398 | ||
| 5c3a87e3 FK |
399 | scu: system-clk-controller@17000000 { |
| 400 | compatible = "apm,xgene-scu","syscon"; | |
| 401 | reg = <0x0 0x17000000 0x0 0x400>; | |
| 402 | }; | |
| 403 | ||
| 404 | reboot: reboot@17000014 { | |
| 405 | compatible = "syscon-reboot"; | |
| 406 | regmap = <&scu>; | |
| 407 | offset = <0x14>; | |
| 408 | mask = <0x1>; | |
| 409 | }; | |
| 410 | ||
| 8f2ae6f3 LH |
411 | csw: csw@7e200000 { |
| 412 | compatible = "apm,xgene-csw", "syscon"; | |
| 413 | reg = <0x0 0x7e200000 0x0 0x1000>; | |
| 414 | }; | |
| 415 | ||
| 416 | mcba: mcba@7e700000 { | |
| 417 | compatible = "apm,xgene-mcb", "syscon"; | |
| 418 | reg = <0x0 0x7e700000 0x0 0x1000>; | |
| 419 | }; | |
| 420 | ||
| 421 | mcbb: mcbb@7e720000 { | |
| 422 | compatible = "apm,xgene-mcb", "syscon"; | |
| 423 | reg = <0x0 0x7e720000 0x0 0x1000>; | |
| 424 | }; | |
| 425 | ||
| 426 | efuse: efuse@1054a000 { | |
| 427 | compatible = "apm,xgene-efuse", "syscon"; | |
| 428 | reg = <0x0 0x1054a000 0x0 0x20>; | |
| 429 | }; | |
| 430 | ||
| 431 | edac@78800000 { | |
| 432 | compatible = "apm,xgene-edac"; | |
| 433 | #address-cells = <2>; | |
| 434 | #size-cells = <2>; | |
| 435 | ranges; | |
| 436 | regmap-csw = <&csw>; | |
| 437 | regmap-mcba = <&mcba>; | |
| 438 | regmap-mcbb = <&mcbb>; | |
| 439 | regmap-efuse = <&efuse>; | |
| 440 | reg = <0x0 0x78800000 0x0 0x100>; | |
| 441 | interrupts = <0x0 0x20 0x4>, | |
| 442 | <0x0 0x21 0x4>, | |
| 443 | <0x0 0x27 0x4>; | |
| 444 | ||
| 445 | edacmc@7e800000 { | |
| 446 | compatible = "apm,xgene-edac-mc"; | |
| 447 | reg = <0x0 0x7e800000 0x0 0x1000>; | |
| 448 | memory-controller = <0>; | |
| 449 | }; | |
| 450 | ||
| 451 | edacmc@7e840000 { | |
| 452 | compatible = "apm,xgene-edac-mc"; | |
| 453 | reg = <0x0 0x7e840000 0x0 0x1000>; | |
| 454 | memory-controller = <1>; | |
| 455 | }; | |
| 456 | ||
| 457 | edacmc@7e880000 { | |
| 458 | compatible = "apm,xgene-edac-mc"; | |
| 459 | reg = <0x0 0x7e880000 0x0 0x1000>; | |
| 460 | memory-controller = <2>; | |
| 461 | }; | |
| 462 | ||
| 463 | edacmc@7e8c0000 { | |
| 464 | compatible = "apm,xgene-edac-mc"; | |
| 465 | reg = <0x0 0x7e8c0000 0x0 0x1000>; | |
| 466 | memory-controller = <3>; | |
| 467 | }; | |
| 468 | ||
| 469 | edacpmd@7c000000 { | |
| 470 | compatible = "apm,xgene-edac-pmd"; | |
| 471 | reg = <0x0 0x7c000000 0x0 0x200000>; | |
| 472 | pmd-controller = <0>; | |
| 473 | }; | |
| 474 | ||
| 475 | edacpmd@7c200000 { | |
| 476 | compatible = "apm,xgene-edac-pmd"; | |
| 477 | reg = <0x0 0x7c200000 0x0 0x200000>; | |
| 478 | pmd-controller = <1>; | |
| 479 | }; | |
| 480 | ||
| 481 | edacpmd@7c400000 { | |
| 482 | compatible = "apm,xgene-edac-pmd"; | |
| 483 | reg = <0x0 0x7c400000 0x0 0x200000>; | |
| 484 | pmd-controller = <2>; | |
| 485 | }; | |
| 486 | ||
| 487 | edacpmd@7c600000 { | |
| 488 | compatible = "apm,xgene-edac-pmd"; | |
| 489 | reg = <0x0 0x7c600000 0x0 0x200000>; | |
| 490 | pmd-controller = <3>; | |
| 491 | }; | |
| 492 | }; | |
| 493 | ||
| 767ebaff TI |
494 | pcie0: pcie@1f2b0000 { |
| 495 | status = "disabled"; | |
| 496 | device_type = "pci"; | |
| 497 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 498 | #interrupt-cells = <1>; | |
| 499 | #size-cells = <2>; | |
| 500 | #address-cells = <3>; | |
| 501 | reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ | |
| 502 | 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 503 | reg-names = "csr", "cfg"; | |
| 504 | ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ | |
| 80bb3eda DD |
505 | 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ |
| 506 | 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ | |
| 767ebaff TI |
507 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
| 508 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 509 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 510 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 | |
| 511 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 | |
| 512 | 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 | |
| 513 | 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; | |
| 514 | dma-coherent; | |
| 515 | clocks = <&pcie0clk 0>; | |
| e1e6e5c4 | 516 | msi-parent = <&msi>; |
| 767ebaff TI |
517 | }; |
| 518 | ||
| 519 | pcie1: pcie@1f2c0000 { | |
| 520 | status = "disabled"; | |
| 521 | device_type = "pci"; | |
| 522 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 523 | #interrupt-cells = <1>; | |
| 524 | #size-cells = <2>; | |
| 525 | #address-cells = <3>; | |
| 526 | reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ | |
| 527 | 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 528 | reg-names = "csr", "cfg"; | |
| 80bb3eda DD |
529 | ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ |
| 530 | 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ | |
| 531 | 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ | |
| 767ebaff TI |
532 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
| 533 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 534 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 535 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 | |
| 536 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 | |
| 537 | 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 | |
| 538 | 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; | |
| 539 | dma-coherent; | |
| 540 | clocks = <&pcie1clk 0>; | |
| e1e6e5c4 | 541 | msi-parent = <&msi>; |
| 767ebaff TI |
542 | }; |
| 543 | ||
| 544 | pcie2: pcie@1f2d0000 { | |
| 545 | status = "disabled"; | |
| 546 | device_type = "pci"; | |
| 547 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 548 | #interrupt-cells = <1>; | |
| 549 | #size-cells = <2>; | |
| 550 | #address-cells = <3>; | |
| 551 | reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ | |
| 552 | 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 553 | reg-names = "csr", "cfg"; | |
| 80bb3eda DD |
554 | ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ |
| 555 | 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ | |
| 556 | 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ | |
| 767ebaff TI |
557 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
| 558 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 559 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 560 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 | |
| 561 | 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 | |
| 562 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 | |
| 563 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; | |
| 564 | dma-coherent; | |
| 565 | clocks = <&pcie2clk 0>; | |
| e1e6e5c4 | 566 | msi-parent = <&msi>; |
| 767ebaff TI |
567 | }; |
| 568 | ||
| 569 | pcie3: pcie@1f500000 { | |
| 570 | status = "disabled"; | |
| 571 | device_type = "pci"; | |
| 572 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 573 | #interrupt-cells = <1>; | |
| 574 | #size-cells = <2>; | |
| 575 | #address-cells = <3>; | |
| 576 | reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ | |
| 577 | 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
| 578 | reg-names = "csr", "cfg"; | |
| 80bb3eda DD |
579 | ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ |
| 580 | 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ | |
| 581 | 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ | |
| 767ebaff TI |
582 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
| 583 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 584 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 585 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 | |
| 586 | 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 | |
| 587 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 | |
| 588 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; | |
| 589 | dma-coherent; | |
| 590 | clocks = <&pcie3clk 0>; | |
| e1e6e5c4 | 591 | msi-parent = <&msi>; |
| 767ebaff TI |
592 | }; |
| 593 | ||
| 594 | pcie4: pcie@1f510000 { | |
| 595 | status = "disabled"; | |
| 596 | device_type = "pci"; | |
| 597 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
| 598 | #interrupt-cells = <1>; | |
| 599 | #size-cells = <2>; | |
| 600 | #address-cells = <3>; | |
| 601 | reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ | |
| 602 | 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ | |
| 603 | reg-names = "csr", "cfg"; | |
| 80bb3eda DD |
604 | ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ |
| 605 | 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ | |
| 606 | 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ | |
| 767ebaff TI |
607 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
| 608 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
| 609 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
| 610 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 | |
| 611 | 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 | |
| 612 | 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 | |
| 613 | 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; | |
| 614 | dma-coherent; | |
| 615 | clocks = <&pcie4clk 0>; | |
| e1e6e5c4 | 616 | msi-parent = <&msi>; |
| 3eb15d84 LH |
617 | }; |
| 618 | ||
| ee877b53 | 619 | serial0: serial@1c020000 { |
| 457ced84 | 620 | status = "disabled"; |
| ee877b53 | 621 | device_type = "serial"; |
| 457ced84 | 622 | compatible = "ns16550a"; |
| ee877b53 VK |
623 | reg = <0 0x1c020000 0x0 0x1000>; |
| 624 | reg-shift = <2>; | |
| 625 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 626 | interrupt-parent = <&gic>; | |
| 627 | interrupts = <0x0 0x4c 0x4>; | |
| 628 | }; | |
| 71b70ee9 | 629 | |
| 457ced84 VK |
630 | serial1: serial@1c021000 { |
| 631 | status = "disabled"; | |
| 632 | device_type = "serial"; | |
| 633 | compatible = "ns16550a"; | |
| 634 | reg = <0 0x1c021000 0x0 0x1000>; | |
| 635 | reg-shift = <2>; | |
| 636 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 637 | interrupt-parent = <&gic>; | |
| 638 | interrupts = <0x0 0x4d 0x4>; | |
| 639 | }; | |
| 640 | ||
| 641 | serial2: serial@1c022000 { | |
| 642 | status = "disabled"; | |
| 643 | device_type = "serial"; | |
| 644 | compatible = "ns16550a"; | |
| 645 | reg = <0 0x1c022000 0x0 0x1000>; | |
| 646 | reg-shift = <2>; | |
| 647 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 648 | interrupt-parent = <&gic>; | |
| 649 | interrupts = <0x0 0x4e 0x4>; | |
| 650 | }; | |
| 651 | ||
| 652 | serial3: serial@1c023000 { | |
| 653 | status = "disabled"; | |
| 654 | device_type = "serial"; | |
| 655 | compatible = "ns16550a"; | |
| 656 | reg = <0 0x1c023000 0x0 0x1000>; | |
| 657 | reg-shift = <2>; | |
| 658 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
| 659 | interrupt-parent = <&gic>; | |
| 660 | interrupts = <0x0 0x4f 0x4>; | |
| 661 | }; | |
| 662 | ||
| 71b70ee9 LH |
663 | phy1: phy@1f21a000 { |
| 664 | compatible = "apm,xgene-phy"; | |
| 665 | reg = <0x0 0x1f21a000 0x0 0x100>; | |
| 666 | #phy-cells = <1>; | |
| 667 | clocks = <&sataphy1clk 0>; | |
| 668 | status = "disabled"; | |
| 669 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
| 670 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
| 671 | }; | |
| 672 | ||
| 673 | phy2: phy@1f22a000 { | |
| 674 | compatible = "apm,xgene-phy"; | |
| 675 | reg = <0x0 0x1f22a000 0x0 0x100>; | |
| 676 | #phy-cells = <1>; | |
| 677 | clocks = <&sataphy2clk 0>; | |
| 678 | status = "ok"; | |
| 679 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
| 680 | apm,tx-eye-tuning = <1 10 10 2 10 10>; | |
| 681 | }; | |
| 682 | ||
| 683 | phy3: phy@1f23a000 { | |
| 684 | compatible = "apm,xgene-phy"; | |
| 685 | reg = <0x0 0x1f23a000 0x0 0x100>; | |
| 686 | #phy-cells = <1>; | |
| 687 | clocks = <&sataphy3clk 0>; | |
| 688 | status = "ok"; | |
| 689 | apm,tx-boost-gain = <31 31 31 31 31 31>; | |
| 690 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
| 691 | }; | |
| db8c0286 LH |
692 | |
| 693 | sata1: sata@1a000000 { | |
| 694 | compatible = "apm,xgene-ahci"; | |
| 695 | reg = <0x0 0x1a000000 0x0 0x1000>, | |
| 696 | <0x0 0x1f210000 0x0 0x1000>, | |
| 697 | <0x0 0x1f21d000 0x0 0x1000>, | |
| 698 | <0x0 0x1f21e000 0x0 0x1000>, | |
| 699 | <0x0 0x1f217000 0x0 0x1000>; | |
| 700 | interrupts = <0x0 0x86 0x4>; | |
| 7a8d1ec1 | 701 | dma-coherent; |
| db8c0286 LH |
702 | status = "disabled"; |
| 703 | clocks = <&sata01clk 0>; | |
| 704 | phys = <&phy1 0>; | |
| 705 | phy-names = "sata-phy"; | |
| 706 | }; | |
| 707 | ||
| 708 | sata2: sata@1a400000 { | |
| 709 | compatible = "apm,xgene-ahci"; | |
| 710 | reg = <0x0 0x1a400000 0x0 0x1000>, | |
| 711 | <0x0 0x1f220000 0x0 0x1000>, | |
| 712 | <0x0 0x1f22d000 0x0 0x1000>, | |
| 713 | <0x0 0x1f22e000 0x0 0x1000>, | |
| 714 | <0x0 0x1f227000 0x0 0x1000>; | |
| 715 | interrupts = <0x0 0x87 0x4>; | |
| 7a8d1ec1 | 716 | dma-coherent; |
| db8c0286 LH |
717 | status = "ok"; |
| 718 | clocks = <&sata23clk 0>; | |
| 719 | phys = <&phy2 0>; | |
| 720 | phy-names = "sata-phy"; | |
| 721 | }; | |
| 722 | ||
| 723 | sata3: sata@1a800000 { | |
| 724 | compatible = "apm,xgene-ahci"; | |
| 725 | reg = <0x0 0x1a800000 0x0 0x1000>, | |
| 726 | <0x0 0x1f230000 0x0 0x1000>, | |
| 727 | <0x0 0x1f23d000 0x0 0x1000>, | |
| 728 | <0x0 0x1f23e000 0x0 0x1000>; | |
| 729 | interrupts = <0x0 0x88 0x4>; | |
| 7a8d1ec1 | 730 | dma-coherent; |
| db8c0286 LH |
731 | status = "ok"; |
| 732 | clocks = <&sata45clk 0>; | |
| 733 | phys = <&phy3 0>; | |
| 734 | phy-names = "sata-phy"; | |
| 735 | }; | |
| 652ba666 | 736 | |
| ea21feb3 V |
737 | sbgpio: sbgpio@17001000{ |
| 738 | compatible = "apm,xgene-gpio-sb"; | |
| 739 | reg = <0x0 0x17001000 0x0 0x400>; | |
| 740 | #gpio-cells = <2>; | |
| 741 | gpio-controller; | |
| 742 | interrupts = <0x0 0x28 0x1>, | |
| 743 | <0x0 0x29 0x1>, | |
| 744 | <0x0 0x2a 0x1>, | |
| 745 | <0x0 0x2b 0x1>, | |
| 746 | <0x0 0x2c 0x1>, | |
| 747 | <0x0 0x2d 0x1>; | |
| 748 | }; | |
| 749 | ||
| 652ba666 LH |
750 | rtc: rtc@10510000 { |
| 751 | compatible = "apm,xgene-rtc"; | |
| 752 | reg = <0x0 0x10510000 0x0 0x400>; | |
| 753 | interrupts = <0x0 0x46 0x4>; | |
| 754 | #clock-cells = <1>; | |
| 755 | clocks = <&rtcclk 0>; | |
| 756 | }; | |
| 3d390425 IS |
757 | |
| 758 | menet: ethernet@17020000 { | |
| 759 | compatible = "apm,xgene-enet"; | |
| 760 | status = "disabled"; | |
| 761 | reg = <0x0 0x17020000 0x0 0xd100>, | |
| 09c9e059 | 762 | <0x0 0X17030000 0x0 0Xc300>, |
| 3d390425 IS |
763 | <0x0 0X10000000 0x0 0X200>; |
| 764 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
| 765 | interrupts = <0x0 0x3c 0x4>; | |
| 766 | dma-coherent; | |
| 767 | clocks = <&menetclk 0>; | |
| 5fb32417 IS |
768 | /* mac address will be overwritten by the bootloader */ |
| 769 | local-mac-address = [00 00 00 00 00 00]; | |
| 3d390425 IS |
770 | phy-connection-type = "rgmii"; |
| 771 | phy-handle = <&menetphy>; | |
| 772 | mdio { | |
| 773 | compatible = "apm,xgene-mdio"; | |
| 774 | #address-cells = <1>; | |
| 775 | #size-cells = <0>; | |
| 776 | menetphy: menetphy@3 { | |
| 777 | compatible = "ethernet-phy-id001c.c915"; | |
| 778 | reg = <0x3>; | |
| 779 | }; | |
| 780 | ||
| 781 | }; | |
| 782 | }; | |
| ab818739 | 783 | |
| 4c2e7f09 | 784 | sgenet0: ethernet@1f210000 { |
| 2a91eb72 | 785 | compatible = "apm,xgene1-sgenet"; |
| 4c2e7f09 | 786 | status = "disabled"; |
| 09c9e059 IS |
787 | reg = <0x0 0x1f210000 0x0 0xd100>, |
| 788 | <0x0 0x1f200000 0x0 0Xc300>, | |
| 789 | <0x0 0x1B000000 0x0 0X200>; | |
| 4c2e7f09 | 790 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
| d3134649 IS |
791 | interrupts = <0x0 0xA0 0x4>, |
| 792 | <0x0 0xA1 0x4>; | |
| 4c2e7f09 IS |
793 | dma-coherent; |
| 794 | clocks = <&sge0clk 0>; | |
| 795 | local-mac-address = [00 00 00 00 00 00]; | |
| 796 | phy-connection-type = "sgmii"; | |
| 797 | }; | |
| 798 | ||
| 2d33394e KC |
799 | sgenet1: ethernet@1f210030 { |
| 800 | compatible = "apm,xgene1-sgenet"; | |
| 801 | status = "disabled"; | |
| 802 | reg = <0x0 0x1f210030 0x0 0xd100>, | |
| 803 | <0x0 0x1f200000 0x0 0Xc300>, | |
| 804 | <0x0 0x1B000000 0x0 0X8000>; | |
| 805 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
| d3134649 IS |
806 | interrupts = <0x0 0xAC 0x4>, |
| 807 | <0x0 0xAD 0x4>; | |
| 2d33394e KC |
808 | port-id = <1>; |
| 809 | dma-coherent; | |
| 810 | clocks = <&sge1clk 0>; | |
| 811 | local-mac-address = [00 00 00 00 00 00]; | |
| 812 | phy-connection-type = "sgmii"; | |
| 813 | }; | |
| 814 | ||
| 5fb32417 | 815 | xgenet: ethernet@1f610000 { |
| 2a91eb72 | 816 | compatible = "apm,xgene1-xgenet"; |
| 5fb32417 IS |
817 | status = "disabled"; |
| 818 | reg = <0x0 0x1f610000 0x0 0xd100>, | |
| 09c9e059 | 819 | <0x0 0x1f600000 0x0 0Xc300>, |
| 5fb32417 IS |
820 | <0x0 0x18000000 0x0 0X200>; |
| 821 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
| d3134649 IS |
822 | interrupts = <0x0 0x60 0x4>, |
| 823 | <0x0 0x61 0x4>; | |
| 5fb32417 IS |
824 | dma-coherent; |
| 825 | clocks = <&xge0clk 0>; | |
| 826 | /* mac address will be overwritten by the bootloader */ | |
| 827 | local-mac-address = [00 00 00 00 00 00]; | |
| 828 | phy-connection-type = "xgmii"; | |
| 829 | }; | |
| 830 | ||
| ab818739 FK |
831 | rng: rng@10520000 { |
| 832 | compatible = "apm,xgene-rng"; | |
| 833 | reg = <0x0 0x10520000 0x0 0x100>; | |
| 834 | interrupts = <0x0 0x41 0x4>; | |
| 835 | clocks = <&rngpkaclk 0>; | |
| 836 | }; | |
| 74e353e1 RPS |
837 | |
| 838 | dma: dma@1f270000 { | |
| 839 | compatible = "apm,xgene-storm-dma"; | |
| 840 | device_type = "dma"; | |
| 841 | reg = <0x0 0x1f270000 0x0 0x10000>, | |
| 842 | <0x0 0x1f200000 0x0 0x10000>, | |
| cda8e937 | 843 | <0x0 0x1b000000 0x0 0x400000>, |
| 74e353e1 RPS |
844 | <0x0 0x1054a000 0x0 0x100>; |
| 845 | interrupts = <0x0 0x82 0x4>, | |
| 846 | <0x0 0xb8 0x4>, | |
| 847 | <0x0 0xb9 0x4>, | |
| 848 | <0x0 0xba 0x4>, | |
| 849 | <0x0 0xbb 0x4>; | |
| 850 | dma-coherent; | |
| 851 | clocks = <&dmaclk 0>; | |
| 852 | }; | |
| ee877b53 VK |
853 | }; |
| 854 | }; |