Commit | Line | Data |
---|---|---|
ee877b53 VK |
1 | /* |
2 | * dts file for AppliedMicro (APM) X-Gene Storm SOC | |
3 | * | |
4 | * Copyright (C) 2013, Applied Micro Circuits Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | / { | |
13 | compatible = "apm,xgene-storm"; | |
14 | interrupt-parent = <&gic>; | |
15 | #address-cells = <2>; | |
16 | #size-cells = <2>; | |
17 | ||
18 | cpus { | |
19 | #address-cells = <2>; | |
20 | #size-cells = <0>; | |
21 | ||
22 | cpu@000 { | |
23 | device_type = "cpu"; | |
24 | compatible = "apm,potenza", "arm,armv8"; | |
25 | reg = <0x0 0x000>; | |
26 | enable-method = "spin-table"; | |
27 | cpu-release-addr = <0x1 0x0000fff8>; | |
28 | }; | |
29 | cpu@001 { | |
30 | device_type = "cpu"; | |
31 | compatible = "apm,potenza", "arm,armv8"; | |
32 | reg = <0x0 0x001>; | |
33 | enable-method = "spin-table"; | |
34 | cpu-release-addr = <0x1 0x0000fff8>; | |
35 | }; | |
36 | cpu@100 { | |
37 | device_type = "cpu"; | |
38 | compatible = "apm,potenza", "arm,armv8"; | |
39 | reg = <0x0 0x100>; | |
40 | enable-method = "spin-table"; | |
41 | cpu-release-addr = <0x1 0x0000fff8>; | |
42 | }; | |
43 | cpu@101 { | |
44 | device_type = "cpu"; | |
45 | compatible = "apm,potenza", "arm,armv8"; | |
46 | reg = <0x0 0x101>; | |
47 | enable-method = "spin-table"; | |
48 | cpu-release-addr = <0x1 0x0000fff8>; | |
49 | }; | |
50 | cpu@200 { | |
51 | device_type = "cpu"; | |
52 | compatible = "apm,potenza", "arm,armv8"; | |
53 | reg = <0x0 0x200>; | |
54 | enable-method = "spin-table"; | |
55 | cpu-release-addr = <0x1 0x0000fff8>; | |
56 | }; | |
57 | cpu@201 { | |
58 | device_type = "cpu"; | |
59 | compatible = "apm,potenza", "arm,armv8"; | |
60 | reg = <0x0 0x201>; | |
61 | enable-method = "spin-table"; | |
62 | cpu-release-addr = <0x1 0x0000fff8>; | |
63 | }; | |
64 | cpu@300 { | |
65 | device_type = "cpu"; | |
66 | compatible = "apm,potenza", "arm,armv8"; | |
67 | reg = <0x0 0x300>; | |
68 | enable-method = "spin-table"; | |
69 | cpu-release-addr = <0x1 0x0000fff8>; | |
70 | }; | |
71 | cpu@301 { | |
72 | device_type = "cpu"; | |
73 | compatible = "apm,potenza", "arm,armv8"; | |
74 | reg = <0x0 0x301>; | |
75 | enable-method = "spin-table"; | |
76 | cpu-release-addr = <0x1 0x0000fff8>; | |
77 | }; | |
78 | }; | |
79 | ||
80 | gic: interrupt-controller@78010000 { | |
81 | compatible = "arm,cortex-a15-gic"; | |
82 | #interrupt-cells = <3>; | |
83 | interrupt-controller; | |
84 | reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ | |
85 | <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ | |
86 | <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ | |
87 | <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ | |
88 | interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ | |
89 | }; | |
90 | ||
91 | timer { | |
92 | compatible = "arm,armv8-timer"; | |
93 | interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ | |
94 | <1 13 0xff01>, /* Non-secure Phys IRQ */ | |
95 | <1 14 0xff01>, /* Virt IRQ */ | |
96 | <1 15 0xff01>; /* Hyp IRQ */ | |
97 | clock-frequency = <50000000>; | |
98 | }; | |
99 | ||
7434f42b FK |
100 | pmu { |
101 | compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; | |
102 | interrupts = <1 12 0xff04>; | |
103 | }; | |
104 | ||
ee877b53 VK |
105 | soc { |
106 | compatible = "simple-bus"; | |
107 | #address-cells = <2>; | |
108 | #size-cells = <2>; | |
109 | ranges; | |
74e353e1 | 110 | dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; |
ee877b53 | 111 | |
3eb15d84 LH |
112 | clocks { |
113 | #address-cells = <2>; | |
114 | #size-cells = <2>; | |
115 | ranges; | |
116 | refclk: refclk { | |
117 | compatible = "fixed-clock"; | |
118 | #clock-cells = <1>; | |
119 | clock-frequency = <100000000>; | |
120 | clock-output-names = "refclk"; | |
121 | }; | |
122 | ||
123 | pcppll: pcppll@17000100 { | |
124 | compatible = "apm,xgene-pcppll-clock"; | |
125 | #clock-cells = <1>; | |
126 | clocks = <&refclk 0>; | |
127 | clock-names = "pcppll"; | |
128 | reg = <0x0 0x17000100 0x0 0x1000>; | |
129 | clock-output-names = "pcppll"; | |
130 | type = <0>; | |
131 | }; | |
132 | ||
133 | socpll: socpll@17000120 { | |
134 | compatible = "apm,xgene-socpll-clock"; | |
135 | #clock-cells = <1>; | |
136 | clocks = <&refclk 0>; | |
137 | clock-names = "socpll"; | |
138 | reg = <0x0 0x17000120 0x0 0x1000>; | |
139 | clock-output-names = "socpll"; | |
140 | type = <1>; | |
141 | }; | |
142 | ||
143 | socplldiv2: socplldiv2 { | |
144 | compatible = "fixed-factor-clock"; | |
145 | #clock-cells = <1>; | |
146 | clocks = <&socpll 0>; | |
147 | clock-names = "socplldiv2"; | |
148 | clock-mult = <1>; | |
149 | clock-div = <2>; | |
150 | clock-output-names = "socplldiv2"; | |
151 | }; | |
152 | ||
8f74e861 ST |
153 | ahbclk: ahbclk@1f2ac000 { |
154 | compatible = "apm,xgene-device-clock"; | |
155 | #clock-cells = <1>; | |
156 | clocks = <&socplldiv2 0>; | |
157 | reg = <0x0 0x1f2ac000 0x0 0x1000 | |
158 | 0x0 0x17000000 0x0 0x2000>; | |
159 | reg-names = "csr-reg", "div-reg"; | |
160 | csr-offset = <0x0>; | |
161 | csr-mask = <0x1>; | |
162 | enable-offset = <0x8>; | |
163 | enable-mask = <0x1>; | |
164 | divider-offset = <0x164>; | |
165 | divider-width = <0x5>; | |
166 | divider-shift = <0x0>; | |
167 | clock-output-names = "ahbclk"; | |
168 | }; | |
169 | ||
170 | sdioclk: sdioclk@1f2ac000 { | |
171 | compatible = "apm,xgene-device-clock"; | |
172 | #clock-cells = <1>; | |
173 | clocks = <&socplldiv2 0>; | |
174 | reg = <0x0 0x1f2ac000 0x0 0x1000 | |
175 | 0x0 0x17000000 0x0 0x2000>; | |
176 | reg-names = "csr-reg", "div-reg"; | |
177 | csr-offset = <0x0>; | |
178 | csr-mask = <0x2>; | |
179 | enable-offset = <0x8>; | |
180 | enable-mask = <0x2>; | |
181 | divider-offset = <0x178>; | |
182 | divider-width = <0x8>; | |
183 | divider-shift = <0x0>; | |
184 | clock-output-names = "sdioclk"; | |
185 | }; | |
186 | ||
3eb15d84 LH |
187 | qmlclk: qmlclk { |
188 | compatible = "apm,xgene-device-clock"; | |
189 | #clock-cells = <1>; | |
190 | clocks = <&socplldiv2 0>; | |
191 | clock-names = "qmlclk"; | |
192 | reg = <0x0 0x1703C000 0x0 0x1000>; | |
193 | reg-names = "csr-reg"; | |
194 | clock-output-names = "qmlclk"; | |
195 | }; | |
196 | ||
197 | ethclk: ethclk { | |
198 | compatible = "apm,xgene-device-clock"; | |
199 | #clock-cells = <1>; | |
200 | clocks = <&socplldiv2 0>; | |
201 | clock-names = "ethclk"; | |
202 | reg = <0x0 0x17000000 0x0 0x1000>; | |
203 | reg-names = "div-reg"; | |
204 | divider-offset = <0x238>; | |
205 | divider-width = <0x9>; | |
206 | divider-shift = <0x0>; | |
207 | clock-output-names = "ethclk"; | |
208 | }; | |
209 | ||
3d390425 | 210 | menetclk: menetclk { |
3eb15d84 LH |
211 | compatible = "apm,xgene-device-clock"; |
212 | #clock-cells = <1>; | |
213 | clocks = <ðclk 0>; | |
3eb15d84 LH |
214 | reg = <0x0 0x1702C000 0x0 0x1000>; |
215 | reg-names = "csr-reg"; | |
3d390425 | 216 | clock-output-names = "menetclk"; |
3eb15d84 | 217 | }; |
71b70ee9 | 218 | |
4c2e7f09 IS |
219 | sge0clk: sge0clk@1f21c000 { |
220 | compatible = "apm,xgene-device-clock"; | |
221 | #clock-cells = <1>; | |
222 | clocks = <&socplldiv2 0>; | |
223 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
224 | reg-names = "csr-reg"; | |
225 | csr-mask = <0x3>; | |
226 | clock-output-names = "sge0clk"; | |
227 | }; | |
228 | ||
2d33394e KC |
229 | sge1clk: sge1clk@1f21c000 { |
230 | compatible = "apm,xgene-device-clock"; | |
231 | #clock-cells = <1>; | |
232 | clocks = <&socplldiv2 0>; | |
233 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
234 | reg-names = "csr-reg"; | |
235 | csr-mask = <0xc>; | |
236 | clock-output-names = "sge1clk"; | |
237 | }; | |
238 | ||
5fb32417 IS |
239 | xge0clk: xge0clk@1f61c000 { |
240 | compatible = "apm,xgene-device-clock"; | |
241 | #clock-cells = <1>; | |
242 | clocks = <&socplldiv2 0>; | |
243 | reg = <0x0 0x1f61c000 0x0 0x1000>; | |
244 | reg-names = "csr-reg"; | |
245 | csr-mask = <0x3>; | |
246 | clock-output-names = "xge0clk"; | |
247 | }; | |
248 | ||
e63c7a09 IS |
249 | xge1clk: xge1clk@1f62c000 { |
250 | compatible = "apm,xgene-device-clock"; | |
251 | status = "disabled"; | |
252 | #clock-cells = <1>; | |
253 | clocks = <&socplldiv2 0>; | |
254 | reg = <0x0 0x1f62c000 0x0 0x1000>; | |
255 | reg-names = "csr-reg"; | |
256 | csr-mask = <0x3>; | |
257 | clock-output-names = "xge1clk"; | |
258 | }; | |
259 | ||
71b70ee9 LH |
260 | sataphy1clk: sataphy1clk@1f21c000 { |
261 | compatible = "apm,xgene-device-clock"; | |
262 | #clock-cells = <1>; | |
263 | clocks = <&socplldiv2 0>; | |
264 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
265 | reg-names = "csr-reg"; | |
266 | clock-output-names = "sataphy1clk"; | |
267 | status = "disabled"; | |
268 | csr-offset = <0x4>; | |
269 | csr-mask = <0x00>; | |
270 | enable-offset = <0x0>; | |
271 | enable-mask = <0x06>; | |
272 | }; | |
273 | ||
274 | sataphy2clk: sataphy1clk@1f22c000 { | |
275 | compatible = "apm,xgene-device-clock"; | |
276 | #clock-cells = <1>; | |
277 | clocks = <&socplldiv2 0>; | |
278 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
279 | reg-names = "csr-reg"; | |
280 | clock-output-names = "sataphy2clk"; | |
281 | status = "ok"; | |
282 | csr-offset = <0x4>; | |
283 | csr-mask = <0x3a>; | |
284 | enable-offset = <0x0>; | |
285 | enable-mask = <0x06>; | |
286 | }; | |
287 | ||
288 | sataphy3clk: sataphy1clk@1f23c000 { | |
289 | compatible = "apm,xgene-device-clock"; | |
290 | #clock-cells = <1>; | |
291 | clocks = <&socplldiv2 0>; | |
292 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
293 | reg-names = "csr-reg"; | |
294 | clock-output-names = "sataphy3clk"; | |
295 | status = "ok"; | |
296 | csr-offset = <0x4>; | |
297 | csr-mask = <0x3a>; | |
298 | enable-offset = <0x0>; | |
299 | enable-mask = <0x06>; | |
300 | }; | |
db8c0286 LH |
301 | |
302 | sata01clk: sata01clk@1f21c000 { | |
303 | compatible = "apm,xgene-device-clock"; | |
304 | #clock-cells = <1>; | |
305 | clocks = <&socplldiv2 0>; | |
306 | reg = <0x0 0x1f21c000 0x0 0x1000>; | |
307 | reg-names = "csr-reg"; | |
308 | clock-output-names = "sata01clk"; | |
309 | csr-offset = <0x4>; | |
310 | csr-mask = <0x05>; | |
311 | enable-offset = <0x0>; | |
312 | enable-mask = <0x39>; | |
313 | }; | |
314 | ||
315 | sata23clk: sata23clk@1f22c000 { | |
316 | compatible = "apm,xgene-device-clock"; | |
317 | #clock-cells = <1>; | |
318 | clocks = <&socplldiv2 0>; | |
319 | reg = <0x0 0x1f22c000 0x0 0x1000>; | |
320 | reg-names = "csr-reg"; | |
321 | clock-output-names = "sata23clk"; | |
322 | csr-offset = <0x4>; | |
323 | csr-mask = <0x05>; | |
324 | enable-offset = <0x0>; | |
325 | enable-mask = <0x39>; | |
326 | }; | |
327 | ||
328 | sata45clk: sata45clk@1f23c000 { | |
329 | compatible = "apm,xgene-device-clock"; | |
330 | #clock-cells = <1>; | |
331 | clocks = <&socplldiv2 0>; | |
332 | reg = <0x0 0x1f23c000 0x0 0x1000>; | |
333 | reg-names = "csr-reg"; | |
334 | clock-output-names = "sata45clk"; | |
335 | csr-offset = <0x4>; | |
336 | csr-mask = <0x05>; | |
337 | enable-offset = <0x0>; | |
338 | enable-mask = <0x39>; | |
339 | }; | |
652ba666 LH |
340 | |
341 | rtcclk: rtcclk@17000000 { | |
342 | compatible = "apm,xgene-device-clock"; | |
343 | #clock-cells = <1>; | |
344 | clocks = <&socplldiv2 0>; | |
345 | reg = <0x0 0x17000000 0x0 0x2000>; | |
346 | reg-names = "csr-reg"; | |
347 | csr-offset = <0xc>; | |
348 | csr-mask = <0x2>; | |
349 | enable-offset = <0x10>; | |
350 | enable-mask = <0x2>; | |
351 | clock-output-names = "rtcclk"; | |
352 | }; | |
ab818739 FK |
353 | |
354 | rngpkaclk: rngpkaclk@17000000 { | |
355 | compatible = "apm,xgene-device-clock"; | |
356 | #clock-cells = <1>; | |
357 | clocks = <&socplldiv2 0>; | |
358 | reg = <0x0 0x17000000 0x0 0x2000>; | |
359 | reg-names = "csr-reg"; | |
360 | csr-offset = <0xc>; | |
361 | csr-mask = <0x10>; | |
362 | enable-offset = <0x10>; | |
363 | enable-mask = <0x10>; | |
364 | clock-output-names = "rngpkaclk"; | |
365 | }; | |
80213c03 | 366 | |
767ebaff TI |
367 | pcie0clk: pcie0clk@1f2bc000 { |
368 | status = "disabled"; | |
369 | compatible = "apm,xgene-device-clock"; | |
370 | #clock-cells = <1>; | |
371 | clocks = <&socplldiv2 0>; | |
372 | reg = <0x0 0x1f2bc000 0x0 0x1000>; | |
373 | reg-names = "csr-reg"; | |
374 | clock-output-names = "pcie0clk"; | |
375 | }; | |
376 | ||
377 | pcie1clk: pcie1clk@1f2cc000 { | |
378 | status = "disabled"; | |
379 | compatible = "apm,xgene-device-clock"; | |
380 | #clock-cells = <1>; | |
381 | clocks = <&socplldiv2 0>; | |
382 | reg = <0x0 0x1f2cc000 0x0 0x1000>; | |
383 | reg-names = "csr-reg"; | |
384 | clock-output-names = "pcie1clk"; | |
385 | }; | |
386 | ||
387 | pcie2clk: pcie2clk@1f2dc000 { | |
388 | status = "disabled"; | |
389 | compatible = "apm,xgene-device-clock"; | |
390 | #clock-cells = <1>; | |
391 | clocks = <&socplldiv2 0>; | |
392 | reg = <0x0 0x1f2dc000 0x0 0x1000>; | |
393 | reg-names = "csr-reg"; | |
394 | clock-output-names = "pcie2clk"; | |
395 | }; | |
396 | ||
397 | pcie3clk: pcie3clk@1f50c000 { | |
398 | status = "disabled"; | |
399 | compatible = "apm,xgene-device-clock"; | |
400 | #clock-cells = <1>; | |
401 | clocks = <&socplldiv2 0>; | |
402 | reg = <0x0 0x1f50c000 0x0 0x1000>; | |
403 | reg-names = "csr-reg"; | |
404 | clock-output-names = "pcie3clk"; | |
405 | }; | |
406 | ||
407 | pcie4clk: pcie4clk@1f51c000 { | |
408 | status = "disabled"; | |
409 | compatible = "apm,xgene-device-clock"; | |
410 | #clock-cells = <1>; | |
411 | clocks = <&socplldiv2 0>; | |
412 | reg = <0x0 0x1f51c000 0x0 0x1000>; | |
413 | reg-names = "csr-reg"; | |
414 | clock-output-names = "pcie4clk"; | |
415 | }; | |
74e353e1 RPS |
416 | |
417 | dmaclk: dmaclk@1f27c000 { | |
418 | compatible = "apm,xgene-device-clock"; | |
419 | #clock-cells = <1>; | |
420 | clocks = <&socplldiv2 0>; | |
421 | reg = <0x0 0x1f27c000 0x0 0x1000>; | |
422 | reg-names = "csr-reg"; | |
423 | clock-output-names = "dmaclk"; | |
424 | }; | |
767ebaff TI |
425 | }; |
426 | ||
e1e6e5c4 DD |
427 | msi: msi@79000000 { |
428 | compatible = "apm,xgene1-msi"; | |
429 | msi-controller; | |
430 | reg = <0x00 0x79000000 0x0 0x900000>; | |
431 | interrupts = < 0x0 0x10 0x4 | |
432 | 0x0 0x11 0x4 | |
433 | 0x0 0x12 0x4 | |
434 | 0x0 0x13 0x4 | |
435 | 0x0 0x14 0x4 | |
436 | 0x0 0x15 0x4 | |
437 | 0x0 0x16 0x4 | |
438 | 0x0 0x17 0x4 | |
439 | 0x0 0x18 0x4 | |
440 | 0x0 0x19 0x4 | |
441 | 0x0 0x1a 0x4 | |
442 | 0x0 0x1b 0x4 | |
443 | 0x0 0x1c 0x4 | |
444 | 0x0 0x1d 0x4 | |
445 | 0x0 0x1e 0x4 | |
446 | 0x0 0x1f 0x4>; | |
447 | }; | |
448 | ||
5c3a87e3 FK |
449 | scu: system-clk-controller@17000000 { |
450 | compatible = "apm,xgene-scu","syscon"; | |
451 | reg = <0x0 0x17000000 0x0 0x400>; | |
452 | }; | |
453 | ||
454 | reboot: reboot@17000014 { | |
455 | compatible = "syscon-reboot"; | |
456 | regmap = <&scu>; | |
457 | offset = <0x14>; | |
458 | mask = <0x1>; | |
459 | }; | |
460 | ||
8f2ae6f3 LH |
461 | csw: csw@7e200000 { |
462 | compatible = "apm,xgene-csw", "syscon"; | |
463 | reg = <0x0 0x7e200000 0x0 0x1000>; | |
464 | }; | |
465 | ||
466 | mcba: mcba@7e700000 { | |
467 | compatible = "apm,xgene-mcb", "syscon"; | |
468 | reg = <0x0 0x7e700000 0x0 0x1000>; | |
469 | }; | |
470 | ||
471 | mcbb: mcbb@7e720000 { | |
472 | compatible = "apm,xgene-mcb", "syscon"; | |
473 | reg = <0x0 0x7e720000 0x0 0x1000>; | |
474 | }; | |
475 | ||
476 | efuse: efuse@1054a000 { | |
477 | compatible = "apm,xgene-efuse", "syscon"; | |
478 | reg = <0x0 0x1054a000 0x0 0x20>; | |
479 | }; | |
480 | ||
481 | edac@78800000 { | |
482 | compatible = "apm,xgene-edac"; | |
483 | #address-cells = <2>; | |
484 | #size-cells = <2>; | |
485 | ranges; | |
486 | regmap-csw = <&csw>; | |
487 | regmap-mcba = <&mcba>; | |
488 | regmap-mcbb = <&mcbb>; | |
489 | regmap-efuse = <&efuse>; | |
490 | reg = <0x0 0x78800000 0x0 0x100>; | |
491 | interrupts = <0x0 0x20 0x4>, | |
492 | <0x0 0x21 0x4>, | |
493 | <0x0 0x27 0x4>; | |
494 | ||
495 | edacmc@7e800000 { | |
496 | compatible = "apm,xgene-edac-mc"; | |
497 | reg = <0x0 0x7e800000 0x0 0x1000>; | |
498 | memory-controller = <0>; | |
499 | }; | |
500 | ||
501 | edacmc@7e840000 { | |
502 | compatible = "apm,xgene-edac-mc"; | |
503 | reg = <0x0 0x7e840000 0x0 0x1000>; | |
504 | memory-controller = <1>; | |
505 | }; | |
506 | ||
507 | edacmc@7e880000 { | |
508 | compatible = "apm,xgene-edac-mc"; | |
509 | reg = <0x0 0x7e880000 0x0 0x1000>; | |
510 | memory-controller = <2>; | |
511 | }; | |
512 | ||
513 | edacmc@7e8c0000 { | |
514 | compatible = "apm,xgene-edac-mc"; | |
515 | reg = <0x0 0x7e8c0000 0x0 0x1000>; | |
516 | memory-controller = <3>; | |
517 | }; | |
518 | ||
519 | edacpmd@7c000000 { | |
520 | compatible = "apm,xgene-edac-pmd"; | |
521 | reg = <0x0 0x7c000000 0x0 0x200000>; | |
522 | pmd-controller = <0>; | |
523 | }; | |
524 | ||
525 | edacpmd@7c200000 { | |
526 | compatible = "apm,xgene-edac-pmd"; | |
527 | reg = <0x0 0x7c200000 0x0 0x200000>; | |
528 | pmd-controller = <1>; | |
529 | }; | |
530 | ||
531 | edacpmd@7c400000 { | |
532 | compatible = "apm,xgene-edac-pmd"; | |
533 | reg = <0x0 0x7c400000 0x0 0x200000>; | |
534 | pmd-controller = <2>; | |
535 | }; | |
536 | ||
537 | edacpmd@7c600000 { | |
538 | compatible = "apm,xgene-edac-pmd"; | |
539 | reg = <0x0 0x7c600000 0x0 0x200000>; | |
540 | pmd-controller = <3>; | |
541 | }; | |
043cba96 LH |
542 | |
543 | edacl3@7e600000 { | |
544 | compatible = "apm,xgene-edac-l3"; | |
545 | reg = <0x0 0x7e600000 0x0 0x1000>; | |
546 | }; | |
547 | ||
548 | edacsoc@7e930000 { | |
549 | compatible = "apm,xgene-edac-soc-v1"; | |
550 | reg = <0x0 0x7e930000 0x0 0x1000>; | |
551 | }; | |
8f2ae6f3 LH |
552 | }; |
553 | ||
767ebaff TI |
554 | pcie0: pcie@1f2b0000 { |
555 | status = "disabled"; | |
556 | device_type = "pci"; | |
557 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
558 | #interrupt-cells = <1>; | |
559 | #size-cells = <2>; | |
560 | #address-cells = <3>; | |
561 | reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ | |
562 | 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
563 | reg-names = "csr", "cfg"; | |
564 | ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ | |
80bb3eda DD |
565 | 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ |
566 | 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ | |
767ebaff TI |
567 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
568 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
569 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
570 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 | |
571 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 | |
572 | 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 | |
573 | 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; | |
574 | dma-coherent; | |
575 | clocks = <&pcie0clk 0>; | |
e1e6e5c4 | 576 | msi-parent = <&msi>; |
767ebaff TI |
577 | }; |
578 | ||
579 | pcie1: pcie@1f2c0000 { | |
580 | status = "disabled"; | |
581 | device_type = "pci"; | |
582 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
583 | #interrupt-cells = <1>; | |
584 | #size-cells = <2>; | |
585 | #address-cells = <3>; | |
586 | reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ | |
587 | 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
588 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
589 | ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ |
590 | 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ | |
591 | 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ | |
767ebaff TI |
592 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
593 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
594 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
595 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 | |
596 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 | |
597 | 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 | |
598 | 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; | |
599 | dma-coherent; | |
600 | clocks = <&pcie1clk 0>; | |
e1e6e5c4 | 601 | msi-parent = <&msi>; |
767ebaff TI |
602 | }; |
603 | ||
604 | pcie2: pcie@1f2d0000 { | |
605 | status = "disabled"; | |
606 | device_type = "pci"; | |
607 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
608 | #interrupt-cells = <1>; | |
609 | #size-cells = <2>; | |
610 | #address-cells = <3>; | |
611 | reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ | |
612 | 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
613 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
614 | ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ |
615 | 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ | |
616 | 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ | |
767ebaff TI |
617 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
618 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
619 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
620 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 | |
621 | 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 | |
622 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 | |
623 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; | |
624 | dma-coherent; | |
625 | clocks = <&pcie2clk 0>; | |
e1e6e5c4 | 626 | msi-parent = <&msi>; |
767ebaff TI |
627 | }; |
628 | ||
629 | pcie3: pcie@1f500000 { | |
630 | status = "disabled"; | |
631 | device_type = "pci"; | |
632 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
633 | #interrupt-cells = <1>; | |
634 | #size-cells = <2>; | |
635 | #address-cells = <3>; | |
636 | reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ | |
637 | 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | |
638 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
639 | ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ |
640 | 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ | |
641 | 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ | |
767ebaff TI |
642 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
643 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
644 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
645 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 | |
646 | 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 | |
647 | 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 | |
648 | 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; | |
649 | dma-coherent; | |
650 | clocks = <&pcie3clk 0>; | |
e1e6e5c4 | 651 | msi-parent = <&msi>; |
767ebaff TI |
652 | }; |
653 | ||
654 | pcie4: pcie@1f510000 { | |
655 | status = "disabled"; | |
656 | device_type = "pci"; | |
657 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | |
658 | #interrupt-cells = <1>; | |
659 | #size-cells = <2>; | |
660 | #address-cells = <3>; | |
661 | reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ | |
662 | 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ | |
663 | reg-names = "csr", "cfg"; | |
80bb3eda DD |
664 | ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ |
665 | 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ | |
666 | 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ | |
767ebaff TI |
667 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
668 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | |
669 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | |
670 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 | |
671 | 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 | |
672 | 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 | |
673 | 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; | |
674 | dma-coherent; | |
675 | clocks = <&pcie4clk 0>; | |
e1e6e5c4 | 676 | msi-parent = <&msi>; |
3eb15d84 LH |
677 | }; |
678 | ||
ee877b53 | 679 | serial0: serial@1c020000 { |
457ced84 | 680 | status = "disabled"; |
ee877b53 | 681 | device_type = "serial"; |
457ced84 | 682 | compatible = "ns16550a"; |
ee877b53 VK |
683 | reg = <0 0x1c020000 0x0 0x1000>; |
684 | reg-shift = <2>; | |
685 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
686 | interrupt-parent = <&gic>; | |
687 | interrupts = <0x0 0x4c 0x4>; | |
688 | }; | |
71b70ee9 | 689 | |
457ced84 VK |
690 | serial1: serial@1c021000 { |
691 | status = "disabled"; | |
692 | device_type = "serial"; | |
693 | compatible = "ns16550a"; | |
694 | reg = <0 0x1c021000 0x0 0x1000>; | |
695 | reg-shift = <2>; | |
696 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
697 | interrupt-parent = <&gic>; | |
698 | interrupts = <0x0 0x4d 0x4>; | |
699 | }; | |
700 | ||
701 | serial2: serial@1c022000 { | |
702 | status = "disabled"; | |
703 | device_type = "serial"; | |
704 | compatible = "ns16550a"; | |
705 | reg = <0 0x1c022000 0x0 0x1000>; | |
706 | reg-shift = <2>; | |
707 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
708 | interrupt-parent = <&gic>; | |
709 | interrupts = <0x0 0x4e 0x4>; | |
710 | }; | |
711 | ||
712 | serial3: serial@1c023000 { | |
713 | status = "disabled"; | |
714 | device_type = "serial"; | |
715 | compatible = "ns16550a"; | |
716 | reg = <0 0x1c023000 0x0 0x1000>; | |
717 | reg-shift = <2>; | |
718 | clock-frequency = <10000000>; /* Updated by bootloader */ | |
719 | interrupt-parent = <&gic>; | |
720 | interrupts = <0x0 0x4f 0x4>; | |
721 | }; | |
722 | ||
8f74e861 ST |
723 | mmc0: mmc@1c000000 { |
724 | compatible = "arasan,sdhci-4.9a"; | |
725 | reg = <0x0 0x1c000000 0x0 0x100>; | |
726 | interrupts = <0x0 0x49 0x4>; | |
727 | dma-coherent; | |
728 | no-1-8-v; | |
729 | clock-names = "clk_xin", "clk_ahb"; | |
730 | clocks = <&sdioclk 0>, <&ahbclk 0>; | |
731 | }; | |
732 | ||
71b70ee9 LH |
733 | phy1: phy@1f21a000 { |
734 | compatible = "apm,xgene-phy"; | |
735 | reg = <0x0 0x1f21a000 0x0 0x100>; | |
736 | #phy-cells = <1>; | |
737 | clocks = <&sataphy1clk 0>; | |
738 | status = "disabled"; | |
739 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
740 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
741 | }; | |
742 | ||
743 | phy2: phy@1f22a000 { | |
744 | compatible = "apm,xgene-phy"; | |
745 | reg = <0x0 0x1f22a000 0x0 0x100>; | |
746 | #phy-cells = <1>; | |
747 | clocks = <&sataphy2clk 0>; | |
748 | status = "ok"; | |
749 | apm,tx-boost-gain = <30 30 30 30 30 30>; | |
750 | apm,tx-eye-tuning = <1 10 10 2 10 10>; | |
751 | }; | |
752 | ||
753 | phy3: phy@1f23a000 { | |
754 | compatible = "apm,xgene-phy"; | |
755 | reg = <0x0 0x1f23a000 0x0 0x100>; | |
756 | #phy-cells = <1>; | |
757 | clocks = <&sataphy3clk 0>; | |
758 | status = "ok"; | |
759 | apm,tx-boost-gain = <31 31 31 31 31 31>; | |
760 | apm,tx-eye-tuning = <2 10 10 2 10 10>; | |
761 | }; | |
db8c0286 LH |
762 | |
763 | sata1: sata@1a000000 { | |
764 | compatible = "apm,xgene-ahci"; | |
765 | reg = <0x0 0x1a000000 0x0 0x1000>, | |
766 | <0x0 0x1f210000 0x0 0x1000>, | |
767 | <0x0 0x1f21d000 0x0 0x1000>, | |
768 | <0x0 0x1f21e000 0x0 0x1000>, | |
769 | <0x0 0x1f217000 0x0 0x1000>; | |
770 | interrupts = <0x0 0x86 0x4>; | |
7a8d1ec1 | 771 | dma-coherent; |
db8c0286 LH |
772 | status = "disabled"; |
773 | clocks = <&sata01clk 0>; | |
774 | phys = <&phy1 0>; | |
775 | phy-names = "sata-phy"; | |
776 | }; | |
777 | ||
778 | sata2: sata@1a400000 { | |
779 | compatible = "apm,xgene-ahci"; | |
780 | reg = <0x0 0x1a400000 0x0 0x1000>, | |
781 | <0x0 0x1f220000 0x0 0x1000>, | |
782 | <0x0 0x1f22d000 0x0 0x1000>, | |
783 | <0x0 0x1f22e000 0x0 0x1000>, | |
784 | <0x0 0x1f227000 0x0 0x1000>; | |
785 | interrupts = <0x0 0x87 0x4>; | |
7a8d1ec1 | 786 | dma-coherent; |
db8c0286 LH |
787 | status = "ok"; |
788 | clocks = <&sata23clk 0>; | |
789 | phys = <&phy2 0>; | |
790 | phy-names = "sata-phy"; | |
791 | }; | |
792 | ||
793 | sata3: sata@1a800000 { | |
794 | compatible = "apm,xgene-ahci"; | |
795 | reg = <0x0 0x1a800000 0x0 0x1000>, | |
796 | <0x0 0x1f230000 0x0 0x1000>, | |
797 | <0x0 0x1f23d000 0x0 0x1000>, | |
798 | <0x0 0x1f23e000 0x0 0x1000>; | |
799 | interrupts = <0x0 0x88 0x4>; | |
7a8d1ec1 | 800 | dma-coherent; |
db8c0286 LH |
801 | status = "ok"; |
802 | clocks = <&sata45clk 0>; | |
803 | phys = <&phy3 0>; | |
804 | phy-names = "sata-phy"; | |
805 | }; | |
652ba666 | 806 | |
ea21feb3 V |
807 | sbgpio: sbgpio@17001000{ |
808 | compatible = "apm,xgene-gpio-sb"; | |
809 | reg = <0x0 0x17001000 0x0 0x400>; | |
810 | #gpio-cells = <2>; | |
811 | gpio-controller; | |
812 | interrupts = <0x0 0x28 0x1>, | |
813 | <0x0 0x29 0x1>, | |
814 | <0x0 0x2a 0x1>, | |
815 | <0x0 0x2b 0x1>, | |
816 | <0x0 0x2c 0x1>, | |
817 | <0x0 0x2d 0x1>; | |
818 | }; | |
819 | ||
652ba666 LH |
820 | rtc: rtc@10510000 { |
821 | compatible = "apm,xgene-rtc"; | |
822 | reg = <0x0 0x10510000 0x0 0x400>; | |
823 | interrupts = <0x0 0x46 0x4>; | |
824 | #clock-cells = <1>; | |
825 | clocks = <&rtcclk 0>; | |
826 | }; | |
3d390425 IS |
827 | |
828 | menet: ethernet@17020000 { | |
829 | compatible = "apm,xgene-enet"; | |
830 | status = "disabled"; | |
831 | reg = <0x0 0x17020000 0x0 0xd100>, | |
09c9e059 | 832 | <0x0 0X17030000 0x0 0Xc300>, |
3d390425 IS |
833 | <0x0 0X10000000 0x0 0X200>; |
834 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
835 | interrupts = <0x0 0x3c 0x4>; | |
836 | dma-coherent; | |
837 | clocks = <&menetclk 0>; | |
5fb32417 IS |
838 | /* mac address will be overwritten by the bootloader */ |
839 | local-mac-address = [00 00 00 00 00 00]; | |
3d390425 IS |
840 | phy-connection-type = "rgmii"; |
841 | phy-handle = <&menetphy>; | |
842 | mdio { | |
843 | compatible = "apm,xgene-mdio"; | |
844 | #address-cells = <1>; | |
845 | #size-cells = <0>; | |
846 | menetphy: menetphy@3 { | |
847 | compatible = "ethernet-phy-id001c.c915"; | |
848 | reg = <0x3>; | |
849 | }; | |
850 | ||
851 | }; | |
852 | }; | |
ab818739 | 853 | |
4c2e7f09 | 854 | sgenet0: ethernet@1f210000 { |
2a91eb72 | 855 | compatible = "apm,xgene1-sgenet"; |
4c2e7f09 | 856 | status = "disabled"; |
09c9e059 IS |
857 | reg = <0x0 0x1f210000 0x0 0xd100>, |
858 | <0x0 0x1f200000 0x0 0Xc300>, | |
859 | <0x0 0x1B000000 0x0 0X200>; | |
4c2e7f09 | 860 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
d3134649 IS |
861 | interrupts = <0x0 0xA0 0x4>, |
862 | <0x0 0xA1 0x4>; | |
4c2e7f09 IS |
863 | dma-coherent; |
864 | clocks = <&sge0clk 0>; | |
865 | local-mac-address = [00 00 00 00 00 00]; | |
866 | phy-connection-type = "sgmii"; | |
867 | }; | |
868 | ||
2d33394e KC |
869 | sgenet1: ethernet@1f210030 { |
870 | compatible = "apm,xgene1-sgenet"; | |
871 | status = "disabled"; | |
872 | reg = <0x0 0x1f210030 0x0 0xd100>, | |
873 | <0x0 0x1f200000 0x0 0Xc300>, | |
874 | <0x0 0x1B000000 0x0 0X8000>; | |
875 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
d3134649 IS |
876 | interrupts = <0x0 0xAC 0x4>, |
877 | <0x0 0xAD 0x4>; | |
2d33394e KC |
878 | port-id = <1>; |
879 | dma-coherent; | |
880 | clocks = <&sge1clk 0>; | |
881 | local-mac-address = [00 00 00 00 00 00]; | |
882 | phy-connection-type = "sgmii"; | |
883 | }; | |
884 | ||
5fb32417 | 885 | xgenet: ethernet@1f610000 { |
2a91eb72 | 886 | compatible = "apm,xgene1-xgenet"; |
5fb32417 IS |
887 | status = "disabled"; |
888 | reg = <0x0 0x1f610000 0x0 0xd100>, | |
09c9e059 | 889 | <0x0 0x1f600000 0x0 0Xc300>, |
5fb32417 IS |
890 | <0x0 0x18000000 0x0 0X200>; |
891 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
d3134649 IS |
892 | interrupts = <0x0 0x60 0x4>, |
893 | <0x0 0x61 0x4>; | |
5fb32417 IS |
894 | dma-coherent; |
895 | clocks = <&xge0clk 0>; | |
896 | /* mac address will be overwritten by the bootloader */ | |
897 | local-mac-address = [00 00 00 00 00 00]; | |
898 | phy-connection-type = "xgmii"; | |
899 | }; | |
900 | ||
e63c7a09 IS |
901 | xgenet1: ethernet@1f620000 { |
902 | compatible = "apm,xgene1-xgenet"; | |
903 | status = "disabled"; | |
904 | reg = <0x0 0x1f620000 0x0 0xd100>, | |
905 | <0x0 0x1f600000 0x0 0Xc300>, | |
906 | <0x0 0x18000000 0x0 0X8000>; | |
907 | reg-names = "enet_csr", "ring_csr", "ring_cmd"; | |
908 | interrupts = <0x0 0x6C 0x4>, | |
909 | <0x0 0x6D 0x4>; | |
910 | port-id = <1>; | |
911 | dma-coherent; | |
912 | clocks = <&xge1clk 0>; | |
913 | /* mac address will be overwritten by the bootloader */ | |
914 | local-mac-address = [00 00 00 00 00 00]; | |
915 | phy-connection-type = "xgmii"; | |
916 | }; | |
917 | ||
ab818739 FK |
918 | rng: rng@10520000 { |
919 | compatible = "apm,xgene-rng"; | |
920 | reg = <0x0 0x10520000 0x0 0x100>; | |
921 | interrupts = <0x0 0x41 0x4>; | |
922 | clocks = <&rngpkaclk 0>; | |
923 | }; | |
74e353e1 RPS |
924 | |
925 | dma: dma@1f270000 { | |
926 | compatible = "apm,xgene-storm-dma"; | |
927 | device_type = "dma"; | |
928 | reg = <0x0 0x1f270000 0x0 0x10000>, | |
929 | <0x0 0x1f200000 0x0 0x10000>, | |
cda8e937 | 930 | <0x0 0x1b000000 0x0 0x400000>, |
74e353e1 RPS |
931 | <0x0 0x1054a000 0x0 0x100>; |
932 | interrupts = <0x0 0x82 0x4>, | |
933 | <0x0 0xb8 0x4>, | |
934 | <0x0 0xb9 0x4>, | |
935 | <0x0 0xba 0x4>, | |
936 | <0x0 0xbb 0x4>; | |
937 | dma-coherent; | |
938 | clocks = <&dmaclk 0>; | |
939 | }; | |
ee877b53 VK |
940 | }; |
941 | }; |