[linux-2.6-block.git] / arch / arm64 / boot / dts / altera / socfpga_stratix10.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright Altera Corporation (C) 2015. All rights reserved.
 */

/dts-v1/;
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/stratix10-clock.h>

/ {
	compatible = "altr,socfpga-stratix10";
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		service_reserved: svcbuffer@0 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x0 0x0 0x1000000>;
			alignment = <0x1000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x1>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x2>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x3>;
		};
	};

	firmware {
		svc {
			compatible = "intel,stratix10-svc";
			method = "smc";
			memory-region = <&service_reserved>;

			fpga_mgr: fpga-mgr {
				compatible = "intel,stratix10-soc-fpga-mgr";
			};
		};
	};

	fpga-region {
		compatible = "fpga-region";
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		fpga-mgr = <&fpga_mgr>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <0 170 4>,
			     <0 171 4>,
			     <0 172 4>,
			     <0 173 4>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
		interrupt-parent = <&intc>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	/* Local timer */
	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		interrupt-parent = <&intc>;
	};

	intc: interrupt-controller@fffc1000 {
		compatible = "arm,gic-400", "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0xfffc1000 0x0 0x1000>,
		      <0x0 0xfffc2000 0x0 0x2000>,
		      <0x0 0xfffc4000 0x0 0x2000>,
		      <0x0 0xfffc6000 0x0 0x2000>;
	};

	clocks {
		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		cb_intosc_ls_clk: cb-intosc-ls-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		f2s_free_clk: f2s-free-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		osc1: osc1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};

		qspi_clk: qspi-clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <200000000>;
		};
	};

	soc@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges = <0 0 0 0xffffffff>;

		clkmgr: clock-controller@ffd10000 {
			compatible = "intel,stratix10-clkmgr";
			reg = <0xffd10000 0x1000>;
			#clock-cells = <1>;
		};

		gmac0: ethernet@ff800000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff800000 0x2000>;
			interrupts = <0 90 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
			reset-names = "stmmaceth", "ahb";
			clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 1>;
			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
			status = "disabled";
		};

		gmac1: ethernet@ff802000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff802000 0x2000>;
			interrupts = <0 91 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
			reset-names = "stmmaceth", "ahb";
			clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 2>;
			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
			status = "disabled";
		};

		gmac2: ethernet@ff804000 {
			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
			reg = <0xff804000 0x2000>;
			interrupts = <0 92 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];
			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
			reset-names = "stmmaceth", "ahb";
			clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
			clock-names = "stmmaceth", "ptp_ref";
			tx-fifo-depth = <16384>;
			rx-fifo-depth = <16384>;
			snps,multicast-filter-bins = <256>;
			iommus = <&smmu 3>;
			altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
			status = "disabled";
		};

		gpio0: gpio@ffc03200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03200 0x100>;
			resets = <&rst GPIO0_RESET>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 110 4>;
			};
		};

		gpio1: gpio@ffc03300 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0xffc03300 0x100>;
			resets = <&rst GPIO1_RESET>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <24>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <0 111 4>;
			};
		};

		i2c0: i2c@ffc02800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02800 0x100>;
			interrupts = <0 103 4>;
			resets = <&rst I2C0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c1: i2c@ffc02900 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02900 0x100>;
			interrupts = <0 104 4>;
			resets = <&rst I2C1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c2: i2c@ffc02a00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02a00 0x100>;
			interrupts = <0 105 4>;
			resets = <&rst I2C2_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c3: i2c@ffc02b00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02b00 0x100>;
			interrupts = <0 106 4>;
			resets = <&rst I2C3_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		i2c4: i2c@ffc02c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc02c00 0x100>;
			interrupts = <0 107 4>;
			resets = <&rst I2C4_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		mmc: mmc@ff808000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff808000 0x1000>;
			interrupts = <0 96 4>;
			fifo-depth = <0x400>;
			resets = <&rst SDMMC_RESET>;
			reset-names = "reset";
			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
				 <&clkmgr STRATIX10_SDMMC_CLK>;
			clock-names = "biu", "ciu";
			iommus = <&smmu 5>;
			altr,sysmgr-syscon = <&sysmgr 0x28 4>;
			status = "disabled";
		};

		nand: nand-controller@ffb90000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "altr,socfpga-denali-nand";
			reg = <0xffb90000 0x10000>,
			      <0xffb80000 0x1000>;
			reg-names = "nand_data", "denali_reg";
			interrupts = <0 97 4>;
			clocks = <&clkmgr STRATIX10_NAND_CLK>,
				 <&clkmgr STRATIX10_NAND_X_CLK>,
				 <&clkmgr STRATIX10_NAND_ECC_CLK>;
			clock-names = "nand", "nand_x", "ecc";
			resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
			status = "disabled";
		};

		ocram: sram@ffe00000 {
			compatible = "mmio-sram";
			reg = <0xffe00000 0x100000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0xffe00000 0x100000>;
		};

		pdma: dma-controller@ffda0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xffda0000 0x1000>;
			interrupts = <0 81 4>,
				     <0 82 4>,
				     <0 83 4>,
				     <0 84 4>,
				     <0 85 4>,
				     <0 86 4>,
				     <0 87 4>,
				     <0 88 4>,
				     <0 89 4>;
			#dma-cells = <1>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			clock-names = "apb_pclk";
			resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
			reset-names = "dma", "dma-ocp";
		};

		pinctrl0: pinctrl@ffd13000 {
			compatible = "pinctrl-single";
			reg = <0xffd13000 0xA0>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x0000000f>;
		};

		pinctrl1: pinctrl@ffd13100 {
			compatible = "pinctrl-single";
			reg = <0xffd13100 0x20>;
			#pinctrl-cells = <1>;
			pinctrl-single,register-width = <32>;
			pinctrl-single,function-mask = <0x0000000f>;
		};

		rst: rstmgr@ffd11000 {
			#reset-cells = <1>;
			compatible = "altr,stratix10-rst-mgr";
			reg = <0xffd11000 0x1000>;
		};

		smmu: iommu@fa000000 {
			compatible = "arm,mmu-500", "arm,smmu-v2";
			reg = <0xfa000000 0x40000>;
			#global-interrupts = <2>;
			#iommu-cells = <1>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			clock-names = "iommu";
			interrupt-parent = <&intc>;
			interrupts = <0 128 4>,	/* Global Secure Fault */
				<0 129 4>, /* Global Non-secure Fault */
				/* Non-secure Context Interrupts (32) */
				<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
				<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
				<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
				<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
				<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
				<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
				<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
				<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
			stream-match-mask = <0x7ff0>;
			status = "disabled";
		};

		spi0: spi@ffda4000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda4000 0x1000>;
			interrupts = <0 99 4>;
			resets = <&rst SPIM0_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			status = "disabled";
		};

		spi1: spi@ffda5000 {
			compatible = "snps,dw-apb-ssi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xffda5000 0x1000>;
			interrupts = <0 100 4>;
			resets = <&rst SPIM1_RESET>;
			reset-names = "spi";
			reg-io-width = <4>;
			num-cs = <4>;
			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
			status = "disabled";
		};

		sysmgr: sysmgr@ffd12000 {
			compatible = "altr,sys-mgr-s10","altr,sys-mgr";
			reg = <0xffd12000 0x228>;
		};

		timer0: timer0@ffc03000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 113 4>;
			reg = <0xffc03000 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer1: timer1@ffc03100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 114 4>;
			reg = <0xffc03100 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 115 4>;
			reg = <0xffd00000 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		timer3: timer3@ffd00100 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 116 4>;
			reg = <0xffd00100 0x100>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			clock-names = "timer";
		};

		uart0: serial@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x100>;
			interrupts = <0 108 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		uart1: serial@ffc02100 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02100 0x100>;
			interrupts = <0 109 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			resets = <&rst UART1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
			status = "disabled";
		};

		usb0: usb@ffb00000 {
			compatible = "snps,dwc2";
			reg = <0xffb00000 0x40000>;
			interrupts = <0 93 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr STRATIX10_USB_CLK>;
			clock-names = "otg";
			iommus = <&smmu 6>;
			status = "disabled";
		};

		usb1: usb@ffb40000 {
			compatible = "snps,dwc2";
			reg = <0xffb40000 0x40000>;
			interrupts = <0 94 4>;
			phys = <&usbphy0>;
			phy-names = "usb2-phy";
			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
			reset-names = "dwc2", "dwc2-ecc";
			clocks = <&clkmgr STRATIX10_USB_CLK>;
			clock-names = "otg";
			iommus = <&smmu 7>;
			status = "disabled";
		};

		watchdog0: watchdog@ffd00200 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00200 0x100>;
			interrupts = <0 117 4>;
			resets = <&rst WATCHDOG0_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog1: watchdog@ffd00300 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00300 0x100>;
			interrupts = <0 118 4>;
			resets = <&rst WATCHDOG1_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog2: watchdog@ffd00400 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00400 0x100>;
			interrupts = <0 125 4>;
			resets = <&rst WATCHDOG2_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		watchdog3: watchdog@ffd00500 {
			compatible = "snps,dw-wdt";
			reg = <0xffd00500 0x100>;
			interrupts = <0 126 4>;
			resets = <&rst WATCHDOG3_RESET>;
			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
			status = "disabled";
		};

		sdr: sdr@f8011100 {
			compatible = "altr,sdr-ctl", "syscon";
			reg = <0xf8011100 0xc0>;
		};

		eccmgr {
			compatible = "altr,socfpga-s10-ecc-manager",
				     "altr,socfpga-a10-ecc-manager";
			altr,sysmgr-syscon = <&sysmgr>;
			#address-cells = <1>;
			#size-cells = <1>;
			interrupts = <0 15 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			ranges;

			sdramedac {
				compatible = "altr,sdram-edac-s10";
				altr,sdr-syscon = <&sdr>;
				interrupts = <16 4>;
			};

			ocram-ecc@ff8cc000 {
				compatible = "altr,socfpga-s10-ocram-ecc",
					     "altr,socfpga-a10-ocram-ecc";
				reg = <0xff8cc000 0x100>;
				altr,ecc-parent = <&ocram>;
				interrupts = <1 4>;
			};

			usb0-ecc@ff8c4000 {
				compatible = "altr,socfpga-s10-usb-ecc",
					     "altr,socfpga-usb-ecc";
				reg = <0xff8c4000 0x100>;
				altr,ecc-parent = <&usb0>;
				interrupts = <2 4>;
			};

			emac0-rx-ecc@ff8c0000 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0000 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <4 4>;
			};

			emac0-tx-ecc@ff8c0400 {
				compatible = "altr,socfpga-s10-eth-mac-ecc",
					     "altr,socfpga-eth-mac-ecc";
				reg = <0xff8c0400 0x100>;
				altr,ecc-parent = <&gmac0>;
				interrupts = <5 4>;
			};

		};

		qspi: spi@ff8d2000 {
			compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0xff8d2000 0x100>,
			      <0xff900000 0x100000>;
			interrupts = <0 3 4>;
			cdns,fifo-depth = <128>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x00000000>;
			clocks = <&qspi_clk>;

			status = "disabled";
		};
	};

	usbphy0: usbphy0 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
78cd6a9d DN	2	/*
78cd6a9d DN	3	* Copyright Altera Corporation (C) 2015. All rights reserved.
78cd6a9d DN	4	*/
	5
	6	/dts-v1/;
e519922e	7	#include <dt-bindings/reset/altr,rst-mgr-s10.h>
5a0e622e	8	#include <dt-bindings/gpio/gpio.h>
d93101ab	9	#include <dt-bindings/clock/stratix10-clock.h>
78cd6a9d DN	10
	11	/ {
	12	compatible = "altr,socfpga-stratix10";
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
adb9e354 RG	16	reserved-memory {
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19	ranges;
	20
	21	service_reserved: svcbuffer@0 {
	22	compatible = "shared-dma-pool";
	23	reg = <0x0 0x0 0x0 0x1000000>;
	24	alignment = <0x1000>;
	25	no-map;
	26	};
	27	};
	28
78cd6a9d DN	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu0: cpu@0 {
31af04cd	34	compatible = "arm,cortex-a53";
78cd6a9d DN	35	device_type = "cpu";
	36	enable-method = "psci";
	37	reg = <0x0>;
	38	};
	39
	40	cpu1: cpu@1 {
31af04cd	41	compatible = "arm,cortex-a53";
78cd6a9d DN	42	device_type = "cpu";
	43	enable-method = "psci";
	44	reg = <0x1>;
	45	};
	46
	47	cpu2: cpu@2 {
31af04cd	48	compatible = "arm,cortex-a53";
78cd6a9d DN	49	device_type = "cpu";
	50	enable-method = "psci";
	51	reg = <0x2>;
	52	};
	53
	54	cpu3: cpu@3 {
31af04cd	55	compatible = "arm,cortex-a53";
78cd6a9d DN	56	device_type = "cpu";
	57	enable-method = "psci";
	58	reg = <0x3>;
	59	};
	60	};
	61
9fc0511a KK	62	firmware {
	63	svc {
	64	compatible = "intel,stratix10-svc";
	65	method = "smc";
	66	memory-region = <&service_reserved>;
	67
	68	fpga_mgr: fpga-mgr {
	69	compatible = "intel,stratix10-soc-fpga-mgr";
	70	};
	71	};
	72	};
	73
5c8f036f KK	74	fpga-region {
	75	compatible = "fpga-region";
	76	#address-cells = <0x2>;
	77	#size-cells = <0x2>;
	78	fpga-mgr = <&fpga_mgr>;
	79	};
	80
78cd6a9d	81	pmu {
8b40a469	82	compatible = "arm,cortex-a53-pmu";
210de0e9 DN	83	interrupts = <0 170 4>,
	84	<0 171 4>,
	85	<0 172 4>,
	86	<0 173 4>;
78cd6a9d DN	87	interrupt-affinity = <&cpu0>,
	88	<&cpu1>,
	89	<&cpu2>,
	90	<&cpu3>;
69c4d8ed	91	interrupt-parent = <&intc>;
78cd6a9d DN	92	};
	93
	94	psci {
	95	compatible = "arm,psci-0.2";
	96	method = "smc";
	97	};
	98
79f1db27 KK	99	/* Local timer */
	100	timer {
	101	compatible = "arm,armv8-timer";
	102	interrupts = <1 13 0xf08>,
	103	<1 14 0xf08>,
	104	<1 11 0xf08>,
	105	<1 10 0xf08>;
	106	interrupt-parent = <&intc>;
	107	};
	108
681a5c71	109	intc: interrupt-controller@fffc1000 {
78cd6a9d DN	110	compatible = "arm,gic-400", "arm,cortex-a15-gic";
	111	#interrupt-cells = <3>;
	112	interrupt-controller;
f973bfa0 DN	113	reg = <0x0 0xfffc1000 0x0 0x1000>,
	114	<0x0 0xfffc2000 0x0 0x2000>,
	115	<0x0 0xfffc4000 0x0 0x2000>,
	116	<0x0 0xfffc6000 0x0 0x2000>;
78cd6a9d DN	117	};
78cd6a9d DN	118
357513c0 NR	119	clocks {
	120	cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
	121	#clock-cells = <0>;
	122	compatible = "fixed-clock";
	123	};
	124
	125	cb_intosc_ls_clk: cb-intosc-ls-clk {
	126	#clock-cells = <0>;
	127	compatible = "fixed-clock";
	128	};
	129
	130	f2s_free_clk: f2s-free-clk {
	131	#clock-cells = <0>;
	132	compatible = "fixed-clock";
	133	};
	134
	135	osc1: osc1 {
	136	#clock-cells = <0>;
	137	compatible = "fixed-clock";
	138	};
	139
	140	qspi_clk: qspi-clk {
	141	#clock-cells = <0>;
	142	compatible = "fixed-clock";
	143	clock-frequency = <200000000>;
	144	};
	145	};
	146
5e53525f	147	soc@0 {
78cd6a9d DN	148	#address-cells = <1>;
	149	#size-cells = <1>;
	150	compatible = "simple-bus";
	151	device_type = "soc";
	152	interrupt-parent = <&intc>;
	153	ranges = <0 0 0 0xffffffff>;
	154
d93101ab DN	155	clkmgr: clock-controller@ffd10000 {
d93101ab DN	156	compatible = "intel,stratix10-clkmgr";
78cd6a9d	157	reg = <0xffd10000 0x1000>;
d93101ab DN	158	#clock-cells = <1>;
	159	};
	160
78cd6a9d	161	gmac0: ethernet@ff800000 {
9aa0cae1	162	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
78cd6a9d DN	163	reg = <0xff800000 0x2000>;
	164	interrupts = <0 90 4>;
	165	interrupt-names = "macirq";
	166	mac-address = [00 00 00 00 00 00];
05690e8a	167	resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
331085a4	168	reset-names = "stmmaceth", "ahb";
6e043c65 DN	169	clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
6e043c65 DN	170	clock-names = "stmmaceth", "ptp_ref";
a27460c9 TT	171	tx-fifo-depth = <16384>;
a27460c9 TT	172	rx-fifo-depth = <16384>;
fd5ba6ee	173	snps,multicast-filter-bins = <256>;
ae3f46c8	174	iommus = <&smmu 1>;
8efd6365	175	altr,sysmgr-syscon = <&sysmgr 0x44 0>;
78cd6a9d DN	176	status = "disabled";
	177	};
	178
	179	gmac1: ethernet@ff802000 {
9aa0cae1	180	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
78cd6a9d DN	181	reg = <0xff802000 0x2000>;
	182	interrupts = <0 91 4>;
	183	interrupt-names = "macirq";
	184	mac-address = [00 00 00 00 00 00];
05690e8a	185	resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
331085a4	186	reset-names = "stmmaceth", "ahb";
6e043c65 DN	187	clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
6e043c65 DN	188	clock-names = "stmmaceth", "ptp_ref";
a27460c9 TT	189	tx-fifo-depth = <16384>;
a27460c9 TT	190	rx-fifo-depth = <16384>;
fd5ba6ee	191	snps,multicast-filter-bins = <256>;
ae3f46c8	192	iommus = <&smmu 2>;
9aa0cae1	193	altr,sysmgr-syscon = <&sysmgr 0x48 8>;
78cd6a9d DN	194	status = "disabled";
	195	};
	196
	197	gmac2: ethernet@ff804000 {
9aa0cae1	198	compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
78cd6a9d DN	199	reg = <0xff804000 0x2000>;
	200	interrupts = <0 92 4>;
	201	interrupt-names = "macirq";
	202	mac-address = [00 00 00 00 00 00];
05690e8a	203	resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
331085a4	204	reset-names = "stmmaceth", "ahb";
6e043c65 DN	205	clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>;
6e043c65 DN	206	clock-names = "stmmaceth", "ptp_ref";
a27460c9 TT	207	tx-fifo-depth = <16384>;
a27460c9 TT	208	rx-fifo-depth = <16384>;
fd5ba6ee	209	snps,multicast-filter-bins = <256>;
ae3f46c8	210	iommus = <&smmu 3>;
9aa0cae1	211	altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
78cd6a9d DN	212	status = "disabled";
	213	};
	214
	215	gpio0: gpio@ffc03200 {
	216	#address-cells = <1>;
	217	#size-cells = <0>;
	218	compatible = "snps,dw-apb-gpio";
	219	reg = <0xffc03200 0x100>;
788251fa	220	resets = <&rst GPIO0_RESET>;
78cd6a9d DN	221	status = "disabled";
	222
	223	porta: gpio-controller@0 {
	224	compatible = "snps,dw-apb-gpio-port";
	225	gpio-controller;
	226	#gpio-cells = <2>;
62b3c680	227	ngpios = <24>;
78cd6a9d DN	228	reg = <0>;
	229	interrupt-controller;
	230	#interrupt-cells = <2>;
	231	interrupts = <0 110 4>;
	232	};
	233	};
	234
	235	gpio1: gpio@ffc03300 {
	236	#address-cells = <1>;
	237	#size-cells = <0>;
	238	compatible = "snps,dw-apb-gpio";
	239	reg = <0xffc03300 0x100>;
788251fa	240	resets = <&rst GPIO1_RESET>;
78cd6a9d DN	241	status = "disabled";
	242
	243	portb: gpio-controller@0 {
	244	compatible = "snps,dw-apb-gpio-port";
	245	gpio-controller;
	246	#gpio-cells = <2>;
62b3c680	247	ngpios = <24>;
78cd6a9d DN	248	reg = <0>;
	249	interrupt-controller;
	250	#interrupt-cells = <2>;
a067fb42	251	interrupts = <0 111 4>;
78cd6a9d DN	252	};
	253	};
	254
	255	i2c0: i2c@ffc02800 {
	256	#address-cells = <1>;
	257	#size-cells = <0>;
	258	compatible = "snps,designware-i2c";
	259	reg = <0xffc02800 0x100>;
	260	interrupts = <0 103 4>;
788251fa	261	resets = <&rst I2C0_RESET>;
eebee19e	262	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	263	status = "disabled";
	264	};
	265
	266	i2c1: i2c@ffc02900 {
	267	#address-cells = <1>;
	268	#size-cells = <0>;
	269	compatible = "snps,designware-i2c";
	270	reg = <0xffc02900 0x100>;
	271	interrupts = <0 104 4>;
788251fa	272	resets = <&rst I2C1_RESET>;
eebee19e	273	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	274	status = "disabled";
	275	};
	276
	277	i2c2: i2c@ffc02a00 {
	278	#address-cells = <1>;
	279	#size-cells = <0>;
	280	compatible = "snps,designware-i2c";
	281	reg = <0xffc02a00 0x100>;
	282	interrupts = <0 105 4>;
788251fa	283	resets = <&rst I2C2_RESET>;
eebee19e	284	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	285	status = "disabled";
	286	};
	287
	288	i2c3: i2c@ffc02b00 {
	289	#address-cells = <1>;
	290	#size-cells = <0>;
	291	compatible = "snps,designware-i2c";
	292	reg = <0xffc02b00 0x100>;
	293	interrupts = <0 106 4>;
788251fa	294	resets = <&rst I2C3_RESET>;
eebee19e	295	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	296	status = "disabled";
	297	};
	298
	299	i2c4: i2c@ffc02c00 {
	300	#address-cells = <1>;
	301	#size-cells = <0>;
	302	compatible = "snps,designware-i2c";
	303	reg = <0xffc02c00 0x100>;
	304	interrupts = <0 107 4>;
788251fa	305	resets = <&rst I2C4_RESET>;
eebee19e	306	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	307	status = "disabled";
	308	};
	309
8b794ab2	310	mmc: mmc@ff808000 {
78cd6a9d DN	311	#address-cells = <1>;
	312	#size-cells = <0>;
	313	compatible = "altr,socfpga-dw-mshc";
	314	reg = <0xff808000 0x1000>;
	315	interrupts = <0 96 4>;
	316	fifo-depth = <0x400>;
788251fa DN	317	resets = <&rst SDMMC_RESET>;
788251fa DN	318	reset-names = "reset";
d93101ab DN	319	clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
	320	<&clkmgr STRATIX10_SDMMC_CLK>;
	321	clock-names = "biu", "ciu";
ae3f46c8	322	iommus = <&smmu 5>;
31354121	323	altr,sysmgr-syscon = <&sysmgr 0x28 4>;
78cd6a9d DN	324	status = "disabled";
	325	};
	326
681a5c71	327	nand: nand-controller@ffb90000 {
67c9fd2d DN	328	#address-cells = <1>;
	329	#size-cells = <0>;
	330	compatible = "altr,socfpga-denali-nand";
	331	reg = <0xffb90000 0x10000>,
	332	<0xffb80000 0x1000>;
	333	reg-names = "nand_data", "denali_reg";
	334	interrupts = <0 97 4>;
	335	clocks = <&clkmgr STRATIX10_NAND_CLK>,
	336	<&clkmgr STRATIX10_NAND_X_CLK>,
	337	<&clkmgr STRATIX10_NAND_ECC_CLK>;
	338	clock-names = "nand", "nand_x", "ecc";
	339	resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
	340	status = "disabled";
	341	};
	342
78cd6a9d DN	343	ocram: sram@ffe00000 {
	344	compatible = "mmio-sram";
	345	reg = <0xffe00000 0x100000>;
6de298ff DN	346	#address-cells = <1>;
	347	#size-cells = <1>;
	348	ranges = <0 0xffe00000 0x100000>;
78cd6a9d DN	349	};
78cd6a9d DN	350
180be1b7	351	pdma: dma-controller@ffda0000 {
ab50a444 GM	352	compatible = "arm,pl330", "arm,primecell";
	353	reg = <0xffda0000 0x1000>;
	354	interrupts = <0 81 4>,
	355	<0 82 4>,
	356	<0 83 4>,
	357	<0 84 4>,
	358	<0 85 4>,
	359	<0 86 4>,
	360	<0 87 4>,
	361	<0 88 4>,
	362	<0 89 4>;
	363	#dma-cells = <1>;
ab50a444 GM	364	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
ab50a444 GM	365	clock-names = "apb_pclk";
e10c1848 DN	366	resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
e10c1848 DN	367	reset-names = "dma", "dma-ocp";
ab50a444 GM	368	};
ab50a444 GM	369
21ab7031 DN	370	pinctrl0: pinctrl@ffd13000 {
	371	compatible = "pinctrl-single";
	372	reg = <0xffd13000 0xA0>;
	373	#pinctrl-cells = <1>;
	374	pinctrl-single,register-width = <32>;
	375	pinctrl-single,function-mask = <0x0000000f>;
	376	};
	377
	378	pinctrl1: pinctrl@ffd13100 {
	379	compatible = "pinctrl-single";
	380	reg = <0xffd13100 0x20>;
	381	#pinctrl-cells = <1>;
	382	pinctrl-single,register-width = <32>;
	383	pinctrl-single,function-mask = <0x0000000f>;
	384	};
	385
78cd6a9d DN	386	rst: rstmgr@ffd11000 {
78cd6a9d DN	387	#reset-cells = <1>;
8bb4f3f5	388	compatible = "altr,stratix10-rst-mgr";
78cd6a9d DN	389	reg = <0xffd11000 0x1000>;
	390	};
	391
ae3f46c8 TT	392	smmu: iommu@fa000000 {
	393	compatible = "arm,mmu-500", "arm,smmu-v2";
	394	reg = <0xfa000000 0x40000>;
	395	#global-interrupts = <2>;
	396	#iommu-cells = <1>;
	397	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
	398	clock-names = "iommu";
	399	interrupt-parent = <&intc>;
	400	interrupts = <0 128 4>, /* Global Secure Fault */
	401	<0 129 4>, /* Global Non-secure Fault */
	402	/* Non-secure Context Interrupts (32) */
	403	<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
	404	<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
	405	<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
	406	<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
	407	<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
	408	<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
	409	<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
	410	<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
	411	stream-match-mask = <0x7ff0>;
	412	status = "disabled";
	413	};
	414
78cd6a9d DN	415	spi0: spi@ffda4000 {
	416	compatible = "snps,dw-apb-ssi";
	417	#address-cells = <1>;
	418	#size-cells = <0>;
	419	reg = <0xffda4000 0x1000>;
889d1509 TT	420	interrupts = <0 99 4>;
889d1509 TT	421	resets = <&rst SPIM0_RESET>;
0ef91ccd	422	reset-names = "spi";
889d1509	423	reg-io-width = <4>;
4595299c	424	num-cs = <4>;
70455ac7	425	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
78cd6a9d DN	426	status = "disabled";
	427	};
	428
	429	spi1: spi@ffda5000 {
	430	compatible = "snps,dw-apb-ssi";
	431	#address-cells = <1>;
	432	#size-cells = <0>;
	433	reg = <0xffda5000 0x1000>;
889d1509 TT	434	interrupts = <0 100 4>;
889d1509 TT	435	resets = <&rst SPIM1_RESET>;
0ef91ccd	436	reset-names = "spi";
889d1509	437	reg-io-width = <4>;
4595299c	438	num-cs = <4>;
70455ac7	439	clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
78cd6a9d DN	440	status = "disabled";
	441	};
	442
	443	sysmgr: sysmgr@ffd12000 {
8f4ebe9b	444	compatible = "altr,sys-mgr-s10","altr,sys-mgr";
74121b9a	445	reg = <0xffd12000 0x228>;
78cd6a9d DN	446	};
78cd6a9d DN	447
78cd6a9d DN	448	timer0: timer0@ffc03000 {
	449	compatible = "snps,dw-apb-timer";
	450	interrupts = <0 113 4>;
	451	reg = <0xffc03000 0x100>;
d93101ab DN	452	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	453	clock-names = "timer";
78cd6a9d DN	454	};
	455
	456	timer1: timer1@ffc03100 {
	457	compatible = "snps,dw-apb-timer";
	458	interrupts = <0 114 4>;
	459	reg = <0xffc03100 0x100>;
d93101ab DN	460	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	461	clock-names = "timer";
78cd6a9d DN	462	};
	463
	464	timer2: timer2@ffd00000 {
	465	compatible = "snps,dw-apb-timer";
	466	interrupts = <0 115 4>;
	467	reg = <0xffd00000 0x100>;
d93101ab DN	468	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	469	clock-names = "timer";
78cd6a9d DN	470	};
	471
	472	timer3: timer3@ffd00100 {
	473	compatible = "snps,dw-apb-timer";
	474	interrupts = <0 116 4>;
	475	reg = <0xffd00100 0x100>;
d93101ab DN	476	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
d93101ab DN	477	clock-names = "timer";
78cd6a9d DN	478	};
78cd6a9d DN	479
681a5c71	480	uart0: serial@ffc02000 {
78cd6a9d DN	481	compatible = "snps,dw-apb-uart";
	482	reg = <0xffc02000 0x100>;
	483	interrupts = <0 108 4>;
	484	reg-shift = <2>;
	485	reg-io-width = <4>;
788251fa	486	resets = <&rst UART0_RESET>;
d93101ab	487	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	488	status = "disabled";
	489	};
	490
681a5c71	491	uart1: serial@ffc02100 {
78cd6a9d DN	492	compatible = "snps,dw-apb-uart";
	493	reg = <0xffc02100 0x100>;
	494	interrupts = <0 109 4>;
	495	reg-shift = <2>;
	496	reg-io-width = <4>;
788251fa	497	resets = <&rst UART1_RESET>;
d93101ab	498	clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
78cd6a9d DN	499	status = "disabled";
	500	};
	501
78cd6a9d DN	502	usb0: usb@ffb00000 {
	503	compatible = "snps,dwc2";
	504	reg = <0xffb00000 0x40000>;
	505	interrupts = <0 93 4>;
	506	phys = <&usbphy0>;
	507	phy-names = "usb2-phy";
33af8ca0 DN	508	resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
33af8ca0 DN	509	reset-names = "dwc2", "dwc2-ecc";
03761ab1	510	clocks = <&clkmgr STRATIX10_USB_CLK>;
4b557e17	511	clock-names = "otg";
ae3f46c8	512	iommus = <&smmu 6>;
78cd6a9d DN	513	status = "disabled";
	514	};
	515
	516	usb1: usb@ffb40000 {
	517	compatible = "snps,dwc2";
	518	reg = <0xffb40000 0x40000>;
	519	interrupts = <0 94 4>;
	520	phys = <&usbphy0>;
	521	phy-names = "usb2-phy";
33af8ca0 DN	522	resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
33af8ca0 DN	523	reset-names = "dwc2", "dwc2-ecc";
03761ab1	524	clocks = <&clkmgr STRATIX10_USB_CLK>;
91b491fd	525	clock-names = "otg";
ae3f46c8	526	iommus = <&smmu 7>;
78cd6a9d DN	527	status = "disabled";
	528	};
	529
	530	watchdog0: watchdog@ffd00200 {
	531	compatible = "snps,dw-wdt";
	532	reg = <0xffd00200 0x100>;
	533	interrupts = <0 117 4>;
788251fa	534	resets = <&rst WATCHDOG0_RESET>;
03761ab1	535	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	536	status = "disabled";
	537	};
	538
	539	watchdog1: watchdog@ffd00300 {
	540	compatible = "snps,dw-wdt";
	541	reg = <0xffd00300 0x100>;
	542	interrupts = <0 118 4>;
788251fa	543	resets = <&rst WATCHDOG1_RESET>;
03761ab1	544	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	545	status = "disabled";
	546	};
	547
	548	watchdog2: watchdog@ffd00400 {
	549	compatible = "snps,dw-wdt";
	550	reg = <0xffd00400 0x100>;
	551	interrupts = <0 125 4>;
788251fa	552	resets = <&rst WATCHDOG2_RESET>;
03761ab1	553	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	554	status = "disabled";
	555	};
	556
	557	watchdog3: watchdog@ffd00500 {
	558	compatible = "snps,dw-wdt";
	559	reg = <0xffd00500 0x100>;
	560	interrupts = <0 126 4>;
788251fa	561	resets = <&rst WATCHDOG3_RESET>;
03761ab1	562	clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
78cd6a9d DN	563	status = "disabled";
78cd6a9d DN	564	};
91fdd827	565
446fd7af TT	566	sdr: sdr@f8011100 {
	567	compatible = "altr,sdr-ctl", "syscon";
	568	reg = <0xf8011100 0xc0>;
	569	};
	570
91fdd827	571	eccmgr {
74676a8e TT	572	compatible = "altr,socfpga-s10-ecc-manager",
74676a8e TT	573	"altr,socfpga-a10-ecc-manager";
3ce078ff TT	574	altr,sysmgr-syscon = <&sysmgr>;
	575	#address-cells = <1>;
	576	#size-cells = <1>;
74676a8e	577	interrupts = <0 15 4>;
91fdd827 TT	578	interrupt-controller;
91fdd827 TT	579	#interrupt-cells = <2>;
3ce078ff	580	ranges;
91fdd827 TT	581
	582	sdramedac {
	583	compatible = "altr,sdram-edac-s10";
446fd7af	584	altr,sdr-syscon = <&sdr>;
74676a8e	585	interrupts = <16 4>;
91fdd827	586	};
6b2da9ff	587
3c4fcb89 TT	588	ocram-ecc@ff8cc000 {
	589	compatible = "altr,socfpga-s10-ocram-ecc",
	590	"altr,socfpga-a10-ocram-ecc";
	591	reg = <0xff8cc000 0x100>;
	592	altr,ecc-parent = <&ocram>;
	593	interrupts = <1 4>;
	594	};
	595
6b2da9ff	596	usb0-ecc@ff8c4000 {
74676a8e TT	597	compatible = "altr,socfpga-s10-usb-ecc",
74676a8e TT	598	"altr,socfpga-usb-ecc";
6b2da9ff TT	599	reg = <0xff8c4000 0x100>;
6b2da9ff TT	600	altr,ecc-parent = <&usb0>;
74676a8e	601	interrupts = <2 4>;
6b2da9ff TT	602	};
	603
	604	emac0-rx-ecc@ff8c0000 {
74676a8e TT	605	compatible = "altr,socfpga-s10-eth-mac-ecc",
74676a8e TT	606	"altr,socfpga-eth-mac-ecc";
6b2da9ff TT	607	reg = <0xff8c0000 0x100>;
6b2da9ff TT	608	altr,ecc-parent = <&gmac0>;
74676a8e	609	interrupts = <4 4>;
6b2da9ff TT	610	};
	611
	612	emac0-tx-ecc@ff8c0400 {
74676a8e TT	613	compatible = "altr,socfpga-s10-eth-mac-ecc",
74676a8e TT	614	"altr,socfpga-eth-mac-ecc";
6b2da9ff TT	615	reg = <0xff8c0400 0x100>;
6b2da9ff TT	616	altr,ecc-parent = <&gmac0>;
74676a8e	617	interrupts = <5 4>;
6b2da9ff TT	618	};
6b2da9ff TT	619
91fdd827	620	};
0cb140d0 TT	621
0cb140d0 TT	622	qspi: spi@ff8d2000 {
85d616dd	623	compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
0cb140d0 TT	624	#address-cells = <1>;
	625	#size-cells = <0>;
	626	reg = <0xff8d2000 0x100>,
	627	<0xff900000 0x100000>;
	628	interrupts = <0 3 4>;
	629	cdns,fifo-depth = <128>;
	630	cdns,fifo-width = <4>;
	631	cdns,trigger-address = <0x00000000>;
	632	clocks = <&qspi_clk>;
	633
	634	status = "disabled";
	635	};
78cd6a9d	636	};
5dad11fa DN	637
	638	usbphy0: usbphy0 {
	639	compatible = "usb-nop-xceiv";
	640	#phy-cells = <0>;
	641	};
78cd6a9d	642	};