Commit | Line | Data |
---|---|---|
ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
8c2c3df3 CM |
2 | config ARM64 |
3 | def_bool y | |
6251d380 | 4 | select ACPI_APMT if ACPI |
b6197b93 | 5 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 6 | select ACPI_GENERIC_GSI if ACPI |
5f1ae4eb | 7 | select ACPI_GTDT if ACPI |
c6bb8f89 | 8 | select ACPI_IORT if ACPI |
6933de0c | 9 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
52146173 | 10 | select ACPI_MCFG if (ACPI && PCI) |
888125a7 | 11 | select ACPI_SPCR_TABLE if ACPI |
0ce82232 | 12 | select ACPI_PPTT if ACPI |
09587a09 | 13 | select ARCH_HAS_DEBUG_WX |
6dd8b1a0 | 14 | select ARCH_BINFMT_ELF_EXTRA_PHDRS |
ab7876a9 | 15 | select ARCH_BINFMT_ELF_STATE |
cd9bc2c9 | 16 | select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE |
1e866974 | 17 | select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION |
91024b3c AK |
18 | select ARCH_ENABLE_MEMORY_HOTPLUG |
19 | select ARCH_ENABLE_MEMORY_HOTREMOVE | |
66f24fa7 | 20 | select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 |
1e866974 | 21 | select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE |
c2280be8 | 22 | select ARCH_HAS_CACHE_LINE_SIZE |
2792d84e | 23 | select ARCH_HAS_CURRENT_STACK_POINTER |
ec6d06ef | 24 | select ARCH_HAS_DEBUG_VIRTUAL |
399145f9 | 25 | select ARCH_HAS_DEBUG_VM_PGTABLE |
13bf5ced | 26 | select ARCH_HAS_DMA_PREP_COHERENT |
38b04a74 | 27 | select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI |
e75bef2a | 28 | select ARCH_HAS_FAST_MULTIPLIER |
6974f0c4 | 29 | select ARCH_HAS_FORTIFY_SOURCE |
957e3fac | 30 | select ARCH_HAS_GCOV_PROFILE_ALL |
4eb0716e | 31 | select ARCH_HAS_GIGANTIC_PAGE |
5e4c7549 | 32 | select ARCH_HAS_KCOV |
71883ae3 | 33 | select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON |
d8ae8a37 | 34 | select ARCH_HAS_KEEPINITRD |
f1e3a12b | 35 | select ARCH_HAS_MEMBARRIER_SYNC_CORE |
6cc9203b | 36 | select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS |
0ebeea8c | 37 | select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE |
73b20c84 | 38 | select ARCH_HAS_PTE_DEVMAP |
3010a5ea | 39 | select ARCH_HAS_PTE_SPECIAL |
71ce1ab5 | 40 | select ARCH_HAS_HW_PTE_YOUNG |
347cb6af | 41 | select ARCH_HAS_SETUP_DMA_OPS |
4739d53f | 42 | select ARCH_HAS_SET_DIRECT_MAP |
d2852a22 | 43 | select ARCH_HAS_SET_MEMORY |
5fc57df2 | 44 | select ARCH_STACKWALK |
ad21fc4f LA |
45 | select ARCH_HAS_STRICT_KERNEL_RWX |
46 | select ARCH_HAS_STRICT_MODULE_RWX | |
886643b7 CH |
47 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
48 | select ARCH_HAS_SYNC_DMA_FOR_CPU | |
4378a7d4 | 49 | select ARCH_HAS_SYSCALL_WRAPPER |
1f85008e | 50 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
63703f37 | 51 | select ARCH_HAS_ZONE_DMA_SET if EXPERT |
ab7876a9 | 52 | select ARCH_HAVE_ELF_PROT |
396a5d4a | 53 | select ARCH_HAVE_NMI_SAFE_CMPXCHG |
d593d64f | 54 | select ARCH_HAVE_TRACE_MMIO_ACCESS |
7ef858da TG |
55 | select ARCH_INLINE_READ_LOCK if !PREEMPTION |
56 | select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION | |
57 | select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION | |
58 | select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION | |
59 | select ARCH_INLINE_READ_UNLOCK if !PREEMPTION | |
60 | select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION | |
61 | select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION | |
62 | select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION | |
63 | select ARCH_INLINE_WRITE_LOCK if !PREEMPTION | |
64 | select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION | |
65 | select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION | |
66 | select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION | |
67 | select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION | |
68 | select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION | |
69 | select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION | |
70 | select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION | |
71 | select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION | |
72 | select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION | |
73 | select ARCH_INLINE_SPIN_LOCK if !PREEMPTION | |
74 | select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION | |
75 | select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION | |
76 | select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION | |
77 | select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION | |
78 | select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION | |
79 | select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION | |
80 | select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION | |
350e88ba | 81 | select ARCH_KEEP_MEMBLOCK |
04d5ea46 | 82 | select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE |
c63c8700 | 83 | select ARCH_USE_CMPXCHG_LOCKREF |
bf7f15c5 | 84 | select ARCH_USE_GNU_PROPERTY |
dce44566 | 85 | select ARCH_USE_MEMTEST |
087133ac | 86 | select ARCH_USE_QUEUED_RWLOCKS |
c1109047 | 87 | select ARCH_USE_QUEUED_SPINLOCKS |
50479d58 | 88 | select ARCH_USE_SYM_ANNOTATIONS |
5d6ad668 | 89 | select ARCH_SUPPORTS_DEBUG_PAGEALLOC |
855f9a8e | 90 | select ARCH_SUPPORTS_HUGETLBFS |
c484f256 | 91 | select ARCH_SUPPORTS_MEMORY_FAILURE |
5287569a | 92 | select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK |
112b6a8e ST |
93 | select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN |
94 | select ARCH_SUPPORTS_LTO_CLANG_THIN | |
9186ad8e | 95 | select ARCH_SUPPORTS_CFI_CLANG |
4badad35 | 96 | select ARCH_SUPPORTS_ATOMIC_RMW |
42a7ba16 | 97 | select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 |
56166230 | 98 | select ARCH_SUPPORTS_NUMA_BALANCING |
42b25471 | 99 | select ARCH_SUPPORTS_PAGE_TABLE_CHECK |
cd7f176a | 100 | select ARCH_SUPPORTS_PER_VMA_LOCK |
43b3dfdd | 101 | select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH |
84c187af | 102 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT |
81c22041 | 103 | select ARCH_WANT_DEFAULT_BPF_JIT |
67f3977f | 104 | select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT |
b6f35981 | 105 | select ARCH_WANT_FRAME_POINTERS |
3876d4a3 | 106 | select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
59612b24 | 107 | select ARCH_WANT_LD_ORPHAN_WARN |
223b5e57 | 108 | select ARCH_WANTS_EXECMEM_LATE if EXECMEM |
51c2ee6d | 109 | select ARCH_WANTS_NO_INSTR |
d0637c50 | 110 | select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES |
918327e9 | 111 | select ARCH_HAS_UBSAN |
25c92a37 | 112 | select ARM_AMBA |
1aee5d7a | 113 | select ARM_ARCH_TIMER |
c4188edc | 114 | select ARM_GIC |
875cbf3e | 115 | select AUDIT_ARCH_COMPAT_GENERIC |
3ee80364 | 116 | select ARM_GIC_V2M if PCI |
021f6537 | 117 | select ARM_GIC_V3 |
3ee80364 | 118 | select ARM_GIC_V3_ITS if PCI |
bff60792 | 119 | select ARM_PSCI_FW |
10916706 | 120 | select BUILDTIME_TABLE_SORT |
db2789b5 | 121 | select CLONE_BACKWARDS |
7ca2ef33 | 122 | select COMMON_CLK |
166936ba | 123 | select CPU_PM if (SUSPEND || CPU_IDLE) |
3fbd56f0 | 124 | select CPUMASK_OFFSTACK if NR_CPUS > 256 |
7481cddf | 125 | select CRC32 |
7bc13fd3 | 126 | select DCACHE_WORD_ACCESS |
cfce092d | 127 | select DYNAMIC_FTRACE if FUNCTION_TRACER |
1c1a429e | 128 | select DMA_BOUNCE_UNALIGNED_KMALLOC |
0c3b3171 | 129 | select DMA_DIRECT_REMAP |
ef37566c | 130 | select EDAC_SUPPORT |
2f34f173 | 131 | select FRAME_POINTER |
47a15aa5 | 132 | select FUNCTION_ALIGNMENT_4B |
baaf553d | 133 | select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS |
d4932f9e | 134 | select GENERIC_ALLOCATOR |
2ef7a295 | 135 | select GENERIC_ARCH_TOPOLOGY |
4b3dc967 | 136 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 137 | select GENERIC_CPU_AUTOPROBE |
d127db1a | 138 | select GENERIC_CPU_DEVICES |
61ae1321 | 139 | select GENERIC_CPU_VULNERABILITIES |
bf4b558e | 140 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 141 | select GENERIC_IDLE_POLL_SETUP |
f23eab0b | 142 | select GENERIC_IOREMAP |
d3afc7f1 | 143 | select GENERIC_IRQ_IPI |
8c2c3df3 CM |
144 | select GENERIC_IRQ_PROBE |
145 | select GENERIC_IRQ_SHOW | |
6544e67b | 146 | select GENERIC_IRQ_SHOW_LEVEL |
6585bd82 | 147 | select GENERIC_LIB_DEVMEM_IS_ALLOWED |
cb61f676 | 148 | select GENERIC_PCI_IOMAP |
102f45fd | 149 | select GENERIC_PTDUMP |
65cd4f6c | 150 | select GENERIC_SCHED_CLOCK |
8c2c3df3 CM |
151 | select GENERIC_SMP_IDLE_THREAD |
152 | select GENERIC_TIME_VSYSCALL | |
28b1a824 | 153 | select GENERIC_GETTIMEOFDAY |
9614cc57 | 154 | select GENERIC_VDSO_TIME_NS |
8c2c3df3 | 155 | select HARDIRQS_SW_RESEND |
fcbfe812 | 156 | select HAS_IOPORT |
45544eee | 157 | select HAVE_MOVE_PMD |
f5308c89 | 158 | select HAVE_MOVE_PUD |
eb01d42a | 159 | select HAVE_PCI |
9f9a35a7 | 160 | select HAVE_ACPI_APEI if (ACPI && EFI) |
2a19be61 | 161 | select HAVE_ALIGNED_STRUCT_PAGE |
875cbf3e | 162 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 163 | select HAVE_ARCH_BITREVERSE |
689eae42 | 164 | select HAVE_ARCH_COMPILER_H |
e9207223 | 165 | select HAVE_ARCH_HUGE_VMALLOC |
324420bf | 166 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 167 | select HAVE_ARCH_JUMP_LABEL |
c296146c | 168 | select HAVE_ARCH_JUMP_LABEL_RELATIVE |
0383808e | 169 | select HAVE_ARCH_KASAN |
71b613fc | 170 | select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN |
2d4acb90 | 171 | select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN |
94ab5b61 | 172 | select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) |
dd03762a KW |
173 | # Some instrumentation may be unsound, hence EXPERT |
174 | select HAVE_ARCH_KCSAN if EXPERT | |
840b2398 | 175 | select HAVE_ARCH_KFENCE |
9529247d | 176 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
177 | select HAVE_ARCH_MMAP_RND_BITS |
178 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
271ca788 | 179 | select HAVE_ARCH_PREL32_RELOCATIONS |
70918779 | 180 | select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET |
a1ae65b2 | 181 | select HAVE_ARCH_SECCOMP_FILTER |
0b3e3366 | 182 | select HAVE_ARCH_STACKLEAK |
9e8084d3 | 183 | select HAVE_ARCH_THREAD_STRUCT_WHITELIST |
8c2c3df3 | 184 | select HAVE_ARCH_TRACEHOOK |
8ee70879 | 185 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
e3067861 | 186 | select HAVE_ARCH_VMAP_STACK |
8ee70879 | 187 | select HAVE_ARM_SMCCC |
2ff2b7ec | 188 | select HAVE_ASM_MODVERSIONS |
6077776b | 189 | select HAVE_EBPF_JIT |
af64d2aa | 190 | select HAVE_C_RECORDMCOUNT |
5284e1b4 | 191 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 192 | select HAVE_CMPXCHG_LOCAL |
24a9c541 | 193 | select HAVE_CONTEXT_TRACKING_USER |
b69ec42b | 194 | select HAVE_DEBUG_KMEMLEAK |
6ac2104d | 195 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 196 | select HAVE_DYNAMIC_FTRACE |
2aa6ac03 FR |
197 | select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ |
198 | if $(cc-option,-fpatchable-function-entry=2) | |
199 | select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ | |
200 | if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS | |
baaf553d | 201 | select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ |
b3f11af9 | 202 | if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ |
a743f26d | 203 | (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) |
a31d793d | 204 | select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ |
26299b3f | 205 | if DYNAMIC_FTRACE_WITH_ARGS |
8c3526fb FR |
206 | select HAVE_SAMPLE_FTRACE_DIRECT |
207 | select HAVE_SAMPLE_FTRACE_DIRECT_MULTI | |
50afc33a | 208 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
25176ad0 | 209 | select HAVE_GUP_FAST |
af64d2aa | 210 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 | 211 | select HAVE_FUNCTION_TRACER |
42d038c4 | 212 | select HAVE_FUNCTION_ERROR_INJECTION |
36469703 | 213 | select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER |
819e50e2 | 214 | select HAVE_FUNCTION_GRAPH_TRACER |
6b90bd4b | 215 | select HAVE_GCC_PLUGINS |
d7a0fe9e DA |
216 | select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ |
217 | HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI | |
8c2c3df3 | 218 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
893dea9c | 219 | select HAVE_IOREMAP_PROT |
24da208d | 220 | select HAVE_IRQ_TIME_ACCOUNTING |
ea3752ba | 221 | select HAVE_MOD_ARCH_SPECIFIC |
396a5d4a | 222 | select HAVE_NMI |
8c2c3df3 | 223 | select HAVE_PERF_EVENTS |
d7a0fe9e | 224 | select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI |
2ee0d7fd JP |
225 | select HAVE_PERF_REGS |
226 | select HAVE_PERF_USER_STACK_DUMP | |
1b2d3451 | 227 | select HAVE_PREEMPT_DYNAMIC_KEY |
0a8ea52c | 228 | select HAVE_REGS_AND_STACK_ACCESS_API |
a68773bd | 229 | select HAVE_POSIX_CPU_TIMERS_TASK_WORK |
a823c35f | 230 | select HAVE_FUNCTION_ARG_ACCESS_API |
ff2e6d72 | 231 | select MMU_GATHER_RCU_TABLE_FREE |
409d5db4 | 232 | select HAVE_RSEQ |
724a75ac | 233 | select HAVE_RUST if CPU_LITTLE_ENDIAN |
d148eac0 | 234 | select HAVE_STACKPROTECTOR |
055b1212 | 235 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 236 | select HAVE_KPROBES |
cd1ee3b1 | 237 | select HAVE_KRETPROBES |
28b1a824 | 238 | select HAVE_GENERIC_VDSO |
b3091f17 | 239 | select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU |
8c2c3df3 | 240 | select IRQ_DOMAIN |
e8557d1f | 241 | select IRQ_FORCED_THREADING |
f6f37d93 | 242 | select KASAN_VMALLOC if KASAN |
ae870a68 | 243 | select LOCK_MM_AND_FIND_VMA |
fea2acaa | 244 | select MODULES_USE_ELF_RELA |
f616ab59 | 245 | select NEED_DMA_MAP_STATE |
86596f0a | 246 | select NEED_SG_DMA_LENGTH |
8c2c3df3 CM |
247 | select OF |
248 | select OF_EARLY_FLATTREE | |
2eac9c2d | 249 | select PCI_DOMAINS_GENERIC if PCI |
52146173 | 250 | select PCI_ECAM if (ACPI && PCI) |
20f1b79d | 251 | select PCI_SYSCALL if PCI |
aa1e8ec1 CM |
252 | select POWER_RESET |
253 | select POWER_SUPPLY | |
8c2c3df3 | 254 | select SPARSE_IRQ |
09230cbc | 255 | select SWIOTLB |
7ac57a89 | 256 | select SYSCTL_EXCEPTION_TRACE |
c02433dd | 257 | select THREAD_INFO_IN_TASK |
7677f7fd | 258 | select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD |
5b32510a | 259 | select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD |
4aae683f | 260 | select TRACE_IRQFLAGS_SUPPORT |
3381da25 | 261 | select TRACE_IRQFLAGS_NMI_SUPPORT |
8eb858c4 | 262 | select HAVE_SOFTIRQ_ON_OWN_STACK |
410e471f | 263 | select USER_STACKTRACE_SUPPORT |
8c2c3df3 CM |
264 | help |
265 | ARM 64-bit (AArch64) Linux support. | |
266 | ||
26299b3f | 267 | config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 NC |
268 | def_bool CC_IS_CLANG |
269 | # https://github.com/ClangBuiltLinux/linux/issues/1507 | |
270 | depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) | |
26299b3f | 271 | select HAVE_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 | 272 | |
26299b3f | 273 | config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 NC |
274 | def_bool CC_IS_GCC |
275 | depends on $(cc-option,-fpatchable-function-entry=2) | |
26299b3f | 276 | select HAVE_DYNAMIC_FTRACE_WITH_ARGS |
45bd8951 | 277 | |
8c2c3df3 CM |
278 | config 64BIT |
279 | def_bool y | |
280 | ||
8c2c3df3 CM |
281 | config MMU |
282 | def_bool y | |
283 | ||
c0d6de32 | 284 | config ARM64_CONT_PTE_SHIFT |
030c4d24 | 285 | int |
d3e5bab9 AB |
286 | default 5 if PAGE_SIZE_64KB |
287 | default 7 if PAGE_SIZE_16KB | |
030c4d24 MR |
288 | default 4 |
289 | ||
e6765941 GS |
290 | config ARM64_CONT_PMD_SHIFT |
291 | int | |
d3e5bab9 AB |
292 | default 5 if PAGE_SIZE_64KB |
293 | default 5 if PAGE_SIZE_16KB | |
e6765941 GS |
294 | default 4 |
295 | ||
8f0d3aa9 | 296 | config ARCH_MMAP_RND_BITS_MIN |
d3e5bab9 AB |
297 | default 14 if PAGE_SIZE_64KB |
298 | default 16 if PAGE_SIZE_16KB | |
3cb7e662 | 299 | default 18 |
8f0d3aa9 DC |
300 | |
301 | # max bits determined by the following formula: | |
302 | # VA_BITS - PAGE_SHIFT - 3 | |
303 | config ARCH_MMAP_RND_BITS_MAX | |
3cb7e662 JH |
304 | default 19 if ARM64_VA_BITS=36 |
305 | default 24 if ARM64_VA_BITS=39 | |
306 | default 27 if ARM64_VA_BITS=42 | |
307 | default 30 if ARM64_VA_BITS=47 | |
308 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
309 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
310 | default 33 if ARM64_VA_BITS=48 | |
311 | default 14 if ARM64_64K_PAGES | |
312 | default 16 if ARM64_16K_PAGES | |
313 | default 18 | |
8f0d3aa9 DC |
314 | |
315 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
3cb7e662 JH |
316 | default 7 if ARM64_64K_PAGES |
317 | default 9 if ARM64_16K_PAGES | |
318 | default 11 | |
8f0d3aa9 DC |
319 | |
320 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
3cb7e662 | 321 | default 16 |
8f0d3aa9 | 322 | |
ce816fa8 | 323 | config NO_IOPORT_MAP |
d1e6dc91 | 324 | def_bool y if !PCI |
8c2c3df3 CM |
325 | |
326 | config STACKTRACE_SUPPORT | |
327 | def_bool y | |
328 | ||
bf0c4e04 JVS |
329 | config ILLEGAL_POINTER_VALUE |
330 | hex | |
331 | default 0xdead000000000000 | |
332 | ||
8c2c3df3 CM |
333 | config LOCKDEP_SUPPORT |
334 | def_bool y | |
335 | ||
9fb7410f DM |
336 | config GENERIC_BUG |
337 | def_bool y | |
338 | depends on BUG | |
339 | ||
340 | config GENERIC_BUG_RELATIVE_POINTERS | |
341 | def_bool y | |
342 | depends on GENERIC_BUG | |
343 | ||
8c2c3df3 CM |
344 | config GENERIC_HWEIGHT |
345 | def_bool y | |
346 | ||
347 | config GENERIC_CSUM | |
3cb7e662 | 348 | def_bool y |
8c2c3df3 CM |
349 | |
350 | config GENERIC_CALIBRATE_DELAY | |
351 | def_bool y | |
352 | ||
4b3dc967 WD |
353 | config SMP |
354 | def_bool y | |
355 | ||
4cfb3613 AB |
356 | config KERNEL_MODE_NEON |
357 | def_bool y | |
358 | ||
92cc15fc RH |
359 | config FIX_EARLYCON_MEM |
360 | def_bool y | |
361 | ||
9f25e6ad KS |
362 | config PGTABLE_LEVELS |
363 | int | |
21539939 | 364 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad | 365 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
b6d00d47 | 366 | default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) |
9f25e6ad | 367 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 |
44eaacf1 | 368 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
352b0395 | 369 | default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) |
44eaacf1 | 370 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 |
352b0395 | 371 | default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 |
9f25e6ad | 372 | |
9842ceae PA |
373 | config ARCH_SUPPORTS_UPROBES |
374 | def_bool y | |
375 | ||
8f360948 AB |
376 | config ARCH_PROC_KCORE_TEXT |
377 | def_bool y | |
378 | ||
8bf9284d VM |
379 | config BROKEN_GAS_INST |
380 | def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) | |
381 | ||
9df3f508 MR |
382 | config BUILTIN_RETURN_ADDRESS_STRIPS_PAC |
383 | bool | |
384 | # Clang's __builtin_return_adddress() strips the PAC since 12.0.0 | |
fafdea34 | 385 | # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 |
634e4ff9 | 386 | default y if CC_IS_CLANG |
9df3f508 MR |
387 | # GCC's __builtin_return_address() strips the PAC since 11.1.0, |
388 | # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier | |
389 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 | |
390 | default y if CC_IS_GCC && (GCC_VERSION >= 110100) | |
391 | default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) | |
392 | default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) | |
393 | default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) | |
394 | default n | |
395 | ||
6bd1d0be SC |
396 | config KASAN_SHADOW_OFFSET |
397 | hex | |
0fea6e9a | 398 | depends on KASAN_GENERIC || KASAN_SW_TAGS |
352b0395 AB |
399 | default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS |
400 | default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS | |
f4693c27 AB |
401 | default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS |
402 | default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS | |
403 | default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS | |
352b0395 AB |
404 | default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS |
405 | default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS | |
f4693c27 AB |
406 | default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS |
407 | default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS | |
408 | default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS | |
6bd1d0be SC |
409 | default 0xffffffffffffffff |
410 | ||
68c76ad4 AB |
411 | config UNWIND_TABLES |
412 | bool | |
413 | ||
6a377491 | 414 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 | 415 | |
8c2c3df3 CM |
416 | menu "Kernel Features" |
417 | ||
c0a01b84 AP |
418 | menu "ARM errata workarounds via the alternatives framework" |
419 | ||
6df696cd OU |
420 | config AMPERE_ERRATUM_AC03_CPU_38 |
421 | bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" | |
422 | default y | |
423 | help | |
424 | This option adds an alternative code sequence to work around Ampere | |
425 | erratum AC03_CPU_38 on AmpereOne. | |
426 | ||
427 | The affected design reports FEAT_HAFDBS as not implemented in | |
428 | ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 | |
429 | as required by the architecture. The unadvertised HAFDBS | |
430 | implementation suffers from an additional erratum where hardware | |
431 | A/D updates can occur after a PTE has been marked invalid. | |
432 | ||
433 | The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, | |
434 | which avoids enabling unadvertised hardware Access Flag management | |
435 | at stage-2. | |
436 | ||
437 | If unsure, say Y. | |
438 | ||
c9460dcb | 439 | config ARM64_WORKAROUND_CLEAN_CACHE |
bc15cf70 | 440 | bool |
c9460dcb | 441 | |
c0a01b84 AP |
442 | config ARM64_ERRATUM_826319 |
443 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
444 | default y | |
c9460dcb | 445 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
446 | help |
447 | This option adds an alternative code sequence to work around ARM | |
448 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
449 | AXI master interface and an L2 cache. | |
450 | ||
451 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
452 | and is unable to accept a certain write via this interface, it will | |
453 | not progress on read data presented on the read data channel and the | |
454 | system can deadlock. | |
455 | ||
456 | The workaround promotes data cache clean instructions to | |
457 | data cache clean-and-invalidate. | |
458 | Please note that this does not necessarily enable the workaround, | |
459 | as it depends on the alternative framework, which will only patch | |
460 | the kernel if an affected CPU is detected. | |
461 | ||
462 | If unsure, say Y. | |
463 | ||
464 | config ARM64_ERRATUM_827319 | |
465 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
466 | default y | |
c9460dcb | 467 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
468 | help |
469 | This option adds an alternative code sequence to work around ARM | |
470 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
471 | master interface and an L2 cache. | |
472 | ||
473 | Under certain conditions this erratum can cause a clean line eviction | |
474 | to occur at the same time as another transaction to the same address | |
475 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
476 | interconnect reorders the two transactions. | |
477 | ||
478 | The workaround promotes data cache clean instructions to | |
479 | data cache clean-and-invalidate. | |
480 | Please note that this does not necessarily enable the workaround, | |
481 | as it depends on the alternative framework, which will only patch | |
482 | the kernel if an affected CPU is detected. | |
483 | ||
484 | If unsure, say Y. | |
485 | ||
486 | config ARM64_ERRATUM_824069 | |
487 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
488 | default y | |
c9460dcb | 489 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
490 | help |
491 | This option adds an alternative code sequence to work around ARM | |
492 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
493 | to a coherent interconnect. | |
494 | ||
495 | If a Cortex-A53 processor is executing a store or prefetch for | |
496 | write instruction at the same time as a processor in another | |
497 | cluster is executing a cache maintenance operation to the same | |
498 | address, then this erratum might cause a clean cache line to be | |
499 | incorrectly marked as dirty. | |
500 | ||
501 | The workaround promotes data cache clean instructions to | |
502 | data cache clean-and-invalidate. | |
503 | Please note that this option does not necessarily enable the | |
504 | workaround, as it depends on the alternative framework, which will | |
505 | only patch the kernel if an affected CPU is detected. | |
506 | ||
507 | If unsure, say Y. | |
508 | ||
509 | config ARM64_ERRATUM_819472 | |
510 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
511 | default y | |
c9460dcb | 512 | select ARM64_WORKAROUND_CLEAN_CACHE |
c0a01b84 AP |
513 | help |
514 | This option adds an alternative code sequence to work around ARM | |
515 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
516 | present when it is connected to a coherent interconnect. | |
517 | ||
518 | If the processor is executing a load and store exclusive sequence at | |
519 | the same time as a processor in another cluster is executing a cache | |
520 | maintenance operation to the same address, then this erratum might | |
521 | cause data corruption. | |
522 | ||
523 | The workaround promotes data cache clean instructions to | |
524 | data cache clean-and-invalidate. | |
525 | Please note that this does not necessarily enable the workaround, | |
526 | as it depends on the alternative framework, which will only patch | |
527 | the kernel if an affected CPU is detected. | |
528 | ||
529 | If unsure, say Y. | |
530 | ||
531 | config ARM64_ERRATUM_832075 | |
532 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
533 | default y | |
534 | help | |
535 | This option adds an alternative code sequence to work around ARM | |
536 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
537 | ||
538 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
539 | instructions to Write-Back memory are mixed with Device loads. | |
540 | ||
541 | The workaround is to promote device loads to use Load-Acquire | |
542 | semantics. | |
543 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
544 | as it depends on the alternative framework, which will only patch |
545 | the kernel if an affected CPU is detected. | |
546 | ||
547 | If unsure, say Y. | |
548 | ||
549 | config ARM64_ERRATUM_834220 | |
8c10cc10 | 550 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" |
498cd5c3 | 551 | depends on KVM |
498cd5c3 MZ |
552 | help |
553 | This option adds an alternative code sequence to work around ARM | |
554 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
555 | ||
556 | Affected Cortex-A57 parts might report a Stage 2 translation | |
557 | fault as the result of a Stage 1 fault for load crossing a | |
558 | page boundary when there is a permission or device memory | |
559 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
560 | ||
561 | The workaround is to verify that the Stage 1 translation | |
562 | doesn't generate a fault before handling the Stage 2 fault. | |
563 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
564 | as it depends on the alternative framework, which will only patch |
565 | the kernel if an affected CPU is detected. | |
566 | ||
8c10cc10 | 567 | If unsure, say N. |
c0a01b84 | 568 | |
44b3834b JM |
569 | config ARM64_ERRATUM_1742098 |
570 | bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" | |
571 | depends on COMPAT | |
572 | default y | |
573 | help | |
574 | This option removes the AES hwcap for aarch32 user-space to | |
575 | workaround erratum 1742098 on Cortex-A57 and Cortex-A72. | |
576 | ||
577 | Affected parts may corrupt the AES state if an interrupt is | |
578 | taken between a pair of AES instructions. These instructions | |
579 | are only present if the cryptography extensions are present. | |
580 | All software should have a fallback implementation for CPUs | |
581 | that don't implement the cryptography extensions. | |
582 | ||
583 | If unsure, say Y. | |
584 | ||
905e8c5d WD |
585 | config ARM64_ERRATUM_845719 |
586 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
587 | depends on COMPAT | |
588 | default y | |
589 | help | |
590 | This option adds an alternative code sequence to work around ARM | |
591 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
592 | ||
593 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
594 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
595 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
596 | might return incorrect data. | |
597 | ||
598 | The workaround is to write the contextidr_el1 register on exception | |
599 | return to a 32-bit task. | |
600 | Please note that this does not necessarily enable the workaround, | |
601 | as it depends on the alternative framework, which will only patch | |
602 | the kernel if an affected CPU is detected. | |
603 | ||
604 | If unsure, say Y. | |
605 | ||
df057cc7 WD |
606 | config ARM64_ERRATUM_843419 |
607 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
df057cc7 WD |
608 | default y |
609 | help | |
6ffe9923 | 610 | This option links the kernel with '--fix-cortex-a53-843419' and |
a257e025 AB |
611 | enables PLT support to replace certain ADRP instructions, which can |
612 | cause subsequent memory accesses to use an incorrect address on | |
613 | Cortex-A53 parts up to r0p4. | |
df057cc7 WD |
614 | |
615 | If unsure, say Y. | |
616 | ||
987fdfec MY |
617 | config ARM64_LD_HAS_FIX_ERRATUM_843419 |
618 | def_bool $(ld-option,--fix-cortex-a53-843419) | |
619 | ||
ece1397c SP |
620 | config ARM64_ERRATUM_1024718 |
621 | bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" | |
622 | default y | |
623 | help | |
bc15cf70 | 624 | This option adds a workaround for ARM Cortex-A55 Erratum 1024718. |
ece1397c | 625 | |
c0b15c25 | 626 | Affected Cortex-A55 cores (all revisions) could cause incorrect |
ece1397c | 627 | update of the hardware dirty bit when the DBM/AP bits are updated |
bc15cf70 | 628 | without a break-before-make. The workaround is to disable the usage |
ece1397c | 629 | of hardware DBM locally on the affected cores. CPUs not affected by |
bc15cf70 | 630 | this erratum will continue to use the feature. |
df057cc7 WD |
631 | |
632 | If unsure, say Y. | |
633 | ||
a5325089 | 634 | config ARM64_ERRATUM_1418040 |
6989303a | 635 | bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" |
95b861a4 | 636 | default y |
c2b5bba3 | 637 | depends on COMPAT |
95b861a4 | 638 | help |
24cf262d | 639 | This option adds a workaround for ARM Cortex-A76/Neoverse-N1 |
a5325089 | 640 | errata 1188873 and 1418040. |
95b861a4 | 641 | |
a5325089 | 642 | Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could |
6989303a MZ |
643 | cause register corruption when accessing the timer registers |
644 | from AArch32 userspace. | |
95b861a4 MZ |
645 | |
646 | If unsure, say Y. | |
647 | ||
02ab1f50 | 648 | config ARM64_WORKAROUND_SPECULATIVE_AT |
e85d68fa SP |
649 | bool |
650 | ||
a457b0f7 | 651 | config ARM64_ERRATUM_1165522 |
02ab1f50 | 652 | bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" |
a457b0f7 | 653 | default y |
02ab1f50 | 654 | select ARM64_WORKAROUND_SPECULATIVE_AT |
a457b0f7 | 655 | help |
bc15cf70 | 656 | This option adds a workaround for ARM Cortex-A76 erratum 1165522. |
a457b0f7 MZ |
657 | |
658 | Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with | |
659 | corrupted TLBs by speculating an AT instruction during a guest | |
660 | context switch. | |
661 | ||
662 | If unsure, say Y. | |
663 | ||
02ab1f50 AS |
664 | config ARM64_ERRATUM_1319367 |
665 | bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" | |
666 | default y | |
667 | select ARM64_WORKAROUND_SPECULATIVE_AT | |
668 | help | |
669 | This option adds work arounds for ARM Cortex-A57 erratum 1319537 | |
670 | and A72 erratum 1319367 | |
671 | ||
672 | Cortex-A57 and A72 cores could end-up with corrupted TLBs by | |
673 | speculating an AT instruction during a guest context switch. | |
674 | ||
675 | If unsure, say Y. | |
676 | ||
275fa0ea | 677 | config ARM64_ERRATUM_1530923 |
02ab1f50 | 678 | bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" |
275fa0ea | 679 | default y |
02ab1f50 | 680 | select ARM64_WORKAROUND_SPECULATIVE_AT |
275fa0ea SP |
681 | help |
682 | This option adds a workaround for ARM Cortex-A55 erratum 1530923. | |
683 | ||
684 | Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with | |
685 | corrupted TLBs by speculating an AT instruction during a guest | |
686 | context switch. | |
687 | ||
688 | If unsure, say Y. | |
a457b0f7 | 689 | |
ebcea694 GU |
690 | config ARM64_WORKAROUND_REPEAT_TLBI |
691 | bool | |
692 | ||
171df580 | 693 | config ARM64_ERRATUM_2441007 |
8c10cc10 | 694 | bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" |
171df580 JM |
695 | select ARM64_WORKAROUND_REPEAT_TLBI |
696 | help | |
697 | This option adds a workaround for ARM Cortex-A55 erratum #2441007. | |
698 | ||
699 | Under very rare circumstances, affected Cortex-A55 CPUs | |
700 | may not handle a race between a break-before-make sequence on one | |
701 | CPU, and another CPU accessing the same page. This could allow a | |
702 | store to a page that has been unmapped. | |
703 | ||
704 | Work around this by adding the affected CPUs to the list that needs | |
705 | TLB sequences to be done twice. | |
706 | ||
8c10cc10 | 707 | If unsure, say N. |
171df580 | 708 | |
ce8c80c5 | 709 | config ARM64_ERRATUM_1286807 |
8c10cc10 | 710 | bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" |
ce8c80c5 CM |
711 | select ARM64_WORKAROUND_REPEAT_TLBI |
712 | help | |
bc15cf70 | 713 | This option adds a workaround for ARM Cortex-A76 erratum 1286807. |
ce8c80c5 CM |
714 | |
715 | On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual | |
716 | address for a cacheable mapping of a location is being | |
717 | accessed by a core while another core is remapping the virtual | |
718 | address to a new physical page using the recommended | |
719 | break-before-make sequence, then under very rare circumstances | |
720 | TLBI+DSB completes before a read using the translation being | |
721 | invalidated has been observed by other observers. The | |
722 | workaround repeats the TLBI+DSB operation. | |
723 | ||
8c10cc10 WD |
724 | If unsure, say N. |
725 | ||
969f5ea6 WD |
726 | config ARM64_ERRATUM_1463225 |
727 | bool "Cortex-A76: Software Step might prevent interrupt recognition" | |
728 | default y | |
729 | help | |
730 | This option adds a workaround for Arm Cortex-A76 erratum 1463225. | |
731 | ||
732 | On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping | |
733 | of a system call instruction (SVC) can prevent recognition of | |
734 | subsequent interrupts when software stepping is disabled in the | |
735 | exception handler of the system call and either kernel debugging | |
736 | is enabled or VHE is in use. | |
737 | ||
738 | Work around the erratum by triggering a dummy step exception | |
739 | when handling a system call from a task that is being stepped | |
740 | in a VHE configuration of the kernel. | |
741 | ||
742 | If unsure, say Y. | |
743 | ||
05460849 | 744 | config ARM64_ERRATUM_1542419 |
8c10cc10 | 745 | bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" |
05460849 JM |
746 | help |
747 | This option adds a workaround for ARM Neoverse-N1 erratum | |
748 | 1542419. | |
749 | ||
750 | Affected Neoverse-N1 cores could execute a stale instruction when | |
751 | modified by another CPU. The workaround depends on a firmware | |
752 | counterpart. | |
753 | ||
754 | Workaround the issue by hiding the DIC feature from EL0. This | |
755 | forces user-space to perform cache maintenance. | |
756 | ||
8c10cc10 | 757 | If unsure, say N. |
05460849 | 758 | |
96d389ca RH |
759 | config ARM64_ERRATUM_1508412 |
760 | bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" | |
761 | default y | |
762 | help | |
763 | This option adds a workaround for Arm Cortex-A77 erratum 1508412. | |
764 | ||
765 | Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence | |
766 | of a store-exclusive or read of PAR_EL1 and a load with device or | |
767 | non-cacheable memory attributes. The workaround depends on a firmware | |
768 | counterpart. | |
769 | ||
770 | KVM guests must also have the workaround implemented or they can | |
771 | deadlock the system. | |
772 | ||
773 | Work around the issue by inserting DMB SY barriers around PAR_EL1 | |
774 | register reads and warning KVM users. The DMB barrier is sufficient | |
775 | to prevent a speculative PAR_EL1 read. | |
776 | ||
777 | If unsure, say Y. | |
778 | ||
b9d216fc SP |
779 | config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE |
780 | bool | |
781 | ||
297ae1eb JM |
782 | config ARM64_ERRATUM_2051678 |
783 | bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" | |
a4b92ceb | 784 | default y |
297ae1eb JM |
785 | help |
786 | This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. | |
0ff74a23 | 787 | Affected Cortex-A510 might not respect the ordering rules for |
297ae1eb JM |
788 | hardware update of the page table's dirty bit. The workaround |
789 | is to not enable the feature on affected CPUs. | |
790 | ||
791 | If unsure, say Y. | |
792 | ||
1dd498e5 JM |
793 | config ARM64_ERRATUM_2077057 |
794 | bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" | |
4c11113c | 795 | default y |
1dd498e5 JM |
796 | help |
797 | This option adds the workaround for ARM Cortex-A510 erratum 2077057. | |
798 | Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is | |
799 | expected, but a Pointer Authentication trap is taken instead. The | |
800 | erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow | |
801 | EL1 to cause a return to EL2 with a guest controlled ELR_EL2. | |
802 | ||
803 | This can only happen when EL2 is stepping EL1. | |
804 | ||
805 | When these conditions occur, the SPSR_EL2 value is unchanged from the | |
806 | previous guest entry, and can be restored from the in-memory copy. | |
807 | ||
808 | If unsure, say Y. | |
809 | ||
1bdb0fbb JM |
810 | config ARM64_ERRATUM_2658417 |
811 | bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" | |
812 | default y | |
813 | help | |
814 | This option adds the workaround for ARM Cortex-A510 erratum 2658417. | |
815 | Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for | |
816 | BFMMLA or VMMLA instructions in rare circumstances when a pair of | |
817 | A510 CPUs are using shared neon hardware. As the sharing is not | |
818 | discoverable by the kernel, hide the BF16 HWCAP to indicate that | |
819 | user-space should not be using these instructions. | |
820 | ||
821 | If unsure, say Y. | |
822 | ||
b9d216fc | 823 | config ARM64_ERRATUM_2119858 |
eb30d838 | 824 | bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" |
b9d216fc | 825 | default y |
b9d216fc SP |
826 | depends on CORESIGHT_TRBE |
827 | select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE | |
828 | help | |
eb30d838 | 829 | This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. |
b9d216fc | 830 | |
eb30d838 | 831 | Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace |
b9d216fc SP |
832 | data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in |
833 | the event of a WRAP event. | |
834 | ||
835 | Work around the issue by always making sure we move the TRBPTR_EL1 by | |
836 | 256 bytes before enabling the buffer and filling the first 256 bytes of | |
837 | the buffer with ETM ignore packets upon disabling. | |
838 | ||
839 | If unsure, say Y. | |
840 | ||
841 | config ARM64_ERRATUM_2139208 | |
842 | bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" | |
843 | default y | |
b9d216fc SP |
844 | depends on CORESIGHT_TRBE |
845 | select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE | |
846 | help | |
847 | This option adds the workaround for ARM Neoverse-N2 erratum 2139208. | |
848 | ||
849 | Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace | |
850 | data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in | |
851 | the event of a WRAP event. | |
852 | ||
853 | Work around the issue by always making sure we move the TRBPTR_EL1 by | |
854 | 256 bytes before enabling the buffer and filling the first 256 bytes of | |
855 | the buffer with ETM ignore packets upon disabling. | |
856 | ||
857 | If unsure, say Y. | |
858 | ||
fa82d0b4 SP |
859 | config ARM64_WORKAROUND_TSB_FLUSH_FAILURE |
860 | bool | |
861 | ||
862 | config ARM64_ERRATUM_2054223 | |
863 | bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" | |
864 | default y | |
865 | select ARM64_WORKAROUND_TSB_FLUSH_FAILURE | |
866 | help | |
867 | Enable workaround for ARM Cortex-A710 erratum 2054223 | |
868 | ||
869 | Affected cores may fail to flush the trace data on a TSB instruction, when | |
870 | the PE is in trace prohibited state. This will cause losing a few bytes | |
871 | of the trace cached. | |
872 | ||
873 | Workaround is to issue two TSB consecutively on affected cores. | |
874 | ||
875 | If unsure, say Y. | |
876 | ||
877 | config ARM64_ERRATUM_2067961 | |
878 | bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" | |
879 | default y | |
880 | select ARM64_WORKAROUND_TSB_FLUSH_FAILURE | |
881 | help | |
882 | Enable workaround for ARM Neoverse-N2 erratum 2067961 | |
883 | ||
884 | Affected cores may fail to flush the trace data on a TSB instruction, when | |
885 | the PE is in trace prohibited state. This will cause losing a few bytes | |
886 | of the trace cached. | |
887 | ||
888 | Workaround is to issue two TSB consecutively on affected cores. | |
889 | ||
890 | If unsure, say Y. | |
891 | ||
8d81b2a3 SP |
892 | config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE |
893 | bool | |
894 | ||
895 | config ARM64_ERRATUM_2253138 | |
896 | bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" | |
8d81b2a3 SP |
897 | depends on CORESIGHT_TRBE |
898 | default y | |
899 | select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE | |
900 | help | |
901 | This option adds the workaround for ARM Neoverse-N2 erratum 2253138. | |
902 | ||
903 | Affected Neoverse-N2 cores might write to an out-of-range address, not reserved | |
904 | for TRBE. Under some conditions, the TRBE might generate a write to the next | |
905 | virtually addressed page following the last page of the TRBE address space | |
906 | (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. | |
907 | ||
908 | Work around this in the driver by always making sure that there is a | |
909 | page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. | |
910 | ||
911 | If unsure, say Y. | |
912 | ||
913 | config ARM64_ERRATUM_2224489 | |
eb30d838 | 914 | bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" |
8d81b2a3 SP |
915 | depends on CORESIGHT_TRBE |
916 | default y | |
917 | select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE | |
918 | help | |
eb30d838 | 919 | This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. |
8d81b2a3 | 920 | |
eb30d838 | 921 | Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved |
8d81b2a3 SP |
922 | for TRBE. Under some conditions, the TRBE might generate a write to the next |
923 | virtually addressed page following the last page of the TRBE address space | |
924 | (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. | |
925 | ||
926 | Work around this in the driver by always making sure that there is a | |
927 | page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. | |
928 | ||
929 | If unsure, say Y. | |
930 | ||
39fdb65f | 931 | config ARM64_ERRATUM_2441009 |
8c10cc10 | 932 | bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" |
39fdb65f JM |
933 | select ARM64_WORKAROUND_REPEAT_TLBI |
934 | help | |
935 | This option adds a workaround for ARM Cortex-A510 erratum #2441009. | |
936 | ||
937 | Under very rare circumstances, affected Cortex-A510 CPUs | |
938 | may not handle a race between a break-before-make sequence on one | |
939 | CPU, and another CPU accessing the same page. This could allow a | |
940 | store to a page that has been unmapped. | |
941 | ||
942 | Work around this by adding the affected CPUs to the list that needs | |
943 | TLB sequences to be done twice. | |
944 | ||
8c10cc10 | 945 | If unsure, say N. |
39fdb65f | 946 | |
607a9afa AK |
947 | config ARM64_ERRATUM_2064142 |
948 | bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" | |
ac0ba210 | 949 | depends on CORESIGHT_TRBE |
607a9afa AK |
950 | default y |
951 | help | |
952 | This option adds the workaround for ARM Cortex-A510 erratum 2064142. | |
953 | ||
954 | Affected Cortex-A510 core might fail to write into system registers after the | |
955 | TRBE has been disabled. Under some conditions after the TRBE has been disabled | |
956 | writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, | |
957 | and TRBTRG_EL1 will be ignored and will not be effected. | |
958 | ||
959 | Work around this in the driver by executing TSB CSYNC and DSB after collection | |
960 | is stopped and before performing a system register write to one of the affected | |
961 | registers. | |
962 | ||
963 | If unsure, say Y. | |
964 | ||
3bd94a87 AK |
965 | config ARM64_ERRATUM_2038923 |
966 | bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" | |
f209e9fe | 967 | depends on CORESIGHT_TRBE |
3bd94a87 AK |
968 | default y |
969 | help | |
970 | This option adds the workaround for ARM Cortex-A510 erratum 2038923. | |
971 | ||
972 | Affected Cortex-A510 core might cause an inconsistent view on whether trace is | |
973 | prohibited within the CPU. As a result, the trace buffer or trace buffer state | |
974 | might be corrupted. This happens after TRBE buffer has been enabled by setting | |
975 | TRBLIMITR_EL1.E, followed by just a single context synchronization event before | |
976 | execution changes from a context, in which trace is prohibited to one where it | |
977 | isn't, or vice versa. In these mentioned conditions, the view of whether trace | |
978 | is prohibited is inconsistent between parts of the CPU, and the trace buffer or | |
979 | the trace buffer state might be corrupted. | |
980 | ||
981 | Work around this in the driver by preventing an inconsistent view of whether the | |
982 | trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a | |
983 | change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or | |
984 | two ISB instructions if no ERET is to take place. | |
985 | ||
986 | If unsure, say Y. | |
987 | ||
708e8af4 AK |
988 | config ARM64_ERRATUM_1902691 |
989 | bool "Cortex-A510: 1902691: workaround TRBE trace corruption" | |
3a828845 | 990 | depends on CORESIGHT_TRBE |
708e8af4 AK |
991 | default y |
992 | help | |
993 | This option adds the workaround for ARM Cortex-A510 erratum 1902691. | |
994 | ||
995 | Affected Cortex-A510 core might cause trace data corruption, when being written | |
996 | into the memory. Effectively TRBE is broken and hence cannot be used to capture | |
997 | trace data. | |
998 | ||
999 | Work around this problem in the driver by just preventing TRBE initialization on | |
1000 | affected cpus. The firmware must have disabled the access to TRBE for the kernel | |
1001 | on such implementations. This will cover the kernel for any firmware that doesn't | |
1002 | do this already. | |
1003 | ||
1004 | If unsure, say Y. | |
1005 | ||
e89d120c IV |
1006 | config ARM64_ERRATUM_2457168 |
1007 | bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" | |
1008 | depends on ARM64_AMU_EXTN | |
1009 | default y | |
1010 | help | |
1011 | This option adds the workaround for ARM Cortex-A510 erratum 2457168. | |
1012 | ||
1013 | The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate | |
1014 | as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments | |
1015 | incorrectly giving a significantly higher output value. | |
1016 | ||
1017 | Work around this problem by returning 0 when reading the affected counter in | |
1018 | key locations that results in disabling all users of this counter. This effect | |
1019 | is the same to firmware disabling affected counters. | |
1020 | ||
1021 | If unsure, say Y. | |
1022 | ||
5db568e7 AK |
1023 | config ARM64_ERRATUM_2645198 |
1024 | bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" | |
1025 | default y | |
1026 | help | |
1027 | This option adds the workaround for ARM Cortex-A715 erratum 2645198. | |
1028 | ||
1029 | If a Cortex-A715 cpu sees a page mapping permissions change from executable | |
1030 | to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the | |
1031 | next instruction abort caused by permission fault. | |
1032 | ||
1033 | Only user-space does executable to non-executable permission transition via | |
1034 | mprotect() system call. Workaround the problem by doing a break-before-make | |
1035 | TLB invalidation, for all changes to executable user space mappings. | |
1036 | ||
1037 | If unsure, say Y. | |
1038 | ||
546b7cde RH |
1039 | config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD |
1040 | bool | |
1041 | ||
471470bc RH |
1042 | config ARM64_ERRATUM_2966298 |
1043 | bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" | |
546b7cde | 1044 | select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD |
471470bc RH |
1045 | default y |
1046 | help | |
1047 | This option adds the workaround for ARM Cortex-A520 erratum 2966298. | |
1048 | ||
1049 | On an affected Cortex-A520 core, a speculatively executed unprivileged | |
1050 | load might leak data from a privileged level via a cache side channel. | |
1051 | ||
1052 | Work around this problem by executing a TLBI before returning to EL0. | |
1053 | ||
1054 | If unsure, say Y. | |
1055 | ||
f827bcda RH |
1056 | config ARM64_ERRATUM_3117295 |
1057 | bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" | |
1058 | select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD | |
1059 | default y | |
1060 | help | |
1061 | This option adds the workaround for ARM Cortex-A510 erratum 3117295. | |
1062 | ||
1063 | On an affected Cortex-A510 core, a speculatively executed unprivileged | |
1064 | load might leak data from a privileged level via a cache side channel. | |
1065 | ||
1066 | Work around this problem by executing a TLBI before returning to EL0. | |
1067 | ||
1068 | If unsure, say Y. | |
1069 | ||
7187bb7d MR |
1070 | config ARM64_WORKAROUND_SPECULATIVE_SSBS |
1071 | bool | |
1072 | ||
1073 | config ARM64_ERRATUM_3194386 | |
1074 | bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" | |
1075 | select ARM64_WORKAROUND_SPECULATIVE_SSBS | |
1076 | default y | |
1077 | help | |
1078 | This option adds the workaround for ARM Cortex-X4 erratum 3194386. | |
1079 | ||
1080 | On affected cores "MSR SSBS, #0" instructions may not affect | |
1081 | subsequent speculative instructions, which may permit unexepected | |
1082 | speculative store bypassing. | |
1083 | ||
1084 | Work around this problem by placing a speculation barrier after | |
1085 | kernel changes to SSBS. The presence of the SSBS special-purpose | |
1086 | register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such | |
1087 | that userspace will use the PR_SPEC_STORE_BYPASS prctl to change | |
1088 | SSBS. | |
1089 | ||
1090 | If unsure, say Y. | |
1091 | ||
1092 | config ARM64_ERRATUM_3312417 | |
1093 | bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" | |
1094 | select ARM64_WORKAROUND_SPECULATIVE_SSBS | |
1095 | default y | |
1096 | help | |
1097 | This option adds the workaround for ARM Neoverse-V3 erratum 3312417. | |
1098 | ||
1099 | On affected cores "MSR SSBS, #0" instructions may not affect | |
1100 | subsequent speculative instructions, which may permit unexepected | |
1101 | speculative store bypassing. | |
1102 | ||
1103 | Work around this problem by placing a speculation barrier after | |
1104 | kernel changes to SSBS. The presence of the SSBS special-purpose | |
1105 | register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such | |
1106 | that userspace will use the PR_SPEC_STORE_BYPASS prctl to change | |
1107 | SSBS. | |
1108 | ||
1109 | If unsure, say Y. | |
1110 | ||
1111 | ||
94100970 RR |
1112 | config CAVIUM_ERRATUM_22375 |
1113 | bool "Cavium erratum 22375, 24313" | |
1114 | default y | |
1115 | help | |
bc15cf70 | 1116 | Enable workaround for errata 22375 and 24313. |
94100970 RR |
1117 | |
1118 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
bc15cf70 | 1119 | with a small impact affecting only ITS table allocation. |
94100970 RR |
1120 | |
1121 | erratum 22375: only alloc 8MB table size | |
1122 | erratum 24313: ignore memory access type | |
1123 | ||
1124 | The fixes are in ITS initialization and basically ignore memory access | |
1125 | type and table size provided by the TYPER and BASER registers. | |
1126 | ||
1127 | If unsure, say Y. | |
1128 | ||
fbf8f40e GK |
1129 | config CAVIUM_ERRATUM_23144 |
1130 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
1131 | depends on NUMA | |
1132 | default y | |
1133 | help | |
1134 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
1135 | ||
1136 | If unsure, say Y. | |
1137 | ||
6d4e11c5 | 1138 | config CAVIUM_ERRATUM_23154 |
24a147bc | 1139 | bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" |
6d4e11c5 RR |
1140 | default y |
1141 | help | |
24a147bc | 1142 | The ThunderX GICv3 implementation requires a modified version for |
6d4e11c5 RR |
1143 | reading the IAR status to ensure data synchronization |
1144 | (access to icc_iar1_el1 is not sync'ed before and after). | |
1145 | ||
24a147bc LC |
1146 | It also suffers from erratum 38545 (also present on Marvell's |
1147 | OcteonTX and OcteonTX2), resulting in deactivated interrupts being | |
1148 | spuriously presented to the CPU interface. | |
1149 | ||
6d4e11c5 RR |
1150 | If unsure, say Y. |
1151 | ||
104a0c02 AP |
1152 | config CAVIUM_ERRATUM_27456 |
1153 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
1154 | default y | |
1155 | help | |
1156 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
1157 | instructions may cause the icache to become corrupted if it | |
1158 | contains data for a non-current ASID. The fix is to | |
1159 | invalidate the icache when changing the mm context. | |
1160 | ||
1161 | If unsure, say Y. | |
1162 | ||
690a3415 DD |
1163 | config CAVIUM_ERRATUM_30115 |
1164 | bool "Cavium erratum 30115: Guest may disable interrupts in host" | |
1165 | default y | |
1166 | help | |
1167 | On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through | |
1168 | 1.2, and T83 Pass 1.0, KVM guest execution may disable | |
1169 | interrupts in host. Trapping both GICv3 group-0 and group-1 | |
1170 | accesses sidesteps the issue. | |
1171 | ||
1172 | If unsure, say Y. | |
1173 | ||
603afdc9 MZ |
1174 | config CAVIUM_TX2_ERRATUM_219 |
1175 | bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" | |
1176 | default y | |
1177 | help | |
1178 | On Cavium ThunderX2, a load, store or prefetch instruction between a | |
1179 | TTBR update and the corresponding context synchronizing operation can | |
1180 | cause a spurious Data Abort to be delivered to any hardware thread in | |
1181 | the CPU core. | |
1182 | ||
1183 | Work around the issue by avoiding the problematic code sequence and | |
1184 | trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The | |
1185 | trap handler performs the corresponding register access, skips the | |
1186 | instruction and ensures context synchronization by virtue of the | |
1187 | exception return. | |
1188 | ||
1189 | If unsure, say Y. | |
1190 | ||
ebcea694 GU |
1191 | config FUJITSU_ERRATUM_010001 |
1192 | bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" | |
1193 | default y | |
1194 | help | |
1195 | This option adds a workaround for Fujitsu-A64FX erratum E#010001. | |
1196 | On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory | |
1197 | accesses may cause undefined fault (Data abort, DFSC=0b111111). | |
1198 | This fault occurs under a specific hardware condition when a | |
1199 | load/store instruction performs an address translation using: | |
1200 | case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. | |
1201 | case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. | |
1202 | case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. | |
1203 | case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. | |
1204 | ||
1205 | The workaround is to ensure these bits are clear in TCR_ELx. | |
1206 | The workaround only affects the Fujitsu-A64FX. | |
1207 | ||
1208 | If unsure, say Y. | |
1209 | ||
1210 | config HISILICON_ERRATUM_161600802 | |
1211 | bool "Hip07 161600802: Erroneous redistributor VLPI base" | |
1212 | default y | |
1213 | help | |
1214 | The HiSilicon Hip07 SoC uses the wrong redistributor base | |
1215 | when issued ITS commands such as VMOVP and VMAPP, and requires | |
1216 | a 128kB offset to be applied to the target address in this commands. | |
1217 | ||
1218 | If unsure, say Y. | |
1219 | ||
38fd94b0 CC |
1220 | config QCOM_FALKOR_ERRATUM_1003 |
1221 | bool "Falkor E1003: Incorrect translation due to ASID change" | |
1222 | default y | |
38fd94b0 CC |
1223 | help |
1224 | On Falkor v1, an incorrect ASID may be cached in the TLB when ASID | |
d1777e68 WD |
1225 | and BADDR are changed together in TTBRx_EL1. Since we keep the ASID |
1226 | in TTBR1_EL1, this situation only occurs in the entry trampoline and | |
1227 | then only for entries in the walk cache, since the leaf translation | |
1228 | is unchanged. Work around the erratum by invalidating the walk cache | |
1229 | entries for the trampoline before entering the kernel proper. | |
38fd94b0 | 1230 | |
d9ff80f8 CC |
1231 | config QCOM_FALKOR_ERRATUM_1009 |
1232 | bool "Falkor E1009: Prematurely complete a DSB after a TLBI" | |
1233 | default y | |
ce8c80c5 | 1234 | select ARM64_WORKAROUND_REPEAT_TLBI |
d9ff80f8 CC |
1235 | help |
1236 | On Falkor v1, the CPU may prematurely complete a DSB following a | |
1237 | TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation | |
1238 | one more time to fix the issue. | |
1239 | ||
1240 | If unsure, say Y. | |
1241 | ||
90922a2d SD |
1242 | config QCOM_QDF2400_ERRATUM_0065 |
1243 | bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" | |
1244 | default y | |
1245 | help | |
1246 | On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports | |
1247 | ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have | |
1248 | been indicated as 16Bytes (0xf), not 8Bytes (0x7). | |
1249 | ||
1250 | If unsure, say Y. | |
1251 | ||
932b50c7 SD |
1252 | config QCOM_FALKOR_ERRATUM_E1041 |
1253 | bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" | |
1254 | default y | |
1255 | help | |
1256 | Falkor CPU may speculatively fetch instructions from an improper | |
1257 | memory location when MMU translation is changed from SCTLR_ELn[M]=1 | |
1258 | to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. | |
1259 | ||
1260 | If unsure, say Y. | |
1261 | ||
20109a85 RW |
1262 | config NVIDIA_CARMEL_CNP_ERRATUM |
1263 | bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" | |
1264 | default y | |
1265 | help | |
1266 | If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not | |
1267 | invalidate shared TLB entries installed by a different core, as it would | |
1268 | on standard ARM cores. | |
1269 | ||
1270 | If unsure, say Y. | |
1271 | ||
a8707f55 SR |
1272 | config ROCKCHIP_ERRATUM_3588001 |
1273 | bool "Rockchip 3588001: GIC600 can not support shareability attributes" | |
1274 | default y | |
1275 | help | |
1276 | The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. | |
1277 | This means, that its sharability feature may not be used, even though it | |
1278 | is supported by the IP itself. | |
1279 | ||
1280 | If unsure, say Y. | |
1281 | ||
ebcea694 GU |
1282 | config SOCIONEXT_SYNQUACER_PREITS |
1283 | bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" | |
3e32131a ZL |
1284 | default y |
1285 | help | |
ebcea694 GU |
1286 | Socionext Synquacer SoCs implement a separate h/w block to generate |
1287 | MSI doorbell writes with non-zero values for the device ID. | |
3e32131a ZL |
1288 | |
1289 | If unsure, say Y. | |
1290 | ||
3cb7e662 | 1291 | endmenu # "ARM errata workarounds via the alternatives framework" |
c0a01b84 | 1292 | |
e41ceed0 JL |
1293 | choice |
1294 | prompt "Page size" | |
1295 | default ARM64_4K_PAGES | |
1296 | help | |
1297 | Page size (translation granule) configuration. | |
1298 | ||
1299 | config ARM64_4K_PAGES | |
1300 | bool "4KB" | |
d3e5bab9 | 1301 | select HAVE_PAGE_SIZE_4KB |
e41ceed0 JL |
1302 | help |
1303 | This feature enables 4KB pages support. | |
1304 | ||
44eaacf1 SP |
1305 | config ARM64_16K_PAGES |
1306 | bool "16KB" | |
d3e5bab9 | 1307 | select HAVE_PAGE_SIZE_16KB |
44eaacf1 SP |
1308 | help |
1309 | The system will use 16KB pages support. AArch32 emulation | |
1310 | requires applications compiled with 16K (or a multiple of 16K) | |
1311 | aligned segments. | |
1312 | ||
8c2c3df3 | 1313 | config ARM64_64K_PAGES |
e41ceed0 | 1314 | bool "64KB" |
d3e5bab9 | 1315 | select HAVE_PAGE_SIZE_64KB |
8c2c3df3 CM |
1316 | help |
1317 | This feature enables 64KB pages support (4KB by default) | |
1318 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
1319 | look-up. AArch32 emulation requires applications compiled |
1320 | with 64K aligned segments. | |
8c2c3df3 | 1321 | |
e41ceed0 JL |
1322 | endchoice |
1323 | ||
1324 | choice | |
1325 | prompt "Virtual address space size" | |
5d101654 | 1326 | default ARM64_VA_BITS_52 |
e41ceed0 JL |
1327 | help |
1328 | Allows choosing one of multiple possible virtual address | |
1329 | space sizes. The level of translation table is determined by | |
1330 | a combination of page size and virtual address space size. | |
1331 | ||
21539939 | 1332 | config ARM64_VA_BITS_36 |
56a3f30e | 1333 | bool "36-bit" if EXPERT |
d3e5bab9 | 1334 | depends on PAGE_SIZE_16KB |
21539939 | 1335 | |
e41ceed0 JL |
1336 | config ARM64_VA_BITS_39 |
1337 | bool "39-bit" | |
d3e5bab9 | 1338 | depends on PAGE_SIZE_4KB |
e41ceed0 JL |
1339 | |
1340 | config ARM64_VA_BITS_42 | |
1341 | bool "42-bit" | |
d3e5bab9 | 1342 | depends on PAGE_SIZE_64KB |
e41ceed0 | 1343 | |
44eaacf1 SP |
1344 | config ARM64_VA_BITS_47 |
1345 | bool "47-bit" | |
d3e5bab9 | 1346 | depends on PAGE_SIZE_16KB |
44eaacf1 | 1347 | |
c79b954b JL |
1348 | config ARM64_VA_BITS_48 |
1349 | bool "48-bit" | |
c79b954b | 1350 | |
b6d00d47 SC |
1351 | config ARM64_VA_BITS_52 |
1352 | bool "52-bit" | |
352b0395 | 1353 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN |
68d23da4 WD |
1354 | help |
1355 | Enable 52-bit virtual addressing for userspace when explicitly | |
b6d00d47 SC |
1356 | requested via a hint to mmap(). The kernel will also use 52-bit |
1357 | virtual addresses for its own mappings (provided HW support for | |
1358 | this feature is available, otherwise it reverts to 48-bit). | |
68d23da4 WD |
1359 | |
1360 | NOTE: Enabling 52-bit virtual addressing in conjunction with | |
1361 | ARMv8.3 Pointer Authentication will result in the PAC being | |
1362 | reduced from 7 bits to 3 bits, which may have a significant | |
1363 | impact on its susceptibility to brute-force attacks. | |
1364 | ||
1365 | If unsure, select 48-bit virtual addressing instead. | |
1366 | ||
e41ceed0 JL |
1367 | endchoice |
1368 | ||
68d23da4 WD |
1369 | config ARM64_FORCE_52BIT |
1370 | bool "Force 52-bit virtual addresses for userspace" | |
b6d00d47 | 1371 | depends on ARM64_VA_BITS_52 && EXPERT |
68d23da4 WD |
1372 | help |
1373 | For systems with 52-bit userspace VAs enabled, the kernel will attempt | |
1374 | to maintain compatibility with older software by providing 48-bit VAs | |
1375 | unless a hint is supplied to mmap. | |
1376 | ||
1377 | This configuration option disables the 48-bit compatibility logic, and | |
1378 | forces all userspace addresses to be 52-bit on HW that supports it. One | |
1379 | should only enable this configuration option for stress testing userspace | |
1380 | memory management code. If unsure say N here. | |
1381 | ||
e41ceed0 JL |
1382 | config ARM64_VA_BITS |
1383 | int | |
21539939 | 1384 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
1385 | default 39 if ARM64_VA_BITS_39 |
1386 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 1387 | default 47 if ARM64_VA_BITS_47 |
b6d00d47 SC |
1388 | default 48 if ARM64_VA_BITS_48 |
1389 | default 52 if ARM64_VA_BITS_52 | |
e41ceed0 | 1390 | |
982aa7c5 KM |
1391 | choice |
1392 | prompt "Physical address space size" | |
1393 | default ARM64_PA_BITS_48 | |
1394 | help | |
1395 | Choose the maximum physical address range that the kernel will | |
1396 | support. | |
1397 | ||
1398 | config ARM64_PA_BITS_48 | |
1399 | bool "48-bit" | |
352b0395 | 1400 | depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 |
982aa7c5 | 1401 | |
f77d2817 | 1402 | config ARM64_PA_BITS_52 |
352b0395 AB |
1403 | bool "52-bit" |
1404 | depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 | |
f77d2817 KM |
1405 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN |
1406 | help | |
1407 | Enable support for a 52-bit physical address space, introduced as | |
1408 | part of the ARMv8.2-LPA extension. | |
1409 | ||
1410 | With this enabled, the kernel will also continue to work on CPUs that | |
1411 | do not support ARMv8.2-LPA, but with some added memory overhead (and | |
1412 | minor performance overhead). | |
1413 | ||
982aa7c5 KM |
1414 | endchoice |
1415 | ||
1416 | config ARM64_PA_BITS | |
1417 | int | |
1418 | default 48 if ARM64_PA_BITS_48 | |
f77d2817 | 1419 | default 52 if ARM64_PA_BITS_52 |
982aa7c5 | 1420 | |
db95ea78 AB |
1421 | config ARM64_LPA2 |
1422 | def_bool y | |
1423 | depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES | |
1424 | ||
d8e85e14 AR |
1425 | choice |
1426 | prompt "Endianness" | |
1427 | default CPU_LITTLE_ENDIAN | |
1428 | help | |
1429 | Select the endianness of data accesses performed by the CPU. Userspace | |
1430 | applications will need to be compiled and linked for the endianness | |
1431 | that is selected here. | |
1432 | ||
a872013d | 1433 | config CPU_BIG_ENDIAN |
e9c6deee | 1434 | bool "Build big-endian kernel" |
146a15b8 NC |
1435 | # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c |
1436 | depends on AS_IS_GNU || AS_VERSION >= 150000 | |
e9c6deee | 1437 | help |
d8e85e14 AR |
1438 | Say Y if you plan on running a kernel with a big-endian userspace. |
1439 | ||
1440 | config CPU_LITTLE_ENDIAN | |
1441 | bool "Build little-endian kernel" | |
1442 | help | |
1443 | Say Y if you plan on running a kernel with a little-endian userspace. | |
1444 | This is usually the case for distributions targeting arm64. | |
1445 | ||
1446 | endchoice | |
a872013d | 1447 | |
f6e763b9 MB |
1448 | config SCHED_MC |
1449 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
1450 | help |
1451 | Multi-core scheduler support improves the CPU scheduler's decision | |
1452 | making when dealing with multi-core CPU chips at a cost of slightly | |
1453 | increased overhead in some places. If unsure say N here. | |
1454 | ||
778c558f BS |
1455 | config SCHED_CLUSTER |
1456 | bool "Cluster scheduler support" | |
1457 | help | |
1458 | Cluster scheduler support improves the CPU scheduler's decision | |
1459 | making when dealing with machines that have clusters of CPUs. | |
1460 | Cluster usually means a couple of CPUs which are placed closely | |
1461 | by sharing mid-level caches, last-level cache tags or internal | |
1462 | busses. | |
1463 | ||
f6e763b9 MB |
1464 | config SCHED_SMT |
1465 | bool "SMT scheduler support" | |
f6e763b9 MB |
1466 | help |
1467 | Improves the CPU scheduler's decision making when dealing with | |
1468 | MultiThreading at a cost of slightly increased overhead in some | |
1469 | places. If unsure say N here. | |
1470 | ||
8c2c3df3 | 1471 | config NR_CPUS |
62aa9655 GK |
1472 | int "Maximum number of CPUs (2-4096)" |
1473 | range 2 4096 | |
3fbd56f0 | 1474 | default "512" |
8c2c3df3 | 1475 | |
9327e2c6 MR |
1476 | config HOTPLUG_CPU |
1477 | bool "Support for hot-pluggable CPUs" | |
217d453d | 1478 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
1479 | help |
1480 | Say Y here to experiment with turning CPUs off and on. CPUs | |
1481 | can be controlled through /sys/devices/system/cpu. | |
1482 | ||
1a2db300 GK |
1483 | # Common NUMA Features |
1484 | config NUMA | |
4399e6cd | 1485 | bool "NUMA Memory Allocation and Scheduler Support" |
ae3c107c | 1486 | select GENERIC_ARCH_NUMA |
0c2a6cce KW |
1487 | select ACPI_NUMA if ACPI |
1488 | select OF_NUMA | |
7ecd19cf KW |
1489 | select HAVE_SETUP_PER_CPU_AREA |
1490 | select NEED_PER_CPU_EMBED_FIRST_CHUNK | |
1491 | select NEED_PER_CPU_PAGE_FIRST_CHUNK | |
1492 | select USE_PERCPU_NUMA_NODE_ID | |
1a2db300 | 1493 | help |
4399e6cd | 1494 | Enable NUMA (Non-Uniform Memory Access) support. |
1a2db300 GK |
1495 | |
1496 | The kernel will try to allocate memory used by a CPU on the | |
1497 | local memory of the CPU and add some more | |
1498 | NUMA awareness to the kernel. | |
1499 | ||
1500 | config NODES_SHIFT | |
1501 | int "Maximum NUMA Nodes (as a power of 2)" | |
1502 | range 1 10 | |
2a13c13b | 1503 | default "4" |
a9ee6cf5 | 1504 | depends on NUMA |
1a2db300 GK |
1505 | help |
1506 | Specify the maximum number of NUMA Nodes available on the target | |
1507 | system. Increases memory reserved to accommodate various tables. | |
1508 | ||
8636a1f9 | 1509 | source "kernel/Kconfig.hz" |
8c2c3df3 | 1510 | |
8c2c3df3 CM |
1511 | config ARCH_SPARSEMEM_ENABLE |
1512 | def_bool y | |
1513 | select SPARSEMEM_VMEMMAP_ENABLE | |
782276b4 | 1514 | select SPARSEMEM_VMEMMAP |
e7d4bac4 | 1515 | |
8c2c3df3 | 1516 | config HW_PERF_EVENTS |
6475b2d8 MR |
1517 | def_bool y |
1518 | depends on ARM_PMU | |
8c2c3df3 | 1519 | |
afcf5441 | 1520 | # Supported by clang >= 7.0 or GCC >= 12.0.0 |
5287569a ST |
1521 | config CC_HAVE_SHADOW_CALL_STACK |
1522 | def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) | |
1523 | ||
dfd57bc3 SS |
1524 | config PARAVIRT |
1525 | bool "Enable paravirtualization code" | |
1526 | help | |
1527 | This changes the kernel so it can modify itself when it is run | |
1528 | under a hypervisor, potentially improving performance significantly | |
1529 | over full virtualization. | |
1530 | ||
1531 | config PARAVIRT_TIME_ACCOUNTING | |
1532 | bool "Paravirtual steal time accounting" | |
1533 | select PARAVIRT | |
dfd57bc3 SS |
1534 | help |
1535 | Select this option to enable fine granularity task steal time | |
1536 | accounting. Time spent executing other tasks in parallel with | |
1537 | the current vCPU is discounted from the vCPU power. To account for | |
1538 | that, there can be a small performance impact. | |
1539 | ||
1540 | If in doubt, say N here. | |
1541 | ||
91506f7e ED |
1542 | config ARCH_SUPPORTS_KEXEC |
1543 | def_bool PM_SLEEP_SMP | |
3ddd9992 | 1544 | |
91506f7e ED |
1545 | config ARCH_SUPPORTS_KEXEC_FILE |
1546 | def_bool y | |
732b7b93 | 1547 | |
91506f7e ED |
1548 | config ARCH_SELECTS_KEXEC_FILE |
1549 | def_bool y | |
1550 | depends on KEXEC_FILE | |
1551 | select HAVE_IMA_KEXEC if IMA | |
732b7b93 | 1552 | |
91506f7e ED |
1553 | config ARCH_SUPPORTS_KEXEC_SIG |
1554 | def_bool y | |
732b7b93 | 1555 | |
91506f7e ED |
1556 | config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG |
1557 | def_bool y | |
732b7b93 | 1558 | |
91506f7e ED |
1559 | config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG |
1560 | def_bool y | |
e62aaeac | 1561 | |
91506f7e ED |
1562 | config ARCH_SUPPORTS_CRASH_DUMP |
1563 | def_bool y | |
e62aaeac | 1564 | |
fdc26823 | 1565 | config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION |
85fcde40 | 1566 | def_bool CRASH_RESERVE |
fdc26823 | 1567 | |
072e3d96 PT |
1568 | config TRANS_TABLE |
1569 | def_bool y | |
08eae0ef | 1570 | depends on HIBERNATION || KEXEC_CORE |
072e3d96 | 1571 | |
aa42aa13 SS |
1572 | config XEN_DOM0 |
1573 | def_bool y | |
1574 | depends on XEN | |
1575 | ||
1576 | config XEN | |
c2ba1f7d | 1577 | bool "Xen guest support on ARM64" |
aa42aa13 | 1578 | depends on ARM64 && OF |
83862ccf | 1579 | select SWIOTLB_XEN |
dfd57bc3 | 1580 | select PARAVIRT |
aa42aa13 SS |
1581 | help |
1582 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
1583 | ||
5a4c2a31 KW |
1584 | # include/linux/mmzone.h requires the following to be true: |
1585 | # | |
5e0a760b | 1586 | # MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS |
5a4c2a31 | 1587 | # |
5e0a760b | 1588 | # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: |
5a4c2a31 | 1589 | # |
5e0a760b KS |
1590 | # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | |
1591 | # ----+-------------------+--------------+----------------------+-------------------------+ | |
1592 | # 4K | 27 | 12 | 15 | 10 | | |
1593 | # 16K | 27 | 14 | 13 | 11 | | |
1594 | # 64K | 29 | 16 | 13 | 13 | | |
0192445c | 1595 | config ARCH_FORCE_MAX_ORDER |
f3c37621 | 1596 | int |
23baf831 | 1597 | default "13" if ARM64_64K_PAGES |
23baf831 | 1598 | default "11" if ARM64_16K_PAGES |
23baf831 | 1599 | default "10" |
44eaacf1 | 1600 | help |
4632cb22 | 1601 | The kernel page allocator limits the size of maximal physically |
5e0a760b | 1602 | contiguous allocations. The limit is called MAX_PAGE_ORDER and it |
4632cb22 MRI |
1603 | defines the maximal power of two of number of pages that can be |
1604 | allocated as a single contiguous block. This option allows | |
1605 | overriding the default setting when ability to allocate very | |
1606 | large blocks of physically contiguous memory is required. | |
44eaacf1 | 1607 | |
4632cb22 | 1608 | The maximal size of allocation cannot exceed the size of the |
5e0a760b | 1609 | section, so the value of MAX_PAGE_ORDER should satisfy |
44eaacf1 | 1610 | |
5e0a760b | 1611 | MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS |
4632cb22 MRI |
1612 | |
1613 | Don't change if unsure. | |
d03bb145 | 1614 | |
084eb77c | 1615 | config UNMAP_KERNEL_AT_EL0 |
7540f70d | 1616 | bool "Unmap kernel when running in userspace (KPTI)" if EXPERT |
084eb77c WD |
1617 | default y |
1618 | help | |
0617052d WD |
1619 | Speculation attacks against some high-performance processors can |
1620 | be used to bypass MMU permission checks and leak kernel data to | |
1621 | userspace. This can be defended against by unmapping the kernel | |
1622 | when running in userspace, mapping it back in on exception entry | |
1623 | via a trampoline page in the vector table. | |
084eb77c WD |
1624 | |
1625 | If unsure, say Y. | |
1626 | ||
558c303c JM |
1627 | config MITIGATE_SPECTRE_BRANCH_HISTORY |
1628 | bool "Mitigate Spectre style attacks against branch history" if EXPERT | |
1629 | default y | |
1630 | help | |
1631 | Speculation attacks against some high-performance processors can | |
1632 | make use of branch history to influence future speculation. | |
1633 | When taking an exception from user-space, a sequence of branches | |
1634 | or a firmware call overwrites the branch history. | |
1635 | ||
c55191e9 AB |
1636 | config RODATA_FULL_DEFAULT_ENABLED |
1637 | bool "Apply r/o permissions of VM areas also to their linear aliases" | |
1638 | default y | |
1639 | help | |
1640 | Apply read-only attributes of VM areas to the linear alias of | |
1641 | the backing pages as well. This prevents code or read-only data | |
1642 | from being modified (inadvertently or intentionally) via another | |
1643 | mapping of the same memory page. This additional enhancement can | |
1644 | be turned off at runtime by passing rodata=[off|on] (and turned on | |
1645 | with rodata=full if this option is set to 'n') | |
1646 | ||
1647 | This requires the linear region to be mapped down to pages, | |
1648 | which may adversely affect performance in some cases. | |
1649 | ||
dd523791 WD |
1650 | config ARM64_SW_TTBR0_PAN |
1651 | bool "Emulate Privileged Access Never using TTBR0_EL1 switching" | |
1652 | help | |
1653 | Enabling this option prevents the kernel from accessing | |
1654 | user-space memory directly by pointing TTBR0_EL1 to a reserved | |
1655 | zeroed area and reserved ASID. The user access routines | |
1656 | restore the valid TTBR0_EL1 temporarily. | |
1657 | ||
63f0c603 CM |
1658 | config ARM64_TAGGED_ADDR_ABI |
1659 | bool "Enable the tagged user addresses syscall ABI" | |
1660 | default y | |
1661 | help | |
1662 | When this option is enabled, user applications can opt in to a | |
1663 | relaxed ABI via prctl() allowing tagged addresses to be passed | |
1664 | to system calls as pointer arguments. For details, see | |
6e4596c4 | 1665 | Documentation/arch/arm64/tagged-address-abi.rst. |
63f0c603 | 1666 | |
dd523791 WD |
1667 | menuconfig COMPAT |
1668 | bool "Kernel support for 32-bit EL0" | |
1669 | depends on ARM64_4K_PAGES || EXPERT | |
dd523791 WD |
1670 | select HAVE_UID16 |
1671 | select OLD_SIGSUSPEND3 | |
1672 | select COMPAT_OLD_SIGACTION | |
1673 | help | |
1674 | This option enables support for a 32-bit EL0 running under a 64-bit | |
1675 | kernel at EL1. AArch32-specific components such as system calls, | |
1676 | the user helper functions, VFP support and the ptrace interface are | |
1677 | handled appropriately by the kernel. | |
1678 | ||
1679 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware | |
1680 | that you will only be able to execute AArch32 binaries that were compiled | |
1681 | with page size aligned segments. | |
1682 | ||
1683 | If you want to execute 32-bit userspace applications, say Y. | |
1684 | ||
1685 | if COMPAT | |
1686 | ||
1687 | config KUSER_HELPERS | |
7c4791c9 | 1688 | bool "Enable kuser helpers page for 32-bit applications" |
dd523791 WD |
1689 | default y |
1690 | help | |
1691 | Warning: disabling this option may break 32-bit user programs. | |
1692 | ||
1693 | Provide kuser helpers to compat tasks. The kernel provides | |
1694 | helper code to userspace in read only form at a fixed location | |
1695 | to allow userspace to be independent of the CPU type fitted to | |
1696 | the system. This permits binaries to be run on ARMv4 through | |
1697 | to ARMv8 without modification. | |
1698 | ||
263638dc | 1699 | See Documentation/arch/arm/kernel_user_helpers.rst for details. |
dd523791 WD |
1700 | |
1701 | However, the fixed address nature of these helpers can be used | |
1702 | by ROP (return orientated programming) authors when creating | |
1703 | exploits. | |
1704 | ||
1705 | If all of the binaries and libraries which run on your platform | |
1706 | are built specifically for your platform, and make no use of | |
1707 | these helpers, then you can turn this option off to hinder | |
1708 | such exploits. However, in that case, if a binary or library | |
1709 | relying on those helpers is run, it will not function correctly. | |
1710 | ||
1711 | Say N here only if you are absolutely certain that you do not | |
1712 | need these helpers; otherwise, the safe option is to say Y. | |
1713 | ||
7c4791c9 WD |
1714 | config COMPAT_VDSO |
1715 | bool "Enable vDSO for 32-bit applications" | |
3e6f8d1f ND |
1716 | depends on !CPU_BIG_ENDIAN |
1717 | depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" | |
7c4791c9 WD |
1718 | select GENERIC_COMPAT_VDSO |
1719 | default y | |
1720 | help | |
1721 | Place in the process address space of 32-bit applications an | |
1722 | ELF shared object providing fast implementations of gettimeofday | |
1723 | and clock_gettime. | |
1724 | ||
1725 | You must have a 32-bit build of glibc 2.22 or later for programs | |
1726 | to seamlessly take advantage of this. | |
dd523791 | 1727 | |
625412c2 ND |
1728 | config THUMB2_COMPAT_VDSO |
1729 | bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT | |
1730 | depends on COMPAT_VDSO | |
1731 | default y | |
1732 | help | |
1733 | Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, | |
1734 | otherwise with '-marm'. | |
1735 | ||
3fc24ef3 AB |
1736 | config COMPAT_ALIGNMENT_FIXUPS |
1737 | bool "Fix up misaligned multi-word loads and stores in user space" | |
1738 | ||
1b907f46 WD |
1739 | menuconfig ARMV8_DEPRECATED |
1740 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
6cfa7cc4 | 1741 | depends on SYSCTL |
1b907f46 WD |
1742 | help |
1743 | Legacy software support may require certain instructions | |
1744 | that have been deprecated or obsoleted in the architecture. | |
1745 | ||
1746 | Enable this config to enable selective emulation of these | |
1747 | features. | |
1748 | ||
1749 | If unsure, say Y | |
1750 | ||
1751 | if ARMV8_DEPRECATED | |
1752 | ||
1753 | config SWP_EMULATION | |
1754 | bool "Emulate SWP/SWPB instructions" | |
1755 | help | |
1756 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
1757 | they are always undefined. Say Y here to enable software | |
1758 | emulation of these instructions for userspace using LDXR/STXR. | |
dd720784 MB |
1759 | This feature can be controlled at runtime with the abi.swp |
1760 | sysctl which is disabled by default. | |
1b907f46 WD |
1761 | |
1762 | In some older versions of glibc [<=2.8] SWP is used during futex | |
1763 | trylock() operations with the assumption that the code will not | |
1764 | be preempted. This invalid assumption may be more likely to fail | |
1765 | with SWP emulation enabled, leading to deadlock of the user | |
1766 | application. | |
1767 | ||
1768 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
1769 | on an external transaction monitoring block called a global | |
1770 | monitor to maintain update atomicity. If your system does not | |
1771 | implement a global monitor, this option can cause programs that | |
1772 | perform SWP operations to uncached memory to deadlock. | |
1773 | ||
1774 | If unsure, say Y | |
1775 | ||
1776 | config CP15_BARRIER_EMULATION | |
1777 | bool "Emulate CP15 Barrier instructions" | |
1778 | help | |
1779 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
1780 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
1781 | strongly recommended to use the ISB, DSB, and DMB | |
1782 | instructions instead. | |
1783 | ||
1784 | Say Y here to enable software emulation of these | |
1785 | instructions for AArch32 userspace code. When this option is | |
1786 | enabled, CP15 barrier usage is traced which can help | |
dd720784 MB |
1787 | identify software that needs updating. This feature can be |
1788 | controlled at runtime with the abi.cp15_barrier sysctl. | |
1b907f46 WD |
1789 | |
1790 | If unsure, say Y | |
1791 | ||
2d888f48 SP |
1792 | config SETEND_EMULATION |
1793 | bool "Emulate SETEND instruction" | |
1794 | help | |
1795 | The SETEND instruction alters the data-endianness of the | |
1796 | AArch32 EL0, and is deprecated in ARMv8. | |
1797 | ||
1798 | Say Y here to enable software emulation of the instruction | |
dd720784 MB |
1799 | for AArch32 userspace code. This feature can be controlled |
1800 | at runtime with the abi.setend sysctl. | |
2d888f48 SP |
1801 | |
1802 | Note: All the cpus on the system must have mixed endian support at EL0 | |
1803 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
1804 | endian - is hotplugged in after this feature has been enabled, there could | |
1805 | be unexpected results in the applications. | |
1806 | ||
1807 | If unsure, say Y | |
3cb7e662 | 1808 | endif # ARMV8_DEPRECATED |
1b907f46 | 1809 | |
3cb7e662 | 1810 | endif # COMPAT |
ba42822a | 1811 | |
0e4a0709 WD |
1812 | menu "ARMv8.1 architectural features" |
1813 | ||
1814 | config ARM64_HW_AFDBM | |
1815 | bool "Support for hardware updates of the Access and Dirty page flags" | |
1816 | default y | |
1817 | help | |
1818 | The ARMv8.1 architecture extensions introduce support for | |
1819 | hardware updates of the access and dirty information in page | |
1820 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
1821 | capable processors, accesses to pages with PTE_AF cleared will | |
1822 | set this bit instead of raising an access flag fault. | |
1823 | Similarly, writes to read-only pages with the DBM bit set will | |
1824 | clear the read-only bit (AP[2]) instead of raising a | |
1825 | permission fault. | |
1826 | ||
1827 | Kernels built with this configuration option enabled continue | |
1828 | to work on pre-ARMv8.1 hardware and the performance impact is | |
1829 | minimal. If unsure, say Y. | |
1830 | ||
1831 | config ARM64_PAN | |
1832 | bool "Enable support for Privileged Access Never (PAN)" | |
1833 | default y | |
1834 | help | |
3cb7e662 JH |
1835 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) |
1836 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
1837 | memory directly. | |
0e4a0709 | 1838 | |
3cb7e662 JH |
1839 | Choosing this option will cause any unprotected (not using |
1840 | copy_to_user et al) memory access to fail with a permission fault. | |
0e4a0709 | 1841 | |
3cb7e662 JH |
1842 | The feature is detected at runtime, and will remain as a 'nop' |
1843 | instruction if the cpu does not implement the feature. | |
0e4a0709 | 1844 | |
2decad92 CM |
1845 | config AS_HAS_LSE_ATOMICS |
1846 | def_bool $(as-instr,.arch_extension lse) | |
1847 | ||
0e4a0709 | 1848 | config ARM64_LSE_ATOMICS |
395af861 CM |
1849 | bool |
1850 | default ARM64_USE_LSE_ATOMICS | |
2decad92 | 1851 | depends on AS_HAS_LSE_ATOMICS |
395af861 CM |
1852 | |
1853 | config ARM64_USE_LSE_ATOMICS | |
0e4a0709 | 1854 | bool "Atomic instructions" |
7bd99b40 | 1855 | default y |
0e4a0709 WD |
1856 | help |
1857 | As part of the Large System Extensions, ARMv8.1 introduces new | |
1858 | atomic instructions that are designed specifically to scale in | |
1859 | very large systems. | |
1860 | ||
1861 | Say Y here to make use of these instructions for the in-kernel | |
1862 | atomic routines. This incurs a small overhead on CPUs that do | |
1863 | not support these instructions and requires the kernel to be | |
7bd99b40 WD |
1864 | built with binutils >= 2.25 in order for the new instructions |
1865 | to be used. | |
0e4a0709 | 1866 | |
3cb7e662 | 1867 | endmenu # "ARMv8.1 architectural features" |
0e4a0709 | 1868 | |
f993318b WD |
1869 | menu "ARMv8.2 architectural features" |
1870 | ||
2c54b423 | 1871 | config AS_HAS_ARMV8_2 |
3cb7e662 | 1872 | def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) |
2c54b423 AB |
1873 | |
1874 | config AS_HAS_SHA3 | |
3cb7e662 | 1875 | def_bool $(as-instr,.arch armv8.2-a+sha3) |
2c54b423 | 1876 | |
d50e071f RM |
1877 | config ARM64_PMEM |
1878 | bool "Enable support for persistent memory" | |
1879 | select ARCH_HAS_PMEM_API | |
5d7bdeb1 | 1880 | select ARCH_HAS_UACCESS_FLUSHCACHE |
d50e071f RM |
1881 | help |
1882 | Say Y to enable support for the persistent memory API based on the | |
1883 | ARMv8.2 DCPoP feature. | |
1884 | ||
1885 | The feature is detected at runtime, and the kernel will use DC CVAC | |
1886 | operations if DC CVAP is not supported (following the behaviour of | |
1887 | DC CVAP itself if the system does not define a point of persistence). | |
1888 | ||
64c02720 XX |
1889 | config ARM64_RAS_EXTN |
1890 | bool "Enable support for RAS CPU Extensions" | |
1891 | default y | |
1892 | help | |
1893 | CPUs that support the Reliability, Availability and Serviceability | |
1894 | (RAS) Extensions, part of ARMv8.2 are able to track faults and | |
1895 | errors, classify them and report them to software. | |
1896 | ||
1897 | On CPUs with these extensions system software can use additional | |
1898 | barriers to determine if faults are pending and read the | |
1899 | classification from a new set of registers. | |
1900 | ||
1901 | Selecting this feature will allow the kernel to use these barriers | |
1902 | and access the new registers if the system supports the extension. | |
1903 | Platform RAS features may additionally depend on firmware support. | |
1904 | ||
5ffdfaed VM |
1905 | config ARM64_CNP |
1906 | bool "Enable support for Common Not Private (CNP) translations" | |
1907 | default y | |
1908 | depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN | |
1909 | help | |
1910 | Common Not Private (CNP) allows translation table entries to | |
1911 | be shared between different PEs in the same inner shareable | |
1912 | domain, so the hardware can use this fact to optimise the | |
1913 | caching of such entries in the TLB. | |
1914 | ||
1915 | Selecting this option allows the CNP feature to be detected | |
1916 | at runtime, and does not affect PEs that do not implement | |
1917 | this feature. | |
1918 | ||
3cb7e662 | 1919 | endmenu # "ARMv8.2 architectural features" |
f993318b | 1920 | |
04ca3204 MR |
1921 | menu "ARMv8.3 architectural features" |
1922 | ||
1923 | config ARM64_PTR_AUTH | |
1924 | bool "Enable support for pointer authentication" | |
1925 | default y | |
1926 | help | |
1927 | Pointer authentication (part of the ARMv8.3 Extensions) provides | |
1928 | instructions for signing and authenticating pointers against secret | |
1929 | keys, which can be used to mitigate Return Oriented Programming (ROP) | |
1930 | and other attacks. | |
1931 | ||
1932 | This option enables these instructions at EL0 (i.e. for userspace). | |
04ca3204 MR |
1933 | Choosing this option will cause the kernel to initialise secret keys |
1934 | for each process at exec() time, with these keys being | |
1935 | context-switched along with the process. | |
1936 | ||
1937 | The feature is detected at runtime. If the feature is not present in | |
384b40ca | 1938 | hardware it will not be advertised to userspace/KVM guest nor will it |
dfb0589c | 1939 | be enabled. |
04ca3204 | 1940 | |
6982934e KM |
1941 | If the feature is present on the boot CPU but not on a late CPU, then |
1942 | the late CPU will be parked. Also, if the boot CPU does not have | |
1943 | address auth and the late CPU has then the late CPU will still boot | |
1944 | but with the feature disabled. On such a system, this option should | |
1945 | not be selected. | |
1946 | ||
b27a9f41 | 1947 | config ARM64_PTR_AUTH_KERNEL |
d053e71a | 1948 | bool "Use pointer authentication for kernel" |
b27a9f41 DK |
1949 | default y |
1950 | depends on ARM64_PTR_AUTH | |
1e249c41 | 1951 | depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 |
b27a9f41 DK |
1952 | # Modern compilers insert a .note.gnu.property section note for PAC |
1953 | # which is only understood by binutils starting with version 2.33.1. | |
1954 | depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) | |
1955 | depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE | |
26299b3f | 1956 | depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) |
b27a9f41 DK |
1957 | help |
1958 | If the compiler supports the -mbranch-protection or | |
1959 | -msign-return-address flag (e.g. GCC 7 or later), then this option | |
1960 | will cause the kernel itself to be compiled with return address | |
1961 | protection. In this case, and if the target hardware is known to | |
1962 | support pointer authentication, then CONFIG_STACKPROTECTOR can be | |
1963 | disabled with minimal loss of protection. | |
1964 | ||
74afda40 | 1965 | This feature works with FUNCTION_GRAPH_TRACER option only if |
26299b3f | 1966 | DYNAMIC_FTRACE_WITH_ARGS is enabled. |
74afda40 KM |
1967 | |
1968 | config CC_HAS_BRANCH_PROT_PAC_RET | |
1969 | # GCC 9 or later, clang 8 or later | |
1970 | def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) | |
1971 | ||
1972 | config CC_HAS_SIGN_RETURN_ADDRESS | |
1973 | # GCC 7, 8 | |
1974 | def_bool $(cc-option,-msign-return-address=all) | |
1975 | ||
1e249c41 | 1976 | config AS_HAS_ARMV8_3 |
4d0831e8 | 1977 | def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) |
74afda40 | 1978 | |
3b446c7d ND |
1979 | config AS_HAS_CFI_NEGATE_RA_STATE |
1980 | def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) | |
1981 | ||
64a0b90a ZH |
1982 | config AS_HAS_LDAPR |
1983 | def_bool $(as-instr,.arch_extension rcpc) | |
1984 | ||
3cb7e662 | 1985 | endmenu # "ARMv8.3 architectural features" |
04ca3204 | 1986 | |
2c9d45b4 IV |
1987 | menu "ARMv8.4 architectural features" |
1988 | ||
1989 | config ARM64_AMU_EXTN | |
1990 | bool "Enable support for the Activity Monitors Unit CPU extension" | |
1991 | default y | |
1992 | help | |
1993 | The activity monitors extension is an optional extension introduced | |
1994 | by the ARMv8.4 CPU architecture. This enables support for version 1 | |
1995 | of the activity monitors architecture, AMUv1. | |
1996 | ||
1997 | To enable the use of this extension on CPUs that implement it, say Y. | |
1998 | ||
1999 | Note that for architectural reasons, firmware _must_ implement AMU | |
2000 | support when running on CPUs that present the activity monitors | |
2001 | extension. The required support is present in: | |
2002 | * Version 1.5 and later of the ARM Trusted Firmware | |
2003 | ||
2004 | For kernels that have this configuration enabled but boot with broken | |
2005 | firmware, you may need to say N here until the firmware is fixed. | |
2006 | Otherwise you may experience firmware panics or lockups when | |
2007 | accessing the counter registers. Even if you are not observing these | |
2008 | symptoms, the values returned by the register reads might not | |
2009 | correctly reflect reality. Most commonly, the value read will be 0, | |
2010 | indicating that the counter is not enabled. | |
2011 | ||
7c78f67e ZY |
2012 | config AS_HAS_ARMV8_4 |
2013 | def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) | |
2014 | ||
2015 | config ARM64_TLB_RANGE | |
2016 | bool "Enable support for tlbi range feature" | |
2017 | default y | |
2018 | depends on AS_HAS_ARMV8_4 | |
2019 | help | |
2020 | ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a | |
2021 | range of input addresses. | |
2022 | ||
2023 | The feature introduces new assembly instructions, and they were | |
2024 | support when binutils >= 2.30. | |
2025 | ||
3cb7e662 | 2026 | endmenu # "ARMv8.4 architectural features" |
04ca3204 | 2027 | |
3e6c69a0 MB |
2028 | menu "ARMv8.5 architectural features" |
2029 | ||
f469c032 VF |
2030 | config AS_HAS_ARMV8_5 |
2031 | def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) | |
2032 | ||
383499f8 DM |
2033 | config ARM64_BTI |
2034 | bool "Branch Target Identification support" | |
2035 | default y | |
2036 | help | |
2037 | Branch Target Identification (part of the ARMv8.5 Extensions) | |
2038 | provides a mechanism to limit the set of locations to which computed | |
2039 | branch instructions such as BR or BLR can jump. | |
2040 | ||
2041 | To make use of BTI on CPUs that support it, say Y. | |
2042 | ||
2043 | BTI is intended to provide complementary protection to other control | |
2044 | flow integrity protection mechanisms, such as the Pointer | |
2045 | authentication mechanism provided as part of the ARMv8.3 Extensions. | |
2046 | For this reason, it does not make sense to enable this option without | |
2047 | also enabling support for pointer authentication. Thus, when | |
2048 | enabling this option you should also select ARM64_PTR_AUTH=y. | |
2049 | ||
2050 | Userspace binaries must also be specifically compiled to make use of | |
2051 | this mechanism. If you say N here or the hardware does not support | |
2052 | BTI, such binaries can still run, but you get no additional | |
2053 | enforcement of branch destinations. | |
2054 | ||
97fed779 MB |
2055 | config ARM64_BTI_KERNEL |
2056 | bool "Use Branch Target Identification for kernel" | |
2057 | default y | |
2058 | depends on ARM64_BTI | |
b27a9f41 | 2059 | depends on ARM64_PTR_AUTH_KERNEL |
97fed779 | 2060 | depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI |
3a88d7c5 WD |
2061 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 |
2062 | depends on !CC_IS_GCC || GCC_VERSION >= 100100 | |
c0a454b9 MB |
2063 | # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 |
2064 | depends on !CC_IS_GCC | |
26299b3f | 2065 | depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) |
97fed779 MB |
2066 | help |
2067 | Build the kernel with Branch Target Identification annotations | |
2068 | and enable enforcement of this for kernel code. When this option | |
2069 | is enabled and the system supports BTI all kernel code including | |
2070 | modular code must have BTI enabled. | |
2071 | ||
2072 | config CC_HAS_BRANCH_PROT_PAC_RET_BTI | |
2073 | # GCC 9 or later, clang 8 or later | |
2074 | def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) | |
2075 | ||
3e6c69a0 MB |
2076 | config ARM64_E0PD |
2077 | bool "Enable support for E0PD" | |
2078 | default y | |
2079 | help | |
e717d93b WD |
2080 | E0PD (part of the ARMv8.5 extensions) allows us to ensure |
2081 | that EL0 accesses made via TTBR1 always fault in constant time, | |
2082 | providing similar benefits to KASLR as those provided by KPTI, but | |
2083 | with lower overhead and without disrupting legitimate access to | |
2084 | kernel memory such as SPE. | |
3e6c69a0 | 2085 | |
e717d93b | 2086 | This option enables E0PD for TTBR1 where available. |
3e6c69a0 | 2087 | |
89b94df9 VF |
2088 | config ARM64_AS_HAS_MTE |
2089 | # Initial support for MTE went in binutils 2.32.0, checked with | |
2090 | # ".arch armv8.5-a+memtag" below. However, this was incomplete | |
2091 | # as a late addition to the final architecture spec (LDGM/STGM) | |
2092 | # is only supported in the newer 2.32.x and 2.33 binutils | |
2093 | # versions, hence the extra "stgm" instruction check below. | |
2094 | def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) | |
2095 | ||
2096 | config ARM64_MTE | |
2097 | bool "Memory Tagging Extension support" | |
2098 | default y | |
2099 | depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI | |
f469c032 | 2100 | depends on AS_HAS_ARMV8_5 |
2decad92 | 2101 | depends on AS_HAS_LSE_ATOMICS |
98c970da VF |
2102 | # Required for tag checking in the uaccess routines |
2103 | depends on ARM64_PAN | |
f3ba50a7 | 2104 | select ARCH_HAS_SUBPAGE_FAULTS |
89b94df9 | 2105 | select ARCH_USES_HIGH_VMA_FLAGS |
b0284cd2 | 2106 | select ARCH_USES_PG_ARCH_X |
89b94df9 VF |
2107 | help |
2108 | Memory Tagging (part of the ARMv8.5 Extensions) provides | |
2109 | architectural support for run-time, always-on detection of | |
2110 | various classes of memory error to aid with software debugging | |
2111 | to eliminate vulnerabilities arising from memory-unsafe | |
2112 | languages. | |
2113 | ||
2114 | This option enables the support for the Memory Tagging | |
2115 | Extension at EL0 (i.e. for userspace). | |
2116 | ||
2117 | Selecting this option allows the feature to be detected at | |
2118 | runtime. Any secondary CPU not implementing this feature will | |
2119 | not be allowed a late bring-up. | |
2120 | ||
2121 | Userspace binaries that want to use this feature must | |
2122 | explicitly opt in. The mechanism for the userspace is | |
2123 | described in: | |
2124 | ||
6e4596c4 | 2125 | Documentation/arch/arm64/memory-tagging-extension.rst. |
89b94df9 | 2126 | |
3cb7e662 | 2127 | endmenu # "ARMv8.5 architectural features" |
3e6c69a0 | 2128 | |
18107f8a VM |
2129 | menu "ARMv8.7 architectural features" |
2130 | ||
2131 | config ARM64_EPAN | |
2132 | bool "Enable support for Enhanced Privileged Access Never (EPAN)" | |
2133 | default y | |
2134 | depends on ARM64_PAN | |
2135 | help | |
3cb7e662 JH |
2136 | Enhanced Privileged Access Never (EPAN) allows Privileged |
2137 | Access Never to be used with Execute-only mappings. | |
18107f8a | 2138 | |
3cb7e662 JH |
2139 | The feature is detected at runtime, and will remain disabled |
2140 | if the cpu does not implement the feature. | |
2141 | endmenu # "ARMv8.7 architectural features" | |
18107f8a | 2142 | |
ddd25ad1 DM |
2143 | config ARM64_SVE |
2144 | bool "ARM Scalable Vector Extension support" | |
2145 | default y | |
2146 | help | |
2147 | The Scalable Vector Extension (SVE) is an extension to the AArch64 | |
2148 | execution state which complements and extends the SIMD functionality | |
2149 | of the base architecture to support much larger vectors and to enable | |
2150 | additional vectorisation opportunities. | |
2151 | ||
2152 | To enable use of this extension on CPUs that implement it, say Y. | |
2153 | ||
06a916fe DM |
2154 | On CPUs that support the SVE2 extensions, this option will enable |
2155 | those too. | |
2156 | ||
5043694e DM |
2157 | Note that for architectural reasons, firmware _must_ implement SVE |
2158 | support when running on SVE capable hardware. The required support | |
2159 | is present in: | |
2160 | ||
2161 | * version 1.5 and later of the ARM Trusted Firmware | |
2162 | * the AArch64 boot wrapper since commit 5e1261e08abf | |
2163 | ("bootwrapper: SVE: Enable SVE for EL2 and below"). | |
2164 | ||
2165 | For other firmware implementations, consult the firmware documentation | |
2166 | or vendor. | |
2167 | ||
2168 | If you need the kernel to boot on SVE-capable hardware with broken | |
2169 | firmware, you may need to say N here until you get your firmware | |
2170 | fixed. Otherwise, you may experience firmware panics or lockups when | |
2171 | booting the kernel. If unsure and you are not observing these | |
2172 | symptoms, you should assume that it is safe to say Y. | |
fd045f6c | 2173 | |
a1f4ccd2 MB |
2174 | config ARM64_SME |
2175 | bool "ARM Scalable Matrix Extension support" | |
2176 | default y | |
2177 | depends on ARM64_SVE | |
2178 | help | |
2179 | The Scalable Matrix Extension (SME) is an extension to the AArch64 | |
2180 | execution state which utilises a substantial subset of the SVE | |
2181 | instruction set, together with the addition of new architectural | |
2182 | register state capable of holding two dimensional matrix tiles to | |
2183 | enable various matrix operations. | |
2184 | ||
bc3c03cc JT |
2185 | config ARM64_PSEUDO_NMI |
2186 | bool "Support for NMI-like interrupts" | |
3c9c1dcd | 2187 | select ARM_GIC_V3 |
bc3c03cc JT |
2188 | help |
2189 | Adds support for mimicking Non-Maskable Interrupts through the use of | |
2190 | GIC interrupt priority. This support requires version 3 or later of | |
bc15cf70 | 2191 | ARM GIC. |
bc3c03cc JT |
2192 | |
2193 | This high priority configuration for interrupts needs to be | |
2194 | explicitly enabled by setting the kernel parameter | |
2195 | "irqchip.gicv3_pseudo_nmi" to 1. | |
2196 | ||
2197 | If unsure, say N | |
2198 | ||
48ce8f80 JT |
2199 | if ARM64_PSEUDO_NMI |
2200 | config ARM64_DEBUG_PRIORITY_MASKING | |
2201 | bool "Debug interrupt priority masking" | |
2202 | help | |
2203 | This adds runtime checks to functions enabling/disabling | |
2204 | interrupts when using priority masking. The additional checks verify | |
2205 | the validity of ICC_PMR_EL1 when calling concerned functions. | |
2206 | ||
2207 | If unsure, say N | |
3cb7e662 | 2208 | endif # ARM64_PSEUDO_NMI |
48ce8f80 | 2209 | |
1e48ef7f | 2210 | config RELOCATABLE |
dd4bc607 | 2211 | bool "Build a relocatable kernel image" if EXPERT |
5cf896fb | 2212 | select ARCH_HAS_RELR |
dd4bc607 | 2213 | default y |
1e48ef7f AB |
2214 | help |
2215 | This builds the kernel as a Position Independent Executable (PIE), | |
2216 | which retains all relocation metadata required to relocate the | |
2217 | kernel binary at runtime to a different virtual address than the | |
2218 | address it was linked at. | |
2219 | Since AArch64 uses the RELA relocation format, this requires a | |
2220 | relocation pass at runtime even if the kernel is loaded at the | |
2221 | same address it was linked at. | |
2222 | ||
f80fb3a3 AB |
2223 | config RANDOMIZE_BASE |
2224 | bool "Randomize the address of the kernel image" | |
f80fb3a3 AB |
2225 | select RELOCATABLE |
2226 | help | |
2227 | Randomizes the virtual address at which the kernel image is | |
2228 | loaded, as a security feature that deters exploit attempts | |
2229 | relying on knowledge of the location of kernel internals. | |
2230 | ||
2231 | It is the bootloader's job to provide entropy, by passing a | |
2232 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
2233 | ||
2b5fe07a AB |
2234 | When booting via the UEFI stub, it will invoke the firmware's |
2235 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
2236 | to the kernel proper. In addition, it will randomise the physical | |
2237 | location of the kernel Image as well. | |
2238 | ||
f80fb3a3 AB |
2239 | If unsure, say N. |
2240 | ||
2241 | config RANDOMIZE_MODULE_REGION_FULL | |
f9c4ff2a | 2242 | bool "Randomize the module region over a 2 GB range" |
e71a4e1b | 2243 | depends on RANDOMIZE_BASE |
f80fb3a3 AB |
2244 | default y |
2245 | help | |
f9c4ff2a | 2246 | Randomizes the location of the module region inside a 2 GB window |
f2b9ba87 | 2247 | covering the core kernel. This way, it is less likely for modules |
f80fb3a3 AB |
2248 | to leak information about the location of core kernel data structures |
2249 | but it does imply that function calls between modules and the core | |
2250 | kernel will need to be resolved via veneers in the module PLT. | |
2251 | ||
2252 | When this option is not set, the module region will be randomized over | |
2253 | a limited range that contains the [_stext, _etext] interval of the | |
f9c4ff2a | 2254 | core kernel, so branch relocations are almost always in range unless |
ea3752ba MR |
2255 | the region is exhausted. In this particular case of region |
2256 | exhaustion, modules might be able to fall back to a larger 2GB area. | |
f80fb3a3 | 2257 | |
0a1213fa AB |
2258 | config CC_HAVE_STACKPROTECTOR_SYSREG |
2259 | def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) | |
2260 | ||
2261 | config STACKPROTECTOR_PER_TASK | |
2262 | def_bool y | |
2263 | depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG | |
2264 | ||
3b619e22 AB |
2265 | config UNWIND_PATCH_PAC_INTO_SCS |
2266 | bool "Enable shadow call stack dynamically using code patching" | |
fafdea34 | 2267 | # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated |
3b619e22 AB |
2268 | depends on CC_IS_CLANG && CLANG_VERSION >= 150000 |
2269 | depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET | |
2270 | depends on SHADOW_CALL_STACK | |
2271 | select UNWIND_TABLES | |
2272 | select DYNAMIC_SCS | |
2273 | ||
4602e575 RR |
2274 | config ARM64_CONTPTE |
2275 | bool "Contiguous PTE mappings for user memory" if EXPERT | |
2276 | depends on TRANSPARENT_HUGEPAGE | |
2277 | default y | |
2278 | help | |
2279 | When enabled, user mappings are configured using the PTE contiguous | |
2280 | bit, for any mappings that meet the size and alignment requirements. | |
2281 | This reduces TLB pressure and improves performance. | |
2282 | ||
3cb7e662 | 2283 | endmenu # "Kernel Features" |
8c2c3df3 CM |
2284 | |
2285 | menu "Boot options" | |
2286 | ||
5e89c55e LP |
2287 | config ARM64_ACPI_PARKING_PROTOCOL |
2288 | bool "Enable support for the ARM64 ACPI parking protocol" | |
2289 | depends on ACPI | |
2290 | help | |
2291 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
2292 | the kernel will not allow booting through the ARM64 ACPI parking | |
2293 | protocol even if the corresponding data is present in the ACPI | |
2294 | MADT table. | |
2295 | ||
8c2c3df3 CM |
2296 | config CMDLINE |
2297 | string "Default kernel command string" | |
2298 | default "" | |
2299 | help | |
2300 | Provide a set of default command-line options at build time by | |
2301 | entering them here. As a minimum, you should specify the the | |
2302 | root device (e.g. root=/dev/nfs). | |
2303 | ||
1e40d105 TH |
2304 | choice |
2305 | prompt "Kernel command line type" if CMDLINE != "" | |
2306 | default CMDLINE_FROM_BOOTLOADER | |
2307 | help | |
2308 | Choose how the kernel will handle the provided default kernel | |
2309 | command line string. | |
2310 | ||
2311 | config CMDLINE_FROM_BOOTLOADER | |
2312 | bool "Use bootloader kernel arguments if available" | |
2313 | help | |
2314 | Uses the command-line options passed by the boot loader. If | |
2315 | the boot loader doesn't provide any, the default kernel command | |
2316 | string provided in CMDLINE will be used. | |
2317 | ||
8c2c3df3 CM |
2318 | config CMDLINE_FORCE |
2319 | bool "Always use the default kernel command string" | |
2320 | help | |
2321 | Always use the default kernel command string, even if the boot | |
2322 | loader passes other arguments to the kernel. | |
2323 | This is useful if you cannot or don't want to change the | |
2324 | command-line options your boot loader passes to the kernel. | |
2325 | ||
1e40d105 TH |
2326 | endchoice |
2327 | ||
f4f75ad5 AB |
2328 | config EFI_STUB |
2329 | bool | |
2330 | ||
f84d0275 MS |
2331 | config EFI |
2332 | bool "UEFI runtime support" | |
2333 | depends on OF && !CPU_BIG_ENDIAN | |
b472db6c | 2334 | depends on KERNEL_MODE_NEON |
2c870e61 | 2335 | select ARCH_SUPPORTS_ACPI |
f84d0275 MS |
2336 | select LIBFDT |
2337 | select UCS2_STRING | |
2338 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 2339 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 | 2340 | select EFI_STUB |
2e0eb483 | 2341 | select EFI_GENERIC_STUB |
8d39cee0 | 2342 | imply IMA_SECURE_AND_OR_TRUSTED_BOOT |
f84d0275 MS |
2343 | default y |
2344 | help | |
2345 | This option provides support for runtime services provided | |
2346 | by UEFI firmware (such as non-volatile variables, realtime | |
3cb7e662 | 2347 | clock, and platform reset). A UEFI stub is also provided to |
3c7f2550 MS |
2348 | allow the kernel to be booted as an EFI application. This |
2349 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 2350 | |
d1ae8c00 YL |
2351 | config DMI |
2352 | bool "Enable support for SMBIOS (DMI) tables" | |
2353 | depends on EFI | |
2354 | default y | |
2355 | help | |
2356 | This enables SMBIOS/DMI feature for systems. | |
2357 | ||
2358 | This option is only useful on systems that have UEFI firmware. | |
2359 | However, even with this option, the resultant kernel should | |
2360 | continue to boot on existing non-UEFI platforms. | |
2361 | ||
3cb7e662 | 2362 | endmenu # "Boot options" |
8c2c3df3 | 2363 | |
166936ba LP |
2364 | menu "Power management options" |
2365 | ||
2366 | source "kernel/power/Kconfig" | |
2367 | ||
82869ac5 JM |
2368 | config ARCH_HIBERNATION_POSSIBLE |
2369 | def_bool y | |
2370 | depends on CPU_PM | |
2371 | ||
2372 | config ARCH_HIBERNATION_HEADER | |
2373 | def_bool y | |
2374 | depends on HIBERNATION | |
2375 | ||
166936ba LP |
2376 | config ARCH_SUSPEND_POSSIBLE |
2377 | def_bool y | |
2378 | ||
3cb7e662 | 2379 | endmenu # "Power management options" |
166936ba | 2380 | |
1307220d LP |
2381 | menu "CPU Power Management" |
2382 | ||
2383 | source "drivers/cpuidle/Kconfig" | |
2384 | ||
52e7e816 RH |
2385 | source "drivers/cpufreq/Kconfig" |
2386 | ||
3cb7e662 | 2387 | endmenu # "CPU Power Management" |
52e7e816 | 2388 | |
b6a02173 GG |
2389 | source "drivers/acpi/Kconfig" |
2390 | ||
c3eb5b14 MZ |
2391 | source "arch/arm64/kvm/Kconfig" |
2392 |