Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
21266be9 | 6 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
8c2c3df3 | 7 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 8 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 9 | select ARCH_HAS_GCOV_PROFILE_ALL |
5e4c7549 | 10 | select ARCH_HAS_KCOV |
308c09f1 | 11 | select ARCH_HAS_SG_CHAIN |
1f85008e | 12 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 13 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 14 | select ARCH_SUPPORTS_ATOMIC_RMW |
56166230 | 15 | select ARCH_SUPPORTS_NUMA_BALANCING |
9170100e | 16 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 17 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 18 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 19 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 20 | select ARM_AMBA |
1aee5d7a | 21 | select ARM_ARCH_TIMER |
c4188edc | 22 | select ARM_GIC |
875cbf3e | 23 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 24 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 25 | select ARM_GIC_V3 |
19812729 | 26 | select ARM_GIC_V3_ITS if PCI_MSI |
bff60792 | 27 | select ARM_PSCI_FW |
adace895 | 28 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 29 | select CLONE_BACKWARDS |
7ca2ef33 | 30 | select COMMON_CLK |
166936ba | 31 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 32 | select DCACHE_WORD_ACCESS |
ef37566c | 33 | select EDAC_SUPPORT |
2f34f173 | 34 | select FRAME_POINTER |
d4932f9e | 35 | select GENERIC_ALLOCATOR |
8c2c3df3 | 36 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 37 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 38 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 39 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 40 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
41 | select GENERIC_IRQ_PROBE |
42 | select GENERIC_IRQ_SHOW | |
6544e67b | 43 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 44 | select GENERIC_PCI_IOMAP |
65cd4f6c | 45 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 46 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
47 | select GENERIC_STRNCPY_FROM_USER |
48 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 49 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 50 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 51 | select HARDIRQS_SW_RESEND |
5284e1b4 | 52 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 53 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 54 | select HAVE_ARCH_BITREVERSE |
324420bf | 55 | select HAVE_ARCH_HUGE_VMAP |
9732cafd | 56 | select HAVE_ARCH_JUMP_LABEL |
f1b9032f | 57 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 58 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
59 | select HAVE_ARCH_MMAP_RND_BITS |
60 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
a1ae65b2 | 61 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 62 | select HAVE_ARCH_TRACEHOOK |
8ee70879 YS |
63 | select HAVE_ARCH_TRANSPARENT_HUGEPAGE |
64 | select HAVE_ARM_SMCCC | |
6077776b | 65 | select HAVE_EBPF_JIT |
af64d2aa | 66 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 67 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 68 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 69 | select HAVE_CMPXCHG_LOCAL |
8ee70879 | 70 | select HAVE_CONTEXT_TRACKING |
9b2a60c4 | 71 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 72 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 | 73 | select HAVE_DMA_API_DEBUG |
6ac2104d | 74 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 75 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 76 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 77 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
78 | select HAVE_FUNCTION_TRACER |
79 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 80 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 81 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 82 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 83 | select HAVE_MEMBLOCK |
1a2db300 | 84 | select HAVE_MEMBLOCK_NODE_MAP if NUMA |
55834a77 | 85 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 86 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
87 | select HAVE_PERF_REGS |
88 | select HAVE_PERF_USER_STACK_DUMP | |
0a8ea52c | 89 | select HAVE_REGS_AND_STACK_ACCESS_API |
5e5f6dc1 | 90 | select HAVE_RCU_TABLE_FREE |
055b1212 | 91 | select HAVE_SYSCALL_TRACEPOINTS |
2dd0e8d2 | 92 | select HAVE_KPROBES |
fcfd708b | 93 | select HAVE_KRETPROBES if HAVE_KPROBES |
876945db | 94 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 95 | select IRQ_DOMAIN |
e8557d1f | 96 | select IRQ_FORCED_THREADING |
fea2acaa | 97 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
98 | select NO_BOOTMEM |
99 | select OF | |
100 | select OF_EARLY_FLATTREE | |
8ee70879 | 101 | select OF_NUMA if NUMA && OF |
9bf14b7c | 102 | select OF_RESERVED_MEM |
8c2c3df3 | 103 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
104 | select POWER_RESET |
105 | select POWER_SUPPLY | |
8c2c3df3 | 106 | select SPARSE_IRQ |
7ac57a89 | 107 | select SYSCTL_EXCEPTION_TRACE |
8c2c3df3 CM |
108 | help |
109 | ARM 64-bit (AArch64) Linux support. | |
110 | ||
111 | config 64BIT | |
112 | def_bool y | |
113 | ||
114 | config ARCH_PHYS_ADDR_T_64BIT | |
115 | def_bool y | |
116 | ||
117 | config MMU | |
118 | def_bool y | |
119 | ||
030c4d24 MR |
120 | config ARM64_PAGE_SHIFT |
121 | int | |
122 | default 16 if ARM64_64K_PAGES | |
123 | default 14 if ARM64_16K_PAGES | |
124 | default 12 | |
125 | ||
126 | config ARM64_CONT_SHIFT | |
127 | int | |
128 | default 5 if ARM64_64K_PAGES | |
129 | default 7 if ARM64_16K_PAGES | |
130 | default 4 | |
131 | ||
8f0d3aa9 DC |
132 | config ARCH_MMAP_RND_BITS_MIN |
133 | default 14 if ARM64_64K_PAGES | |
134 | default 16 if ARM64_16K_PAGES | |
135 | default 18 | |
136 | ||
137 | # max bits determined by the following formula: | |
138 | # VA_BITS - PAGE_SHIFT - 3 | |
139 | config ARCH_MMAP_RND_BITS_MAX | |
140 | default 19 if ARM64_VA_BITS=36 | |
141 | default 24 if ARM64_VA_BITS=39 | |
142 | default 27 if ARM64_VA_BITS=42 | |
143 | default 30 if ARM64_VA_BITS=47 | |
144 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
145 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
146 | default 33 if ARM64_VA_BITS=48 | |
147 | default 14 if ARM64_64K_PAGES | |
148 | default 16 if ARM64_16K_PAGES | |
149 | default 18 | |
150 | ||
151 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
152 | default 7 if ARM64_64K_PAGES | |
153 | default 9 if ARM64_16K_PAGES | |
154 | default 11 | |
155 | ||
156 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
157 | default 16 | |
158 | ||
ce816fa8 | 159 | config NO_IOPORT_MAP |
d1e6dc91 | 160 | def_bool y if !PCI |
8c2c3df3 CM |
161 | |
162 | config STACKTRACE_SUPPORT | |
163 | def_bool y | |
164 | ||
bf0c4e04 JVS |
165 | config ILLEGAL_POINTER_VALUE |
166 | hex | |
167 | default 0xdead000000000000 | |
168 | ||
8c2c3df3 CM |
169 | config LOCKDEP_SUPPORT |
170 | def_bool y | |
171 | ||
172 | config TRACE_IRQFLAGS_SUPPORT | |
173 | def_bool y | |
174 | ||
c209f799 | 175 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
176 | def_bool y |
177 | ||
9fb7410f DM |
178 | config GENERIC_BUG |
179 | def_bool y | |
180 | depends on BUG | |
181 | ||
182 | config GENERIC_BUG_RELATIVE_POINTERS | |
183 | def_bool y | |
184 | depends on GENERIC_BUG | |
185 | ||
8c2c3df3 CM |
186 | config GENERIC_HWEIGHT |
187 | def_bool y | |
188 | ||
189 | config GENERIC_CSUM | |
190 | def_bool y | |
191 | ||
192 | config GENERIC_CALIBRATE_DELAY | |
193 | def_bool y | |
194 | ||
19e7640d | 195 | config ZONE_DMA |
8c2c3df3 CM |
196 | def_bool y |
197 | ||
29e56940 SC |
198 | config HAVE_GENERIC_RCU_GUP |
199 | def_bool y | |
200 | ||
8c2c3df3 CM |
201 | config ARCH_DMA_ADDR_T_64BIT |
202 | def_bool y | |
203 | ||
204 | config NEED_DMA_MAP_STATE | |
205 | def_bool y | |
206 | ||
207 | config NEED_SG_DMA_LENGTH | |
208 | def_bool y | |
209 | ||
4b3dc967 WD |
210 | config SMP |
211 | def_bool y | |
212 | ||
8c2c3df3 CM |
213 | config SWIOTLB |
214 | def_bool y | |
215 | ||
216 | config IOMMU_HELPER | |
217 | def_bool SWIOTLB | |
218 | ||
4cfb3613 AB |
219 | config KERNEL_MODE_NEON |
220 | def_bool y | |
221 | ||
92cc15fc RH |
222 | config FIX_EARLYCON_MEM |
223 | def_bool y | |
224 | ||
9f25e6ad KS |
225 | config PGTABLE_LEVELS |
226 | int | |
21539939 | 227 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
228 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
229 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
230 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
231 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
232 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 233 | |
8c2c3df3 CM |
234 | source "init/Kconfig" |
235 | ||
236 | source "kernel/Kconfig.freezer" | |
237 | ||
6a377491 | 238 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
239 | |
240 | menu "Bus support" | |
241 | ||
d1e6dc91 LD |
242 | config PCI |
243 | bool "PCI support" | |
244 | help | |
245 | This feature enables support for PCI bus system. If you say Y | |
246 | here, the kernel will include drivers and infrastructure code | |
247 | to support PCI bus devices. | |
248 | ||
249 | config PCI_DOMAINS | |
250 | def_bool PCI | |
251 | ||
252 | config PCI_DOMAINS_GENERIC | |
253 | def_bool PCI | |
254 | ||
255 | config PCI_SYSCALL | |
256 | def_bool PCI | |
257 | ||
258 | source "drivers/pci/Kconfig" | |
d1e6dc91 | 259 | |
8c2c3df3 CM |
260 | endmenu |
261 | ||
262 | menu "Kernel Features" | |
263 | ||
c0a01b84 AP |
264 | menu "ARM errata workarounds via the alternatives framework" |
265 | ||
266 | config ARM64_ERRATUM_826319 | |
267 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
268 | default y | |
269 | help | |
270 | This option adds an alternative code sequence to work around ARM | |
271 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
272 | AXI master interface and an L2 cache. | |
273 | ||
274 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
275 | and is unable to accept a certain write via this interface, it will | |
276 | not progress on read data presented on the read data channel and the | |
277 | system can deadlock. | |
278 | ||
279 | The workaround promotes data cache clean instructions to | |
280 | data cache clean-and-invalidate. | |
281 | Please note that this does not necessarily enable the workaround, | |
282 | as it depends on the alternative framework, which will only patch | |
283 | the kernel if an affected CPU is detected. | |
284 | ||
285 | If unsure, say Y. | |
286 | ||
287 | config ARM64_ERRATUM_827319 | |
288 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
289 | default y | |
290 | help | |
291 | This option adds an alternative code sequence to work around ARM | |
292 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
293 | master interface and an L2 cache. | |
294 | ||
295 | Under certain conditions this erratum can cause a clean line eviction | |
296 | to occur at the same time as another transaction to the same address | |
297 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
298 | interconnect reorders the two transactions. | |
299 | ||
300 | The workaround promotes data cache clean instructions to | |
301 | data cache clean-and-invalidate. | |
302 | Please note that this does not necessarily enable the workaround, | |
303 | as it depends on the alternative framework, which will only patch | |
304 | the kernel if an affected CPU is detected. | |
305 | ||
306 | If unsure, say Y. | |
307 | ||
308 | config ARM64_ERRATUM_824069 | |
309 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
310 | default y | |
311 | help | |
312 | This option adds an alternative code sequence to work around ARM | |
313 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
314 | to a coherent interconnect. | |
315 | ||
316 | If a Cortex-A53 processor is executing a store or prefetch for | |
317 | write instruction at the same time as a processor in another | |
318 | cluster is executing a cache maintenance operation to the same | |
319 | address, then this erratum might cause a clean cache line to be | |
320 | incorrectly marked as dirty. | |
321 | ||
322 | The workaround promotes data cache clean instructions to | |
323 | data cache clean-and-invalidate. | |
324 | Please note that this option does not necessarily enable the | |
325 | workaround, as it depends on the alternative framework, which will | |
326 | only patch the kernel if an affected CPU is detected. | |
327 | ||
328 | If unsure, say Y. | |
329 | ||
330 | config ARM64_ERRATUM_819472 | |
331 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
332 | default y | |
333 | help | |
334 | This option adds an alternative code sequence to work around ARM | |
335 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
336 | present when it is connected to a coherent interconnect. | |
337 | ||
338 | If the processor is executing a load and store exclusive sequence at | |
339 | the same time as a processor in another cluster is executing a cache | |
340 | maintenance operation to the same address, then this erratum might | |
341 | cause data corruption. | |
342 | ||
343 | The workaround promotes data cache clean instructions to | |
344 | data cache clean-and-invalidate. | |
345 | Please note that this does not necessarily enable the workaround, | |
346 | as it depends on the alternative framework, which will only patch | |
347 | the kernel if an affected CPU is detected. | |
348 | ||
349 | If unsure, say Y. | |
350 | ||
351 | config ARM64_ERRATUM_832075 | |
352 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
353 | default y | |
354 | help | |
355 | This option adds an alternative code sequence to work around ARM | |
356 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
357 | ||
358 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
359 | instructions to Write-Back memory are mixed with Device loads. | |
360 | ||
361 | The workaround is to promote device loads to use Load-Acquire | |
362 | semantics. | |
363 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
364 | as it depends on the alternative framework, which will only patch |
365 | the kernel if an affected CPU is detected. | |
366 | ||
367 | If unsure, say Y. | |
368 | ||
369 | config ARM64_ERRATUM_834220 | |
370 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
371 | depends on KVM | |
372 | default y | |
373 | help | |
374 | This option adds an alternative code sequence to work around ARM | |
375 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
376 | ||
377 | Affected Cortex-A57 parts might report a Stage 2 translation | |
378 | fault as the result of a Stage 1 fault for load crossing a | |
379 | page boundary when there is a permission or device memory | |
380 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
381 | ||
382 | The workaround is to verify that the Stage 1 translation | |
383 | doesn't generate a fault before handling the Stage 2 fault. | |
384 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
385 | as it depends on the alternative framework, which will only patch |
386 | the kernel if an affected CPU is detected. | |
387 | ||
388 | If unsure, say Y. | |
389 | ||
905e8c5d WD |
390 | config ARM64_ERRATUM_845719 |
391 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
392 | depends on COMPAT | |
393 | default y | |
394 | help | |
395 | This option adds an alternative code sequence to work around ARM | |
396 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
397 | ||
398 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
399 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
400 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
401 | might return incorrect data. | |
402 | ||
403 | The workaround is to write the contextidr_el1 register on exception | |
404 | return to a 32-bit task. | |
405 | Please note that this does not necessarily enable the workaround, | |
406 | as it depends on the alternative framework, which will only patch | |
407 | the kernel if an affected CPU is detected. | |
408 | ||
409 | If unsure, say Y. | |
410 | ||
df057cc7 WD |
411 | config ARM64_ERRATUM_843419 |
412 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
413 | depends on MODULES | |
414 | default y | |
fd045f6c | 415 | select ARM64_MODULE_CMODEL_LARGE |
df057cc7 WD |
416 | help |
417 | This option builds kernel modules using the large memory model in | |
418 | order to avoid the use of the ADRP instruction, which can cause | |
419 | a subsequent memory access to use an incorrect address on Cortex-A53 | |
420 | parts up to r0p4. | |
421 | ||
422 | Note that the kernel itself must be linked with a version of ld | |
423 | which fixes potentially affected ADRP instructions through the | |
424 | use of veneers. | |
425 | ||
426 | If unsure, say Y. | |
427 | ||
94100970 RR |
428 | config CAVIUM_ERRATUM_22375 |
429 | bool "Cavium erratum 22375, 24313" | |
430 | default y | |
431 | help | |
432 | Enable workaround for erratum 22375, 24313. | |
433 | ||
434 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
435 | with small impact affecting only ITS table allocation. | |
436 | ||
437 | erratum 22375: only alloc 8MB table size | |
438 | erratum 24313: ignore memory access type | |
439 | ||
440 | The fixes are in ITS initialization and basically ignore memory access | |
441 | type and table size provided by the TYPER and BASER registers. | |
442 | ||
443 | If unsure, say Y. | |
444 | ||
fbf8f40e GK |
445 | config CAVIUM_ERRATUM_23144 |
446 | bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" | |
447 | depends on NUMA | |
448 | default y | |
449 | help | |
450 | ITS SYNC command hang for cross node io and collections/cpu mapping. | |
451 | ||
452 | If unsure, say Y. | |
453 | ||
6d4e11c5 RR |
454 | config CAVIUM_ERRATUM_23154 |
455 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
456 | default y | |
457 | help | |
458 | The gicv3 of ThunderX requires a modified version for | |
459 | reading the IAR status to ensure data synchronization | |
460 | (access to icc_iar1_el1 is not sync'ed before and after). | |
461 | ||
462 | If unsure, say Y. | |
463 | ||
104a0c02 AP |
464 | config CAVIUM_ERRATUM_27456 |
465 | bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" | |
466 | default y | |
467 | help | |
468 | On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI | |
469 | instructions may cause the icache to become corrupted if it | |
470 | contains data for a non-current ASID. The fix is to | |
471 | invalidate the icache when changing the mm context. | |
472 | ||
473 | If unsure, say Y. | |
474 | ||
c0a01b84 AP |
475 | endmenu |
476 | ||
477 | ||
e41ceed0 JL |
478 | choice |
479 | prompt "Page size" | |
480 | default ARM64_4K_PAGES | |
481 | help | |
482 | Page size (translation granule) configuration. | |
483 | ||
484 | config ARM64_4K_PAGES | |
485 | bool "4KB" | |
486 | help | |
487 | This feature enables 4KB pages support. | |
488 | ||
44eaacf1 SP |
489 | config ARM64_16K_PAGES |
490 | bool "16KB" | |
491 | help | |
492 | The system will use 16KB pages support. AArch32 emulation | |
493 | requires applications compiled with 16K (or a multiple of 16K) | |
494 | aligned segments. | |
495 | ||
8c2c3df3 | 496 | config ARM64_64K_PAGES |
e41ceed0 | 497 | bool "64KB" |
8c2c3df3 CM |
498 | help |
499 | This feature enables 64KB pages support (4KB by default) | |
500 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
501 | look-up. AArch32 emulation requires applications compiled |
502 | with 64K aligned segments. | |
8c2c3df3 | 503 | |
e41ceed0 JL |
504 | endchoice |
505 | ||
506 | choice | |
507 | prompt "Virtual address space size" | |
508 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 509 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
510 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
511 | help | |
512 | Allows choosing one of multiple possible virtual address | |
513 | space sizes. The level of translation table is determined by | |
514 | a combination of page size and virtual address space size. | |
515 | ||
21539939 | 516 | config ARM64_VA_BITS_36 |
56a3f30e | 517 | bool "36-bit" if EXPERT |
21539939 SP |
518 | depends on ARM64_16K_PAGES |
519 | ||
e41ceed0 JL |
520 | config ARM64_VA_BITS_39 |
521 | bool "39-bit" | |
522 | depends on ARM64_4K_PAGES | |
523 | ||
524 | config ARM64_VA_BITS_42 | |
525 | bool "42-bit" | |
526 | depends on ARM64_64K_PAGES | |
527 | ||
44eaacf1 SP |
528 | config ARM64_VA_BITS_47 |
529 | bool "47-bit" | |
530 | depends on ARM64_16K_PAGES | |
531 | ||
c79b954b JL |
532 | config ARM64_VA_BITS_48 |
533 | bool "48-bit" | |
c79b954b | 534 | |
e41ceed0 JL |
535 | endchoice |
536 | ||
537 | config ARM64_VA_BITS | |
538 | int | |
21539939 | 539 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
540 | default 39 if ARM64_VA_BITS_39 |
541 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 542 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 543 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 544 | |
a872013d WD |
545 | config CPU_BIG_ENDIAN |
546 | bool "Build big-endian kernel" | |
547 | help | |
548 | Say Y if you plan on running a kernel in big-endian mode. | |
549 | ||
f6e763b9 MB |
550 | config SCHED_MC |
551 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
552 | help |
553 | Multi-core scheduler support improves the CPU scheduler's decision | |
554 | making when dealing with multi-core CPU chips at a cost of slightly | |
555 | increased overhead in some places. If unsure say N here. | |
556 | ||
557 | config SCHED_SMT | |
558 | bool "SMT scheduler support" | |
f6e763b9 MB |
559 | help |
560 | Improves the CPU scheduler's decision making when dealing with | |
561 | MultiThreading at a cost of slightly increased overhead in some | |
562 | places. If unsure say N here. | |
563 | ||
8c2c3df3 | 564 | config NR_CPUS |
62aa9655 GK |
565 | int "Maximum number of CPUs (2-4096)" |
566 | range 2 4096 | |
15942853 | 567 | # These have to remain sorted largest to smallest |
e3672649 | 568 | default "64" |
8c2c3df3 | 569 | |
9327e2c6 MR |
570 | config HOTPLUG_CPU |
571 | bool "Support for hot-pluggable CPUs" | |
217d453d | 572 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
573 | help |
574 | Say Y here to experiment with turning CPUs off and on. CPUs | |
575 | can be controlled through /sys/devices/system/cpu. | |
576 | ||
1a2db300 GK |
577 | # Common NUMA Features |
578 | config NUMA | |
579 | bool "Numa Memory Allocation and Scheduler Support" | |
580 | depends on SMP | |
581 | help | |
582 | Enable NUMA (Non Uniform Memory Access) support. | |
583 | ||
584 | The kernel will try to allocate memory used by a CPU on the | |
585 | local memory of the CPU and add some more | |
586 | NUMA awareness to the kernel. | |
587 | ||
588 | config NODES_SHIFT | |
589 | int "Maximum NUMA Nodes (as a power of 2)" | |
590 | range 1 10 | |
591 | default "2" | |
592 | depends on NEED_MULTIPLE_NODES | |
593 | help | |
594 | Specify the maximum number of NUMA Nodes available on the target | |
595 | system. Increases memory reserved to accommodate various tables. | |
596 | ||
597 | config USE_PERCPU_NUMA_NODE_ID | |
598 | def_bool y | |
599 | depends on NUMA | |
600 | ||
8c2c3df3 | 601 | source kernel/Kconfig.preempt |
f90df5e2 | 602 | source kernel/Kconfig.hz |
8c2c3df3 | 603 | |
83863f25 | 604 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
da24eb1f | 605 | depends on !HIBERNATION |
83863f25 LA |
606 | def_bool y |
607 | ||
8c2c3df3 CM |
608 | config ARCH_HAS_HOLES_MEMORYMODEL |
609 | def_bool y if SPARSEMEM | |
610 | ||
611 | config ARCH_SPARSEMEM_ENABLE | |
612 | def_bool y | |
613 | select SPARSEMEM_VMEMMAP_ENABLE | |
614 | ||
615 | config ARCH_SPARSEMEM_DEFAULT | |
616 | def_bool ARCH_SPARSEMEM_ENABLE | |
617 | ||
618 | config ARCH_SELECT_MEMORY_MODEL | |
619 | def_bool ARCH_SPARSEMEM_ENABLE | |
620 | ||
621 | config HAVE_ARCH_PFN_VALID | |
622 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
623 | ||
624 | config HW_PERF_EVENTS | |
6475b2d8 MR |
625 | def_bool y |
626 | depends on ARM_PMU | |
8c2c3df3 | 627 | |
084bd298 SC |
628 | config SYS_SUPPORTS_HUGETLBFS |
629 | def_bool y | |
630 | ||
084bd298 | 631 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 632 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 633 | |
a41dc0e8 CM |
634 | config ARCH_HAS_CACHE_LINE_SIZE |
635 | def_bool y | |
636 | ||
8c2c3df3 CM |
637 | source "mm/Kconfig" |
638 | ||
a1ae65b2 AT |
639 | config SECCOMP |
640 | bool "Enable seccomp to safely compute untrusted bytecode" | |
641 | ---help--- | |
642 | This kernel feature is useful for number crunching applications | |
643 | that may need to compute untrusted bytecode during their | |
644 | execution. By using pipes or other transports made available to | |
645 | the process as file descriptors supporting the read/write | |
646 | syscalls, it's possible to isolate those applications in | |
647 | their own address space using seccomp. Once seccomp is | |
648 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
649 | and the task is only allowed to execute a few safe syscalls | |
650 | defined by each seccomp mode. | |
651 | ||
dfd57bc3 SS |
652 | config PARAVIRT |
653 | bool "Enable paravirtualization code" | |
654 | help | |
655 | This changes the kernel so it can modify itself when it is run | |
656 | under a hypervisor, potentially improving performance significantly | |
657 | over full virtualization. | |
658 | ||
659 | config PARAVIRT_TIME_ACCOUNTING | |
660 | bool "Paravirtual steal time accounting" | |
661 | select PARAVIRT | |
662 | default n | |
663 | help | |
664 | Select this option to enable fine granularity task steal time | |
665 | accounting. Time spent executing other tasks in parallel with | |
666 | the current vCPU is discounted from the vCPU power. To account for | |
667 | that, there can be a small performance impact. | |
668 | ||
669 | If in doubt, say N here. | |
670 | ||
d28f6df1 GL |
671 | config KEXEC |
672 | depends on PM_SLEEP_SMP | |
673 | select KEXEC_CORE | |
674 | bool "kexec system call" | |
675 | ---help--- | |
676 | kexec is a system call that implements the ability to shutdown your | |
677 | current kernel, and to start another kernel. It is like a reboot | |
678 | but it is independent of the system firmware. And like a reboot | |
679 | you can start any kernel with it, not just Linux. | |
680 | ||
aa42aa13 SS |
681 | config XEN_DOM0 |
682 | def_bool y | |
683 | depends on XEN | |
684 | ||
685 | config XEN | |
c2ba1f7d | 686 | bool "Xen guest support on ARM64" |
aa42aa13 | 687 | depends on ARM64 && OF |
83862ccf | 688 | select SWIOTLB_XEN |
dfd57bc3 | 689 | select PARAVIRT |
aa42aa13 SS |
690 | help |
691 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
692 | ||
d03bb145 SC |
693 | config FORCE_MAX_ZONEORDER |
694 | int | |
695 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 696 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 697 | default "11" |
44eaacf1 SP |
698 | help |
699 | The kernel memory allocator divides physically contiguous memory | |
700 | blocks into "zones", where each zone is a power of two number of | |
701 | pages. This option selects the largest power of two that the kernel | |
702 | keeps in the memory allocator. If you need to allocate very large | |
703 | blocks of physically contiguous memory, then you may need to | |
704 | increase this value. | |
705 | ||
706 | This config option is actually maximum order plus one. For example, | |
707 | a value of 11 means that the largest free memory block is 2^10 pages. | |
708 | ||
709 | We make sure that we can allocate upto a HugePage size for each configuration. | |
710 | Hence we have : | |
711 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
712 | ||
713 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
714 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 715 | |
1b907f46 WD |
716 | menuconfig ARMV8_DEPRECATED |
717 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
718 | depends on COMPAT | |
719 | help | |
720 | Legacy software support may require certain instructions | |
721 | that have been deprecated or obsoleted in the architecture. | |
722 | ||
723 | Enable this config to enable selective emulation of these | |
724 | features. | |
725 | ||
726 | If unsure, say Y | |
727 | ||
728 | if ARMV8_DEPRECATED | |
729 | ||
730 | config SWP_EMULATION | |
731 | bool "Emulate SWP/SWPB instructions" | |
732 | help | |
733 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
734 | they are always undefined. Say Y here to enable software | |
735 | emulation of these instructions for userspace using LDXR/STXR. | |
736 | ||
737 | In some older versions of glibc [<=2.8] SWP is used during futex | |
738 | trylock() operations with the assumption that the code will not | |
739 | be preempted. This invalid assumption may be more likely to fail | |
740 | with SWP emulation enabled, leading to deadlock of the user | |
741 | application. | |
742 | ||
743 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
744 | on an external transaction monitoring block called a global | |
745 | monitor to maintain update atomicity. If your system does not | |
746 | implement a global monitor, this option can cause programs that | |
747 | perform SWP operations to uncached memory to deadlock. | |
748 | ||
749 | If unsure, say Y | |
750 | ||
751 | config CP15_BARRIER_EMULATION | |
752 | bool "Emulate CP15 Barrier instructions" | |
753 | help | |
754 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
755 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
756 | strongly recommended to use the ISB, DSB, and DMB | |
757 | instructions instead. | |
758 | ||
759 | Say Y here to enable software emulation of these | |
760 | instructions for AArch32 userspace code. When this option is | |
761 | enabled, CP15 barrier usage is traced which can help | |
762 | identify software that needs updating. | |
763 | ||
764 | If unsure, say Y | |
765 | ||
2d888f48 SP |
766 | config SETEND_EMULATION |
767 | bool "Emulate SETEND instruction" | |
768 | help | |
769 | The SETEND instruction alters the data-endianness of the | |
770 | AArch32 EL0, and is deprecated in ARMv8. | |
771 | ||
772 | Say Y here to enable software emulation of the instruction | |
773 | for AArch32 userspace code. | |
774 | ||
775 | Note: All the cpus on the system must have mixed endian support at EL0 | |
776 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
777 | endian - is hotplugged in after this feature has been enabled, there could | |
778 | be unexpected results in the applications. | |
779 | ||
780 | If unsure, say Y | |
1b907f46 WD |
781 | endif |
782 | ||
0e4a0709 WD |
783 | menu "ARMv8.1 architectural features" |
784 | ||
785 | config ARM64_HW_AFDBM | |
786 | bool "Support for hardware updates of the Access and Dirty page flags" | |
787 | default y | |
788 | help | |
789 | The ARMv8.1 architecture extensions introduce support for | |
790 | hardware updates of the access and dirty information in page | |
791 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
792 | capable processors, accesses to pages with PTE_AF cleared will | |
793 | set this bit instead of raising an access flag fault. | |
794 | Similarly, writes to read-only pages with the DBM bit set will | |
795 | clear the read-only bit (AP[2]) instead of raising a | |
796 | permission fault. | |
797 | ||
798 | Kernels built with this configuration option enabled continue | |
799 | to work on pre-ARMv8.1 hardware and the performance impact is | |
800 | minimal. If unsure, say Y. | |
801 | ||
802 | config ARM64_PAN | |
803 | bool "Enable support for Privileged Access Never (PAN)" | |
804 | default y | |
805 | help | |
806 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
807 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
808 | memory directly. | |
809 | ||
810 | Choosing this option will cause any unprotected (not using | |
811 | copy_to_user et al) memory access to fail with a permission fault. | |
812 | ||
813 | The feature is detected at runtime, and will remain as a 'nop' | |
814 | instruction if the cpu does not implement the feature. | |
815 | ||
816 | config ARM64_LSE_ATOMICS | |
817 | bool "Atomic instructions" | |
818 | help | |
819 | As part of the Large System Extensions, ARMv8.1 introduces new | |
820 | atomic instructions that are designed specifically to scale in | |
821 | very large systems. | |
822 | ||
823 | Say Y here to make use of these instructions for the in-kernel | |
824 | atomic routines. This incurs a small overhead on CPUs that do | |
825 | not support these instructions and requires the kernel to be | |
826 | built with binutils >= 2.25. | |
827 | ||
1f364c8c MZ |
828 | config ARM64_VHE |
829 | bool "Enable support for Virtualization Host Extensions (VHE)" | |
830 | default y | |
831 | help | |
832 | Virtualization Host Extensions (VHE) allow the kernel to run | |
833 | directly at EL2 (instead of EL1) on processors that support | |
834 | it. This leads to better performance for KVM, as they reduce | |
835 | the cost of the world switch. | |
836 | ||
837 | Selecting this option allows the VHE feature to be detected | |
838 | at runtime, and does not affect processors that do not | |
839 | implement this feature. | |
840 | ||
0e4a0709 WD |
841 | endmenu |
842 | ||
f993318b WD |
843 | menu "ARMv8.2 architectural features" |
844 | ||
57f4959b JM |
845 | config ARM64_UAO |
846 | bool "Enable support for User Access Override (UAO)" | |
847 | default y | |
848 | help | |
849 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
850 | causes the 'unprivileged' variant of the load/store instructions to | |
851 | be overriden to be privileged. | |
852 | ||
853 | This option changes get_user() and friends to use the 'unprivileged' | |
854 | variant of the load/store instructions. This ensures that user-space | |
855 | really did have access to the supplied memory. When addr_limit is | |
856 | set to kernel memory the UAO bit will be set, allowing privileged | |
857 | access to kernel memory. | |
858 | ||
859 | Choosing this option will cause copy_to_user() et al to use user-space | |
860 | memory permissions. | |
861 | ||
862 | The feature is detected at runtime, the kernel will use the | |
863 | regular load/store instructions if the cpu does not implement the | |
864 | feature. | |
865 | ||
f993318b WD |
866 | endmenu |
867 | ||
fd045f6c AB |
868 | config ARM64_MODULE_CMODEL_LARGE |
869 | bool | |
870 | ||
871 | config ARM64_MODULE_PLTS | |
872 | bool | |
873 | select ARM64_MODULE_CMODEL_LARGE | |
874 | select HAVE_MOD_ARCH_SPECIFIC | |
875 | ||
1e48ef7f AB |
876 | config RELOCATABLE |
877 | bool | |
878 | help | |
879 | This builds the kernel as a Position Independent Executable (PIE), | |
880 | which retains all relocation metadata required to relocate the | |
881 | kernel binary at runtime to a different virtual address than the | |
882 | address it was linked at. | |
883 | Since AArch64 uses the RELA relocation format, this requires a | |
884 | relocation pass at runtime even if the kernel is loaded at the | |
885 | same address it was linked at. | |
886 | ||
f80fb3a3 AB |
887 | config RANDOMIZE_BASE |
888 | bool "Randomize the address of the kernel image" | |
889 | select ARM64_MODULE_PLTS | |
890 | select RELOCATABLE | |
891 | help | |
892 | Randomizes the virtual address at which the kernel image is | |
893 | loaded, as a security feature that deters exploit attempts | |
894 | relying on knowledge of the location of kernel internals. | |
895 | ||
896 | It is the bootloader's job to provide entropy, by passing a | |
897 | random u64 value in /chosen/kaslr-seed at kernel entry. | |
898 | ||
2b5fe07a AB |
899 | When booting via the UEFI stub, it will invoke the firmware's |
900 | EFI_RNG_PROTOCOL implementation (if available) to supply entropy | |
901 | to the kernel proper. In addition, it will randomise the physical | |
902 | location of the kernel Image as well. | |
903 | ||
f80fb3a3 AB |
904 | If unsure, say N. |
905 | ||
906 | config RANDOMIZE_MODULE_REGION_FULL | |
907 | bool "Randomize the module region independently from the core kernel" | |
908 | depends on RANDOMIZE_BASE | |
909 | default y | |
910 | help | |
911 | Randomizes the location of the module region without considering the | |
912 | location of the core kernel. This way, it is impossible for modules | |
913 | to leak information about the location of core kernel data structures | |
914 | but it does imply that function calls between modules and the core | |
915 | kernel will need to be resolved via veneers in the module PLT. | |
916 | ||
917 | When this option is not set, the module region will be randomized over | |
918 | a limited range that contains the [_stext, _etext] interval of the | |
919 | core kernel, so branch relocations are always in range. | |
920 | ||
8c2c3df3 CM |
921 | endmenu |
922 | ||
923 | menu "Boot options" | |
924 | ||
5e89c55e LP |
925 | config ARM64_ACPI_PARKING_PROTOCOL |
926 | bool "Enable support for the ARM64 ACPI parking protocol" | |
927 | depends on ACPI | |
928 | help | |
929 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
930 | the kernel will not allow booting through the ARM64 ACPI parking | |
931 | protocol even if the corresponding data is present in the ACPI | |
932 | MADT table. | |
933 | ||
8c2c3df3 CM |
934 | config CMDLINE |
935 | string "Default kernel command string" | |
936 | default "" | |
937 | help | |
938 | Provide a set of default command-line options at build time by | |
939 | entering them here. As a minimum, you should specify the the | |
940 | root device (e.g. root=/dev/nfs). | |
941 | ||
942 | config CMDLINE_FORCE | |
943 | bool "Always use the default kernel command string" | |
944 | help | |
945 | Always use the default kernel command string, even if the boot | |
946 | loader passes other arguments to the kernel. | |
947 | This is useful if you cannot or don't want to change the | |
948 | command-line options your boot loader passes to the kernel. | |
949 | ||
f4f75ad5 AB |
950 | config EFI_STUB |
951 | bool | |
952 | ||
f84d0275 MS |
953 | config EFI |
954 | bool "UEFI runtime support" | |
955 | depends on OF && !CPU_BIG_ENDIAN | |
956 | select LIBFDT | |
957 | select UCS2_STRING | |
958 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 959 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
960 | select EFI_STUB |
961 | select EFI_ARMSTUB | |
f84d0275 MS |
962 | default y |
963 | help | |
964 | This option provides support for runtime services provided | |
965 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
966 | clock, and platform reset). A UEFI stub is also provided to |
967 | allow the kernel to be booted as an EFI application. This | |
968 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 969 | |
d1ae8c00 YL |
970 | config DMI |
971 | bool "Enable support for SMBIOS (DMI) tables" | |
972 | depends on EFI | |
973 | default y | |
974 | help | |
975 | This enables SMBIOS/DMI feature for systems. | |
976 | ||
977 | This option is only useful on systems that have UEFI firmware. | |
978 | However, even with this option, the resultant kernel should | |
979 | continue to boot on existing non-UEFI platforms. | |
980 | ||
8c2c3df3 CM |
981 | endmenu |
982 | ||
983 | menu "Userspace binary formats" | |
984 | ||
985 | source "fs/Kconfig.binfmt" | |
986 | ||
987 | config COMPAT | |
988 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 989 | depends on ARM64_4K_PAGES || EXPERT |
8c2c3df3 | 990 | select COMPAT_BINFMT_ELF |
af1839eb | 991 | select HAVE_UID16 |
84b9e9b4 | 992 | select OLD_SIGSUSPEND3 |
51682036 | 993 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
994 | help |
995 | This option enables support for a 32-bit EL0 running under a 64-bit | |
996 | kernel at EL1. AArch32-specific components such as system calls, | |
997 | the user helper functions, VFP support and the ptrace interface are | |
998 | handled appropriately by the kernel. | |
999 | ||
44eaacf1 SP |
1000 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
1001 | that you will only be able to execute AArch32 binaries that were compiled | |
1002 | with page size aligned segments. | |
a8fcd8b1 | 1003 | |
8c2c3df3 CM |
1004 | If you want to execute 32-bit userspace applications, say Y. |
1005 | ||
1006 | config SYSVIPC_COMPAT | |
1007 | def_bool y | |
1008 | depends on COMPAT && SYSVIPC | |
1009 | ||
1010 | endmenu | |
1011 | ||
166936ba LP |
1012 | menu "Power management options" |
1013 | ||
1014 | source "kernel/power/Kconfig" | |
1015 | ||
82869ac5 JM |
1016 | config ARCH_HIBERNATION_POSSIBLE |
1017 | def_bool y | |
1018 | depends on CPU_PM | |
1019 | ||
1020 | config ARCH_HIBERNATION_HEADER | |
1021 | def_bool y | |
1022 | depends on HIBERNATION | |
1023 | ||
166936ba LP |
1024 | config ARCH_SUSPEND_POSSIBLE |
1025 | def_bool y | |
1026 | ||
166936ba LP |
1027 | endmenu |
1028 | ||
1307220d LP |
1029 | menu "CPU Power Management" |
1030 | ||
1031 | source "drivers/cpuidle/Kconfig" | |
1032 | ||
52e7e816 RH |
1033 | source "drivers/cpufreq/Kconfig" |
1034 | ||
1035 | endmenu | |
1036 | ||
8c2c3df3 CM |
1037 | source "net/Kconfig" |
1038 | ||
1039 | source "drivers/Kconfig" | |
1040 | ||
f84d0275 MS |
1041 | source "drivers/firmware/Kconfig" |
1042 | ||
b6a02173 GG |
1043 | source "drivers/acpi/Kconfig" |
1044 | ||
8c2c3df3 CM |
1045 | source "fs/Kconfig" |
1046 | ||
c3eb5b14 MZ |
1047 | source "arch/arm64/kvm/Kconfig" |
1048 | ||
8c2c3df3 CM |
1049 | source "arch/arm64/Kconfig.debug" |
1050 | ||
1051 | source "security/Kconfig" | |
1052 | ||
1053 | source "crypto/Kconfig" | |
2c98833a AB |
1054 | if CRYPTO |
1055 | source "arch/arm64/crypto/Kconfig" | |
1056 | endif | |
8c2c3df3 CM |
1057 | |
1058 | source "lib/Kconfig" |