Commit | Line | Data |
---|---|---|
8c2c3df3 CM |
1 | config ARM64 |
2 | def_bool y | |
b6197b93 | 3 | select ACPI_CCA_REQUIRED if ACPI |
d8f4f161 | 4 | select ACPI_GENERIC_GSI if ACPI |
6933de0c | 5 | select ACPI_REDUCED_HARDWARE_ONLY if ACPI |
21266be9 | 6 | select ARCH_HAS_DEVMEM_IS_ALLOWED |
8c2c3df3 | 7 | select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE |
2b68f6ca | 8 | select ARCH_HAS_ELF_RANDOMIZE |
957e3fac | 9 | select ARCH_HAS_GCOV_PROFILE_ALL |
308c09f1 | 10 | select ARCH_HAS_SG_CHAIN |
1f85008e | 11 | select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST |
c63c8700 | 12 | select ARCH_USE_CMPXCHG_LOCKREF |
4badad35 | 13 | select ARCH_SUPPORTS_ATOMIC_RMW |
9170100e | 14 | select ARCH_WANT_OPTIONAL_GPIOLIB |
6212a512 | 15 | select ARCH_WANT_COMPAT_IPC_PARSE_VERSION |
b6f35981 | 16 | select ARCH_WANT_FRAME_POINTERS |
f0b7f8a4 | 17 | select ARCH_HAS_UBSAN_SANITIZE_ALL |
25c92a37 | 18 | select ARM_AMBA |
1aee5d7a | 19 | select ARM_ARCH_TIMER |
c4188edc | 20 | select ARM_GIC |
875cbf3e | 21 | select AUDIT_ARCH_COMPAT_GENERIC |
853a33ce | 22 | select ARM_GIC_V2M if PCI_MSI |
021f6537 | 23 | select ARM_GIC_V3 |
19812729 | 24 | select ARM_GIC_V3_ITS if PCI_MSI |
bff60792 | 25 | select ARM_PSCI_FW |
adace895 | 26 | select BUILDTIME_EXTABLE_SORT |
db2789b5 | 27 | select CLONE_BACKWARDS |
7ca2ef33 | 28 | select COMMON_CLK |
166936ba | 29 | select CPU_PM if (SUSPEND || CPU_IDLE) |
7bc13fd3 | 30 | select DCACHE_WORD_ACCESS |
ef37566c | 31 | select EDAC_SUPPORT |
2f34f173 | 32 | select FRAME_POINTER |
d4932f9e | 33 | select GENERIC_ALLOCATOR |
8c2c3df3 | 34 | select GENERIC_CLOCKEVENTS |
4b3dc967 | 35 | select GENERIC_CLOCKEVENTS_BROADCAST |
3be1a5c4 | 36 | select GENERIC_CPU_AUTOPROBE |
bf4b558e | 37 | select GENERIC_EARLY_IOREMAP |
2314ee4d | 38 | select GENERIC_IDLE_POLL_SETUP |
8c2c3df3 CM |
39 | select GENERIC_IRQ_PROBE |
40 | select GENERIC_IRQ_SHOW | |
6544e67b | 41 | select GENERIC_IRQ_SHOW_LEVEL |
cb61f676 | 42 | select GENERIC_PCI_IOMAP |
65cd4f6c | 43 | select GENERIC_SCHED_CLOCK |
8c2c3df3 | 44 | select GENERIC_SMP_IDLE_THREAD |
12a0ef7b WD |
45 | select GENERIC_STRNCPY_FROM_USER |
46 | select GENERIC_STRNLEN_USER | |
8c2c3df3 | 47 | select GENERIC_TIME_VSYSCALL |
a1ddc74a | 48 | select HANDLE_DOMAIN_IRQ |
8c2c3df3 | 49 | select HARDIRQS_SW_RESEND |
5284e1b4 | 50 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
875cbf3e | 51 | select HAVE_ARCH_AUDITSYSCALL |
8e7a4cef | 52 | select HAVE_ARCH_BITREVERSE |
9732cafd | 53 | select HAVE_ARCH_JUMP_LABEL |
f1b9032f | 54 | select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) |
9529247d | 55 | select HAVE_ARCH_KGDB |
8f0d3aa9 DC |
56 | select HAVE_ARCH_MMAP_RND_BITS |
57 | select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT | |
a1ae65b2 | 58 | select HAVE_ARCH_SECCOMP_FILTER |
8c2c3df3 | 59 | select HAVE_ARCH_TRACEHOOK |
e54bcde3 | 60 | select HAVE_BPF_JIT |
af64d2aa | 61 | select HAVE_C_RECORDMCOUNT |
c0c264ae | 62 | select HAVE_CC_STACKPROTECTOR |
5284e1b4 | 63 | select HAVE_CMPXCHG_DOUBLE |
95eff6b2 | 64 | select HAVE_CMPXCHG_LOCAL |
9b2a60c4 | 65 | select HAVE_DEBUG_BUGVERBOSE |
b69ec42b | 66 | select HAVE_DEBUG_KMEMLEAK |
8c2c3df3 | 67 | select HAVE_DMA_API_DEBUG |
6ac2104d | 68 | select HAVE_DMA_CONTIGUOUS |
bd7d38db | 69 | select HAVE_DYNAMIC_FTRACE |
50afc33a | 70 | select HAVE_EFFICIENT_UNALIGNED_ACCESS |
af64d2aa | 71 | select HAVE_FTRACE_MCOUNT_RECORD |
819e50e2 AT |
72 | select HAVE_FUNCTION_TRACER |
73 | select HAVE_FUNCTION_GRAPH_TRACER | |
8c2c3df3 | 74 | select HAVE_GENERIC_DMA_COHERENT |
8c2c3df3 | 75 | select HAVE_HW_BREAKPOINT if PERF_EVENTS |
24da208d | 76 | select HAVE_IRQ_TIME_ACCOUNTING |
8c2c3df3 | 77 | select HAVE_MEMBLOCK |
55834a77 | 78 | select HAVE_PATA_PLATFORM |
8c2c3df3 | 79 | select HAVE_PERF_EVENTS |
2ee0d7fd JP |
80 | select HAVE_PERF_REGS |
81 | select HAVE_PERF_USER_STACK_DUMP | |
5e5f6dc1 | 82 | select HAVE_RCU_TABLE_FREE |
055b1212 | 83 | select HAVE_SYSCALL_TRACEPOINTS |
876945db | 84 | select IOMMU_DMA if IOMMU_SUPPORT |
8c2c3df3 | 85 | select IRQ_DOMAIN |
e8557d1f | 86 | select IRQ_FORCED_THREADING |
fea2acaa | 87 | select MODULES_USE_ELF_RELA |
8c2c3df3 CM |
88 | select NO_BOOTMEM |
89 | select OF | |
90 | select OF_EARLY_FLATTREE | |
9bf14b7c | 91 | select OF_RESERVED_MEM |
8c2c3df3 | 92 | select PERF_USE_VMALLOC |
aa1e8ec1 CM |
93 | select POWER_RESET |
94 | select POWER_SUPPLY | |
8c2c3df3 CM |
95 | select RTC_LIB |
96 | select SPARSE_IRQ | |
7ac57a89 | 97 | select SYSCTL_EXCEPTION_TRACE |
6c81fe79 | 98 | select HAVE_CONTEXT_TRACKING |
14457459 | 99 | select HAVE_ARM_SMCCC |
8c2c3df3 CM |
100 | help |
101 | ARM 64-bit (AArch64) Linux support. | |
102 | ||
103 | config 64BIT | |
104 | def_bool y | |
105 | ||
106 | config ARCH_PHYS_ADDR_T_64BIT | |
107 | def_bool y | |
108 | ||
109 | config MMU | |
110 | def_bool y | |
111 | ||
8f0d3aa9 DC |
112 | config ARCH_MMAP_RND_BITS_MIN |
113 | default 14 if ARM64_64K_PAGES | |
114 | default 16 if ARM64_16K_PAGES | |
115 | default 18 | |
116 | ||
117 | # max bits determined by the following formula: | |
118 | # VA_BITS - PAGE_SHIFT - 3 | |
119 | config ARCH_MMAP_RND_BITS_MAX | |
120 | default 19 if ARM64_VA_BITS=36 | |
121 | default 24 if ARM64_VA_BITS=39 | |
122 | default 27 if ARM64_VA_BITS=42 | |
123 | default 30 if ARM64_VA_BITS=47 | |
124 | default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES | |
125 | default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES | |
126 | default 33 if ARM64_VA_BITS=48 | |
127 | default 14 if ARM64_64K_PAGES | |
128 | default 16 if ARM64_16K_PAGES | |
129 | default 18 | |
130 | ||
131 | config ARCH_MMAP_RND_COMPAT_BITS_MIN | |
132 | default 7 if ARM64_64K_PAGES | |
133 | default 9 if ARM64_16K_PAGES | |
134 | default 11 | |
135 | ||
136 | config ARCH_MMAP_RND_COMPAT_BITS_MAX | |
137 | default 16 | |
138 | ||
ce816fa8 | 139 | config NO_IOPORT_MAP |
d1e6dc91 | 140 | def_bool y if !PCI |
8c2c3df3 CM |
141 | |
142 | config STACKTRACE_SUPPORT | |
143 | def_bool y | |
144 | ||
bf0c4e04 JVS |
145 | config ILLEGAL_POINTER_VALUE |
146 | hex | |
147 | default 0xdead000000000000 | |
148 | ||
8c2c3df3 CM |
149 | config LOCKDEP_SUPPORT |
150 | def_bool y | |
151 | ||
152 | config TRACE_IRQFLAGS_SUPPORT | |
153 | def_bool y | |
154 | ||
c209f799 | 155 | config RWSEM_XCHGADD_ALGORITHM |
8c2c3df3 CM |
156 | def_bool y |
157 | ||
9fb7410f DM |
158 | config GENERIC_BUG |
159 | def_bool y | |
160 | depends on BUG | |
161 | ||
162 | config GENERIC_BUG_RELATIVE_POINTERS | |
163 | def_bool y | |
164 | depends on GENERIC_BUG | |
165 | ||
8c2c3df3 CM |
166 | config GENERIC_HWEIGHT |
167 | def_bool y | |
168 | ||
169 | config GENERIC_CSUM | |
170 | def_bool y | |
171 | ||
172 | config GENERIC_CALIBRATE_DELAY | |
173 | def_bool y | |
174 | ||
19e7640d | 175 | config ZONE_DMA |
8c2c3df3 CM |
176 | def_bool y |
177 | ||
29e56940 SC |
178 | config HAVE_GENERIC_RCU_GUP |
179 | def_bool y | |
180 | ||
8c2c3df3 CM |
181 | config ARCH_DMA_ADDR_T_64BIT |
182 | def_bool y | |
183 | ||
184 | config NEED_DMA_MAP_STATE | |
185 | def_bool y | |
186 | ||
187 | config NEED_SG_DMA_LENGTH | |
188 | def_bool y | |
189 | ||
4b3dc967 WD |
190 | config SMP |
191 | def_bool y | |
192 | ||
8c2c3df3 CM |
193 | config SWIOTLB |
194 | def_bool y | |
195 | ||
196 | config IOMMU_HELPER | |
197 | def_bool SWIOTLB | |
198 | ||
4cfb3613 AB |
199 | config KERNEL_MODE_NEON |
200 | def_bool y | |
201 | ||
92cc15fc RH |
202 | config FIX_EARLYCON_MEM |
203 | def_bool y | |
204 | ||
9f25e6ad KS |
205 | config PGTABLE_LEVELS |
206 | int | |
21539939 | 207 | default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 |
9f25e6ad KS |
208 | default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 |
209 | default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
210 | default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 | |
44eaacf1 SP |
211 | default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 |
212 | default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 | |
9f25e6ad | 213 | |
8c2c3df3 CM |
214 | source "init/Kconfig" |
215 | ||
216 | source "kernel/Kconfig.freezer" | |
217 | ||
6a377491 | 218 | source "arch/arm64/Kconfig.platforms" |
8c2c3df3 CM |
219 | |
220 | menu "Bus support" | |
221 | ||
d1e6dc91 LD |
222 | config PCI |
223 | bool "PCI support" | |
224 | help | |
225 | This feature enables support for PCI bus system. If you say Y | |
226 | here, the kernel will include drivers and infrastructure code | |
227 | to support PCI bus devices. | |
228 | ||
229 | config PCI_DOMAINS | |
230 | def_bool PCI | |
231 | ||
232 | config PCI_DOMAINS_GENERIC | |
233 | def_bool PCI | |
234 | ||
235 | config PCI_SYSCALL | |
236 | def_bool PCI | |
237 | ||
238 | source "drivers/pci/Kconfig" | |
239 | source "drivers/pci/pcie/Kconfig" | |
240 | source "drivers/pci/hotplug/Kconfig" | |
241 | ||
8c2c3df3 CM |
242 | endmenu |
243 | ||
244 | menu "Kernel Features" | |
245 | ||
c0a01b84 AP |
246 | menu "ARM errata workarounds via the alternatives framework" |
247 | ||
248 | config ARM64_ERRATUM_826319 | |
249 | bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" | |
250 | default y | |
251 | help | |
252 | This option adds an alternative code sequence to work around ARM | |
253 | erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or | |
254 | AXI master interface and an L2 cache. | |
255 | ||
256 | If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors | |
257 | and is unable to accept a certain write via this interface, it will | |
258 | not progress on read data presented on the read data channel and the | |
259 | system can deadlock. | |
260 | ||
261 | The workaround promotes data cache clean instructions to | |
262 | data cache clean-and-invalidate. | |
263 | Please note that this does not necessarily enable the workaround, | |
264 | as it depends on the alternative framework, which will only patch | |
265 | the kernel if an affected CPU is detected. | |
266 | ||
267 | If unsure, say Y. | |
268 | ||
269 | config ARM64_ERRATUM_827319 | |
270 | bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" | |
271 | default y | |
272 | help | |
273 | This option adds an alternative code sequence to work around ARM | |
274 | erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI | |
275 | master interface and an L2 cache. | |
276 | ||
277 | Under certain conditions this erratum can cause a clean line eviction | |
278 | to occur at the same time as another transaction to the same address | |
279 | on the AMBA 5 CHI interface, which can cause data corruption if the | |
280 | interconnect reorders the two transactions. | |
281 | ||
282 | The workaround promotes data cache clean instructions to | |
283 | data cache clean-and-invalidate. | |
284 | Please note that this does not necessarily enable the workaround, | |
285 | as it depends on the alternative framework, which will only patch | |
286 | the kernel if an affected CPU is detected. | |
287 | ||
288 | If unsure, say Y. | |
289 | ||
290 | config ARM64_ERRATUM_824069 | |
291 | bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" | |
292 | default y | |
293 | help | |
294 | This option adds an alternative code sequence to work around ARM | |
295 | erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected | |
296 | to a coherent interconnect. | |
297 | ||
298 | If a Cortex-A53 processor is executing a store or prefetch for | |
299 | write instruction at the same time as a processor in another | |
300 | cluster is executing a cache maintenance operation to the same | |
301 | address, then this erratum might cause a clean cache line to be | |
302 | incorrectly marked as dirty. | |
303 | ||
304 | The workaround promotes data cache clean instructions to | |
305 | data cache clean-and-invalidate. | |
306 | Please note that this option does not necessarily enable the | |
307 | workaround, as it depends on the alternative framework, which will | |
308 | only patch the kernel if an affected CPU is detected. | |
309 | ||
310 | If unsure, say Y. | |
311 | ||
312 | config ARM64_ERRATUM_819472 | |
313 | bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" | |
314 | default y | |
315 | help | |
316 | This option adds an alternative code sequence to work around ARM | |
317 | erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache | |
318 | present when it is connected to a coherent interconnect. | |
319 | ||
320 | If the processor is executing a load and store exclusive sequence at | |
321 | the same time as a processor in another cluster is executing a cache | |
322 | maintenance operation to the same address, then this erratum might | |
323 | cause data corruption. | |
324 | ||
325 | The workaround promotes data cache clean instructions to | |
326 | data cache clean-and-invalidate. | |
327 | Please note that this does not necessarily enable the workaround, | |
328 | as it depends on the alternative framework, which will only patch | |
329 | the kernel if an affected CPU is detected. | |
330 | ||
331 | If unsure, say Y. | |
332 | ||
333 | config ARM64_ERRATUM_832075 | |
334 | bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" | |
335 | default y | |
336 | help | |
337 | This option adds an alternative code sequence to work around ARM | |
338 | erratum 832075 on Cortex-A57 parts up to r1p2. | |
339 | ||
340 | Affected Cortex-A57 parts might deadlock when exclusive load/store | |
341 | instructions to Write-Back memory are mixed with Device loads. | |
342 | ||
343 | The workaround is to promote device loads to use Load-Acquire | |
344 | semantics. | |
345 | Please note that this does not necessarily enable the workaround, | |
498cd5c3 MZ |
346 | as it depends on the alternative framework, which will only patch |
347 | the kernel if an affected CPU is detected. | |
348 | ||
349 | If unsure, say Y. | |
350 | ||
351 | config ARM64_ERRATUM_834220 | |
352 | bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" | |
353 | depends on KVM | |
354 | default y | |
355 | help | |
356 | This option adds an alternative code sequence to work around ARM | |
357 | erratum 834220 on Cortex-A57 parts up to r1p2. | |
358 | ||
359 | Affected Cortex-A57 parts might report a Stage 2 translation | |
360 | fault as the result of a Stage 1 fault for load crossing a | |
361 | page boundary when there is a permission or device memory | |
362 | alignment fault at Stage 1 and a translation fault at Stage 2. | |
363 | ||
364 | The workaround is to verify that the Stage 1 translation | |
365 | doesn't generate a fault before handling the Stage 2 fault. | |
366 | Please note that this does not necessarily enable the workaround, | |
c0a01b84 AP |
367 | as it depends on the alternative framework, which will only patch |
368 | the kernel if an affected CPU is detected. | |
369 | ||
370 | If unsure, say Y. | |
371 | ||
905e8c5d WD |
372 | config ARM64_ERRATUM_845719 |
373 | bool "Cortex-A53: 845719: a load might read incorrect data" | |
374 | depends on COMPAT | |
375 | default y | |
376 | help | |
377 | This option adds an alternative code sequence to work around ARM | |
378 | erratum 845719 on Cortex-A53 parts up to r0p4. | |
379 | ||
380 | When running a compat (AArch32) userspace on an affected Cortex-A53 | |
381 | part, a load at EL0 from a virtual address that matches the bottom 32 | |
382 | bits of the virtual address used by a recent load at (AArch64) EL1 | |
383 | might return incorrect data. | |
384 | ||
385 | The workaround is to write the contextidr_el1 register on exception | |
386 | return to a 32-bit task. | |
387 | Please note that this does not necessarily enable the workaround, | |
388 | as it depends on the alternative framework, which will only patch | |
389 | the kernel if an affected CPU is detected. | |
390 | ||
391 | If unsure, say Y. | |
392 | ||
df057cc7 WD |
393 | config ARM64_ERRATUM_843419 |
394 | bool "Cortex-A53: 843419: A load or store might access an incorrect address" | |
395 | depends on MODULES | |
396 | default y | |
397 | help | |
398 | This option builds kernel modules using the large memory model in | |
399 | order to avoid the use of the ADRP instruction, which can cause | |
400 | a subsequent memory access to use an incorrect address on Cortex-A53 | |
401 | parts up to r0p4. | |
402 | ||
403 | Note that the kernel itself must be linked with a version of ld | |
404 | which fixes potentially affected ADRP instructions through the | |
405 | use of veneers. | |
406 | ||
407 | If unsure, say Y. | |
408 | ||
94100970 RR |
409 | config CAVIUM_ERRATUM_22375 |
410 | bool "Cavium erratum 22375, 24313" | |
411 | default y | |
412 | help | |
413 | Enable workaround for erratum 22375, 24313. | |
414 | ||
415 | This implements two gicv3-its errata workarounds for ThunderX. Both | |
416 | with small impact affecting only ITS table allocation. | |
417 | ||
418 | erratum 22375: only alloc 8MB table size | |
419 | erratum 24313: ignore memory access type | |
420 | ||
421 | The fixes are in ITS initialization and basically ignore memory access | |
422 | type and table size provided by the TYPER and BASER registers. | |
423 | ||
424 | If unsure, say Y. | |
425 | ||
6d4e11c5 RR |
426 | config CAVIUM_ERRATUM_23154 |
427 | bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" | |
428 | default y | |
429 | help | |
430 | The gicv3 of ThunderX requires a modified version for | |
431 | reading the IAR status to ensure data synchronization | |
432 | (access to icc_iar1_el1 is not sync'ed before and after). | |
433 | ||
434 | If unsure, say Y. | |
435 | ||
c0a01b84 AP |
436 | endmenu |
437 | ||
438 | ||
e41ceed0 JL |
439 | choice |
440 | prompt "Page size" | |
441 | default ARM64_4K_PAGES | |
442 | help | |
443 | Page size (translation granule) configuration. | |
444 | ||
445 | config ARM64_4K_PAGES | |
446 | bool "4KB" | |
447 | help | |
448 | This feature enables 4KB pages support. | |
449 | ||
44eaacf1 SP |
450 | config ARM64_16K_PAGES |
451 | bool "16KB" | |
452 | help | |
453 | The system will use 16KB pages support. AArch32 emulation | |
454 | requires applications compiled with 16K (or a multiple of 16K) | |
455 | aligned segments. | |
456 | ||
8c2c3df3 | 457 | config ARM64_64K_PAGES |
e41ceed0 | 458 | bool "64KB" |
8c2c3df3 CM |
459 | help |
460 | This feature enables 64KB pages support (4KB by default) | |
461 | allowing only two levels of page tables and faster TLB | |
db488be3 SP |
462 | look-up. AArch32 emulation requires applications compiled |
463 | with 64K aligned segments. | |
8c2c3df3 | 464 | |
e41ceed0 JL |
465 | endchoice |
466 | ||
467 | choice | |
468 | prompt "Virtual address space size" | |
469 | default ARM64_VA_BITS_39 if ARM64_4K_PAGES | |
44eaacf1 | 470 | default ARM64_VA_BITS_47 if ARM64_16K_PAGES |
e41ceed0 JL |
471 | default ARM64_VA_BITS_42 if ARM64_64K_PAGES |
472 | help | |
473 | Allows choosing one of multiple possible virtual address | |
474 | space sizes. The level of translation table is determined by | |
475 | a combination of page size and virtual address space size. | |
476 | ||
21539939 | 477 | config ARM64_VA_BITS_36 |
56a3f30e | 478 | bool "36-bit" if EXPERT |
21539939 SP |
479 | depends on ARM64_16K_PAGES |
480 | ||
e41ceed0 JL |
481 | config ARM64_VA_BITS_39 |
482 | bool "39-bit" | |
483 | depends on ARM64_4K_PAGES | |
484 | ||
485 | config ARM64_VA_BITS_42 | |
486 | bool "42-bit" | |
487 | depends on ARM64_64K_PAGES | |
488 | ||
44eaacf1 SP |
489 | config ARM64_VA_BITS_47 |
490 | bool "47-bit" | |
491 | depends on ARM64_16K_PAGES | |
492 | ||
c79b954b JL |
493 | config ARM64_VA_BITS_48 |
494 | bool "48-bit" | |
c79b954b | 495 | |
e41ceed0 JL |
496 | endchoice |
497 | ||
498 | config ARM64_VA_BITS | |
499 | int | |
21539939 | 500 | default 36 if ARM64_VA_BITS_36 |
e41ceed0 JL |
501 | default 39 if ARM64_VA_BITS_39 |
502 | default 42 if ARM64_VA_BITS_42 | |
44eaacf1 | 503 | default 47 if ARM64_VA_BITS_47 |
c79b954b | 504 | default 48 if ARM64_VA_BITS_48 |
e41ceed0 | 505 | |
a872013d WD |
506 | config CPU_BIG_ENDIAN |
507 | bool "Build big-endian kernel" | |
508 | help | |
509 | Say Y if you plan on running a kernel in big-endian mode. | |
510 | ||
f6e763b9 MB |
511 | config SCHED_MC |
512 | bool "Multi-core scheduler support" | |
f6e763b9 MB |
513 | help |
514 | Multi-core scheduler support improves the CPU scheduler's decision | |
515 | making when dealing with multi-core CPU chips at a cost of slightly | |
516 | increased overhead in some places. If unsure say N here. | |
517 | ||
518 | config SCHED_SMT | |
519 | bool "SMT scheduler support" | |
f6e763b9 MB |
520 | help |
521 | Improves the CPU scheduler's decision making when dealing with | |
522 | MultiThreading at a cost of slightly increased overhead in some | |
523 | places. If unsure say N here. | |
524 | ||
8c2c3df3 | 525 | config NR_CPUS |
62aa9655 GK |
526 | int "Maximum number of CPUs (2-4096)" |
527 | range 2 4096 | |
15942853 | 528 | # These have to remain sorted largest to smallest |
e3672649 | 529 | default "64" |
8c2c3df3 | 530 | |
9327e2c6 MR |
531 | config HOTPLUG_CPU |
532 | bool "Support for hot-pluggable CPUs" | |
217d453d | 533 | select GENERIC_IRQ_MIGRATION |
9327e2c6 MR |
534 | help |
535 | Say Y here to experiment with turning CPUs off and on. CPUs | |
536 | can be controlled through /sys/devices/system/cpu. | |
537 | ||
8c2c3df3 | 538 | source kernel/Kconfig.preempt |
f90df5e2 | 539 | source kernel/Kconfig.hz |
8c2c3df3 | 540 | |
83863f25 LA |
541 | config ARCH_SUPPORTS_DEBUG_PAGEALLOC |
542 | def_bool y | |
543 | ||
8c2c3df3 CM |
544 | config ARCH_HAS_HOLES_MEMORYMODEL |
545 | def_bool y if SPARSEMEM | |
546 | ||
547 | config ARCH_SPARSEMEM_ENABLE | |
548 | def_bool y | |
549 | select SPARSEMEM_VMEMMAP_ENABLE | |
550 | ||
551 | config ARCH_SPARSEMEM_DEFAULT | |
552 | def_bool ARCH_SPARSEMEM_ENABLE | |
553 | ||
554 | config ARCH_SELECT_MEMORY_MODEL | |
555 | def_bool ARCH_SPARSEMEM_ENABLE | |
556 | ||
557 | config HAVE_ARCH_PFN_VALID | |
558 | def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM | |
559 | ||
560 | config HW_PERF_EVENTS | |
6475b2d8 MR |
561 | def_bool y |
562 | depends on ARM_PMU | |
8c2c3df3 | 563 | |
084bd298 SC |
564 | config SYS_SUPPORTS_HUGETLBFS |
565 | def_bool y | |
566 | ||
084bd298 | 567 | config ARCH_WANT_HUGE_PMD_SHARE |
21539939 | 568 | def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) |
084bd298 | 569 | |
af074848 SC |
570 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
571 | def_bool y | |
572 | ||
a41dc0e8 CM |
573 | config ARCH_HAS_CACHE_LINE_SIZE |
574 | def_bool y | |
575 | ||
8c2c3df3 CM |
576 | source "mm/Kconfig" |
577 | ||
a1ae65b2 AT |
578 | config SECCOMP |
579 | bool "Enable seccomp to safely compute untrusted bytecode" | |
580 | ---help--- | |
581 | This kernel feature is useful for number crunching applications | |
582 | that may need to compute untrusted bytecode during their | |
583 | execution. By using pipes or other transports made available to | |
584 | the process as file descriptors supporting the read/write | |
585 | syscalls, it's possible to isolate those applications in | |
586 | their own address space using seccomp. Once seccomp is | |
587 | enabled via prctl(PR_SET_SECCOMP), it cannot be disabled | |
588 | and the task is only allowed to execute a few safe syscalls | |
589 | defined by each seccomp mode. | |
590 | ||
dfd57bc3 SS |
591 | config PARAVIRT |
592 | bool "Enable paravirtualization code" | |
593 | help | |
594 | This changes the kernel so it can modify itself when it is run | |
595 | under a hypervisor, potentially improving performance significantly | |
596 | over full virtualization. | |
597 | ||
598 | config PARAVIRT_TIME_ACCOUNTING | |
599 | bool "Paravirtual steal time accounting" | |
600 | select PARAVIRT | |
601 | default n | |
602 | help | |
603 | Select this option to enable fine granularity task steal time | |
604 | accounting. Time spent executing other tasks in parallel with | |
605 | the current vCPU is discounted from the vCPU power. To account for | |
606 | that, there can be a small performance impact. | |
607 | ||
608 | If in doubt, say N here. | |
609 | ||
aa42aa13 SS |
610 | config XEN_DOM0 |
611 | def_bool y | |
612 | depends on XEN | |
613 | ||
614 | config XEN | |
c2ba1f7d | 615 | bool "Xen guest support on ARM64" |
aa42aa13 | 616 | depends on ARM64 && OF |
83862ccf | 617 | select SWIOTLB_XEN |
dfd57bc3 | 618 | select PARAVIRT |
aa42aa13 SS |
619 | help |
620 | Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. | |
621 | ||
d03bb145 SC |
622 | config FORCE_MAX_ZONEORDER |
623 | int | |
624 | default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) | |
44eaacf1 | 625 | default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) |
d03bb145 | 626 | default "11" |
44eaacf1 SP |
627 | help |
628 | The kernel memory allocator divides physically contiguous memory | |
629 | blocks into "zones", where each zone is a power of two number of | |
630 | pages. This option selects the largest power of two that the kernel | |
631 | keeps in the memory allocator. If you need to allocate very large | |
632 | blocks of physically contiguous memory, then you may need to | |
633 | increase this value. | |
634 | ||
635 | This config option is actually maximum order plus one. For example, | |
636 | a value of 11 means that the largest free memory block is 2^10 pages. | |
637 | ||
638 | We make sure that we can allocate upto a HugePage size for each configuration. | |
639 | Hence we have : | |
640 | MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 | |
641 | ||
642 | However for 4K, we choose a higher default value, 11 as opposed to 10, giving us | |
643 | 4M allocations matching the default size used by generic code. | |
d03bb145 | 644 | |
1b907f46 WD |
645 | menuconfig ARMV8_DEPRECATED |
646 | bool "Emulate deprecated/obsolete ARMv8 instructions" | |
647 | depends on COMPAT | |
648 | help | |
649 | Legacy software support may require certain instructions | |
650 | that have been deprecated or obsoleted in the architecture. | |
651 | ||
652 | Enable this config to enable selective emulation of these | |
653 | features. | |
654 | ||
655 | If unsure, say Y | |
656 | ||
657 | if ARMV8_DEPRECATED | |
658 | ||
659 | config SWP_EMULATION | |
660 | bool "Emulate SWP/SWPB instructions" | |
661 | help | |
662 | ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that | |
663 | they are always undefined. Say Y here to enable software | |
664 | emulation of these instructions for userspace using LDXR/STXR. | |
665 | ||
666 | In some older versions of glibc [<=2.8] SWP is used during futex | |
667 | trylock() operations with the assumption that the code will not | |
668 | be preempted. This invalid assumption may be more likely to fail | |
669 | with SWP emulation enabled, leading to deadlock of the user | |
670 | application. | |
671 | ||
672 | NOTE: when accessing uncached shared regions, LDXR/STXR rely | |
673 | on an external transaction monitoring block called a global | |
674 | monitor to maintain update atomicity. If your system does not | |
675 | implement a global monitor, this option can cause programs that | |
676 | perform SWP operations to uncached memory to deadlock. | |
677 | ||
678 | If unsure, say Y | |
679 | ||
680 | config CP15_BARRIER_EMULATION | |
681 | bool "Emulate CP15 Barrier instructions" | |
682 | help | |
683 | The CP15 barrier instructions - CP15ISB, CP15DSB, and | |
684 | CP15DMB - are deprecated in ARMv8 (and ARMv7). It is | |
685 | strongly recommended to use the ISB, DSB, and DMB | |
686 | instructions instead. | |
687 | ||
688 | Say Y here to enable software emulation of these | |
689 | instructions for AArch32 userspace code. When this option is | |
690 | enabled, CP15 barrier usage is traced which can help | |
691 | identify software that needs updating. | |
692 | ||
693 | If unsure, say Y | |
694 | ||
2d888f48 SP |
695 | config SETEND_EMULATION |
696 | bool "Emulate SETEND instruction" | |
697 | help | |
698 | The SETEND instruction alters the data-endianness of the | |
699 | AArch32 EL0, and is deprecated in ARMv8. | |
700 | ||
701 | Say Y here to enable software emulation of the instruction | |
702 | for AArch32 userspace code. | |
703 | ||
704 | Note: All the cpus on the system must have mixed endian support at EL0 | |
705 | for this feature to be enabled. If a new CPU - which doesn't support mixed | |
706 | endian - is hotplugged in after this feature has been enabled, there could | |
707 | be unexpected results in the applications. | |
708 | ||
709 | If unsure, say Y | |
1b907f46 WD |
710 | endif |
711 | ||
0e4a0709 WD |
712 | menu "ARMv8.1 architectural features" |
713 | ||
714 | config ARM64_HW_AFDBM | |
715 | bool "Support for hardware updates of the Access and Dirty page flags" | |
716 | default y | |
717 | help | |
718 | The ARMv8.1 architecture extensions introduce support for | |
719 | hardware updates of the access and dirty information in page | |
720 | table entries. When enabled in TCR_EL1 (HA and HD bits) on | |
721 | capable processors, accesses to pages with PTE_AF cleared will | |
722 | set this bit instead of raising an access flag fault. | |
723 | Similarly, writes to read-only pages with the DBM bit set will | |
724 | clear the read-only bit (AP[2]) instead of raising a | |
725 | permission fault. | |
726 | ||
727 | Kernels built with this configuration option enabled continue | |
728 | to work on pre-ARMv8.1 hardware and the performance impact is | |
729 | minimal. If unsure, say Y. | |
730 | ||
731 | config ARM64_PAN | |
732 | bool "Enable support for Privileged Access Never (PAN)" | |
733 | default y | |
734 | help | |
735 | Privileged Access Never (PAN; part of the ARMv8.1 Extensions) | |
736 | prevents the kernel or hypervisor from accessing user-space (EL0) | |
737 | memory directly. | |
738 | ||
739 | Choosing this option will cause any unprotected (not using | |
740 | copy_to_user et al) memory access to fail with a permission fault. | |
741 | ||
742 | The feature is detected at runtime, and will remain as a 'nop' | |
743 | instruction if the cpu does not implement the feature. | |
744 | ||
745 | config ARM64_LSE_ATOMICS | |
746 | bool "Atomic instructions" | |
747 | help | |
748 | As part of the Large System Extensions, ARMv8.1 introduces new | |
749 | atomic instructions that are designed specifically to scale in | |
750 | very large systems. | |
751 | ||
752 | Say Y here to make use of these instructions for the in-kernel | |
753 | atomic routines. This incurs a small overhead on CPUs that do | |
754 | not support these instructions and requires the kernel to be | |
755 | built with binutils >= 2.25. | |
756 | ||
757 | endmenu | |
758 | ||
57f4959b JM |
759 | config ARM64_UAO |
760 | bool "Enable support for User Access Override (UAO)" | |
761 | default y | |
762 | help | |
763 | User Access Override (UAO; part of the ARMv8.2 Extensions) | |
764 | causes the 'unprivileged' variant of the load/store instructions to | |
765 | be overriden to be privileged. | |
766 | ||
767 | This option changes get_user() and friends to use the 'unprivileged' | |
768 | variant of the load/store instructions. This ensures that user-space | |
769 | really did have access to the supplied memory. When addr_limit is | |
770 | set to kernel memory the UAO bit will be set, allowing privileged | |
771 | access to kernel memory. | |
772 | ||
773 | Choosing this option will cause copy_to_user() et al to use user-space | |
774 | memory permissions. | |
775 | ||
776 | The feature is detected at runtime, the kernel will use the | |
777 | regular load/store instructions if the cpu does not implement the | |
778 | feature. | |
779 | ||
8c2c3df3 CM |
780 | endmenu |
781 | ||
782 | menu "Boot options" | |
783 | ||
5e89c55e LP |
784 | config ARM64_ACPI_PARKING_PROTOCOL |
785 | bool "Enable support for the ARM64 ACPI parking protocol" | |
786 | depends on ACPI | |
787 | help | |
788 | Enable support for the ARM64 ACPI parking protocol. If disabled | |
789 | the kernel will not allow booting through the ARM64 ACPI parking | |
790 | protocol even if the corresponding data is present in the ACPI | |
791 | MADT table. | |
792 | ||
8c2c3df3 CM |
793 | config CMDLINE |
794 | string "Default kernel command string" | |
795 | default "" | |
796 | help | |
797 | Provide a set of default command-line options at build time by | |
798 | entering them here. As a minimum, you should specify the the | |
799 | root device (e.g. root=/dev/nfs). | |
800 | ||
801 | config CMDLINE_FORCE | |
802 | bool "Always use the default kernel command string" | |
803 | help | |
804 | Always use the default kernel command string, even if the boot | |
805 | loader passes other arguments to the kernel. | |
806 | This is useful if you cannot or don't want to change the | |
807 | command-line options your boot loader passes to the kernel. | |
808 | ||
f4f75ad5 AB |
809 | config EFI_STUB |
810 | bool | |
811 | ||
f84d0275 MS |
812 | config EFI |
813 | bool "UEFI runtime support" | |
814 | depends on OF && !CPU_BIG_ENDIAN | |
815 | select LIBFDT | |
816 | select UCS2_STRING | |
817 | select EFI_PARAMS_FROM_FDT | |
e15dd494 | 818 | select EFI_RUNTIME_WRAPPERS |
f4f75ad5 AB |
819 | select EFI_STUB |
820 | select EFI_ARMSTUB | |
f84d0275 MS |
821 | default y |
822 | help | |
823 | This option provides support for runtime services provided | |
824 | by UEFI firmware (such as non-volatile variables, realtime | |
3c7f2550 MS |
825 | clock, and platform reset). A UEFI stub is also provided to |
826 | allow the kernel to be booted as an EFI application. This | |
827 | is only useful on systems that have UEFI firmware. | |
f84d0275 | 828 | |
d1ae8c00 YL |
829 | config DMI |
830 | bool "Enable support for SMBIOS (DMI) tables" | |
831 | depends on EFI | |
832 | default y | |
833 | help | |
834 | This enables SMBIOS/DMI feature for systems. | |
835 | ||
836 | This option is only useful on systems that have UEFI firmware. | |
837 | However, even with this option, the resultant kernel should | |
838 | continue to boot on existing non-UEFI platforms. | |
839 | ||
8c2c3df3 CM |
840 | endmenu |
841 | ||
842 | menu "Userspace binary formats" | |
843 | ||
844 | source "fs/Kconfig.binfmt" | |
845 | ||
846 | config COMPAT | |
847 | bool "Kernel support for 32-bit EL0" | |
755e70b7 | 848 | depends on ARM64_4K_PAGES || EXPERT |
8c2c3df3 | 849 | select COMPAT_BINFMT_ELF |
af1839eb | 850 | select HAVE_UID16 |
84b9e9b4 | 851 | select OLD_SIGSUSPEND3 |
51682036 | 852 | select COMPAT_OLD_SIGACTION |
8c2c3df3 CM |
853 | help |
854 | This option enables support for a 32-bit EL0 running under a 64-bit | |
855 | kernel at EL1. AArch32-specific components such as system calls, | |
856 | the user helper functions, VFP support and the ptrace interface are | |
857 | handled appropriately by the kernel. | |
858 | ||
44eaacf1 SP |
859 | If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware |
860 | that you will only be able to execute AArch32 binaries that were compiled | |
861 | with page size aligned segments. | |
a8fcd8b1 | 862 | |
8c2c3df3 CM |
863 | If you want to execute 32-bit userspace applications, say Y. |
864 | ||
865 | config SYSVIPC_COMPAT | |
866 | def_bool y | |
867 | depends on COMPAT && SYSVIPC | |
868 | ||
869 | endmenu | |
870 | ||
166936ba LP |
871 | menu "Power management options" |
872 | ||
873 | source "kernel/power/Kconfig" | |
874 | ||
875 | config ARCH_SUSPEND_POSSIBLE | |
876 | def_bool y | |
877 | ||
166936ba LP |
878 | endmenu |
879 | ||
1307220d LP |
880 | menu "CPU Power Management" |
881 | ||
882 | source "drivers/cpuidle/Kconfig" | |
883 | ||
52e7e816 RH |
884 | source "drivers/cpufreq/Kconfig" |
885 | ||
886 | endmenu | |
887 | ||
8c2c3df3 CM |
888 | source "net/Kconfig" |
889 | ||
890 | source "drivers/Kconfig" | |
891 | ||
f84d0275 MS |
892 | source "drivers/firmware/Kconfig" |
893 | ||
b6a02173 GG |
894 | source "drivers/acpi/Kconfig" |
895 | ||
8c2c3df3 CM |
896 | source "fs/Kconfig" |
897 | ||
c3eb5b14 MZ |
898 | source "arch/arm64/kvm/Kconfig" |
899 | ||
8c2c3df3 CM |
900 | source "arch/arm64/Kconfig.debug" |
901 | ||
902 | source "security/Kconfig" | |
903 | ||
904 | source "crypto/Kconfig" | |
2c98833a AB |
905 | if CRYPTO |
906 | source "arch/arm64/crypto/Kconfig" | |
907 | endif | |
8c2c3df3 CM |
908 | |
909 | source "lib/Kconfig" |