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1 | /* arch/arm/plat-s5pc1xx/irq.c |
2 | * | |
3 | * Copyright 2009 Samsung Electronics Co. | |
4 | * Byungho Min <bhmin@samsung.com> | |
5 | * | |
6 | * S5PC1XX - Interrupt handling | |
7 | * | |
8 | * Based on plat-s3c64xx/irq.c | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/io.h> | |
19 | ||
20 | #include <asm/hardware/vic.h> | |
21 | ||
22 | #include <mach/map.h> | |
47101ec7 | 23 | #include <plat/irq-vic-timer.h> |
be97162d | 24 | #include <plat/irq-uart.h> |
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25 | #include <plat/cpu.h> |
26 | ||
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27 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] |
28 | * are consecutive when looking up the interrupt in the demux routines. | |
29 | */ | |
be97162d | 30 | static struct s3c_uart_irq uart_irqs[] = { |
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31 | [0] = { |
32 | .regs = (void *)S3C_VA_UART0, | |
33 | .base_irq = IRQ_S3CUART_BASE0, | |
34 | .parent_irq = IRQ_UART0, | |
35 | }, | |
36 | [1] = { | |
37 | .regs = (void *)S3C_VA_UART1, | |
38 | .base_irq = IRQ_S3CUART_BASE1, | |
39 | .parent_irq = IRQ_UART1, | |
40 | }, | |
41 | [2] = { | |
42 | .regs = (void *)S3C_VA_UART2, | |
43 | .base_irq = IRQ_S3CUART_BASE2, | |
44 | .parent_irq = IRQ_UART2, | |
45 | }, | |
46 | [3] = { | |
47 | .regs = (void *)S3C_VA_UART3, | |
48 | .base_irq = IRQ_S3CUART_BASE3, | |
49 | .parent_irq = IRQ_UART3, | |
50 | }, | |
51 | }; | |
52 | ||
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53 | void __init s5pc1xx_init_irq(u32 *vic_valid, int num) |
54 | { | |
55 | int i; | |
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56 | |
57 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | |
58 | ||
59 | /* initialise the pair of VICs */ | |
60 | for (i = 0; i < num; i++) | |
61 | vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET), | |
62 | vic_valid[i], 0); | |
63 | ||
64 | /* add the timer sub-irqs */ | |
65 | ||
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66 | s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); |
67 | s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); | |
68 | s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); | |
69 | s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); | |
70 | s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); | |
c9b870e7 | 71 | |
be97162d | 72 | s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); |
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73 | } |
74 | ||
75 |