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1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h |
2 | * | |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * http://armlinux.simtec.co.uk/ | |
7 | * | |
8 | * GPIO Bank N register and configuration definitions | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) | |
16 | #define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) | |
17 | #define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08) | |
18 | ||
19 | #define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | |
20 | #define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | |
21 | #define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | |
22 | ||
23 | #define S3C64XX_GPN0_EINT0 (0x02 << 0) | |
24 | #define S3C64XX_GPN0_KP_ROW0 (0x03 << 0) | |
25 | ||
26 | #define S3C64XX_GPN1_EINT1 (0x02 << 2) | |
27 | #define S3C64XX_GPN1_KP_ROW1 (0x03 << 2) | |
28 | ||
29 | #define S3C64XX_GPN2_EINT2 (0x02 << 4) | |
30 | #define S3C64XX_GPN2_KP_ROW2 (0x03 << 4) | |
31 | ||
32 | #define S3C64XX_GPN3_EINT3 (0x02 << 6) | |
33 | #define S3C64XX_GPN3_KP_ROW3 (0x03 << 6) | |
34 | ||
35 | #define S3C64XX_GPN4_EINT4 (0x02 << 8) | |
36 | #define S3C64XX_GPN4_KP_ROW4 (0x03 << 8) | |
37 | ||
38 | #define S3C64XX_GPN5_EINT5 (0x02 << 10) | |
39 | #define S3C64XX_GPN5_KP_ROW5 (0x03 << 10) | |
40 | ||
41 | #define S3C64XX_GPN6_EINT6 (0x02 << 12) | |
42 | #define S3C64XX_GPN6_KP_ROW6 (0x03 << 12) | |
43 | ||
44 | #define S3C64XX_GPN7_EINT7 (0x02 << 14) | |
45 | #define S3C64XX_GPN7_KP_ROW7 (0x03 << 14) | |
46 | ||
47 | #define S3C64XX_GPN8_EINT8 (0x02 << 16) | |
48 | #define S3C64XX_GPN9_EINT9 (0x02 << 18) | |
49 | #define S3C64XX_GPN10_EINT10 (0x02 << 20) | |
50 | #define S3C64XX_GPN11_EINT11 (0x02 << 22) | |
51 | #define S3C64XX_GPN12_EINT12 (0x02 << 24) | |
52 | #define S3C64XX_GPN13_EINT13 (0x02 << 26) | |
53 | #define S3C64XX_GPN14_EINT14 (0x02 << 28) | |
54 | #define S3C64XX_GPN15_EINT15 (0x02 << 30) |