Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
c7909509 | 20 | #include <linux/dma-contiguous.h> |
39af22a7 | 21 | #include <linux/highmem.h> |
c7909509 | 22 | #include <linux/memblock.h> |
99d1717d | 23 | #include <linux/slab.h> |
4ce63fcd | 24 | #include <linux/iommu.h> |
e9da6e99 | 25 | #include <linux/io.h> |
4ce63fcd | 26 | #include <linux/vmalloc.h> |
158e8bfe | 27 | #include <linux/sizes.h> |
1da177e4 | 28 | |
23759dc6 | 29 | #include <asm/memory.h> |
43377453 | 30 | #include <asm/highmem.h> |
1da177e4 | 31 | #include <asm/cacheflush.h> |
1da177e4 | 32 | #include <asm/tlbflush.h> |
99d1717d | 33 | #include <asm/mach/arch.h> |
4ce63fcd | 34 | #include <asm/dma-iommu.h> |
c7909509 MS |
35 | #include <asm/mach/map.h> |
36 | #include <asm/system_info.h> | |
37 | #include <asm/dma-contiguous.h> | |
37134cd5 | 38 | |
022ae537 RK |
39 | #include "mm.h" |
40 | ||
15237e1f MS |
41 | /* |
42 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
43 | * is either exclusively owned by the CPU (and therefore may be accessed | |
44 | * by it) or exclusively owned by the DMA device. These helper functions | |
45 | * represent the transitions between these two ownership states. | |
46 | * | |
47 | * Note, however, that on later ARMs, this notion does not work due to | |
48 | * speculative prefetches. We model our approach on the assumption that | |
49 | * the CPU does do speculative prefetches, which means we clean caches | |
50 | * before transfers and delay cache invalidation until transfer completion. | |
51 | * | |
15237e1f | 52 | */ |
51fde349 | 53 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 54 | size_t, enum dma_data_direction); |
51fde349 | 55 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
56 | size_t, enum dma_data_direction); |
57 | ||
2dc6a016 MS |
58 | /** |
59 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
60 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
61 | * @page: page that buffer resides in | |
62 | * @offset: offset into page for start of buffer | |
63 | * @size: size of buffer to map | |
64 | * @dir: DMA transfer direction | |
65 | * | |
66 | * Ensure that any data held in the cache is appropriately discarded | |
67 | * or written back. | |
68 | * | |
69 | * The device owns this memory once this call has completed. The CPU | |
70 | * can regain ownership by calling dma_unmap_page(). | |
71 | */ | |
51fde349 | 72 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
73 | unsigned long offset, size_t size, enum dma_data_direction dir, |
74 | struct dma_attrs *attrs) | |
75 | { | |
97ef952a | 76 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
77 | __dma_page_cpu_to_dev(page, offset, size, dir); |
78 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
79 | } |
80 | ||
81 | /** | |
82 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
83 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
84 | * @handle: DMA address of buffer | |
85 | * @size: size of buffer (same as passed to dma_map_page) | |
86 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
87 | * | |
88 | * Unmap a page streaming mode DMA translation. The handle and size | |
89 | * must match what was provided in the previous dma_map_page() call. | |
90 | * All other usages are undefined. | |
91 | * | |
92 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
93 | * whatever the device wrote there. | |
94 | */ | |
51fde349 | 95 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
96 | size_t size, enum dma_data_direction dir, |
97 | struct dma_attrs *attrs) | |
98 | { | |
97ef952a | 99 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
100 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
101 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
102 | } |
103 | ||
51fde349 | 104 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
105 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
106 | { | |
107 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
108 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
109 | if (!arch_is_coherent()) |
110 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
51fde349 | 113 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
114 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
115 | { | |
116 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
117 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
118 | if (!arch_is_coherent()) |
119 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2dc6a016 MS |
120 | } |
121 | ||
122 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
123 | ||
124 | struct dma_map_ops arm_dma_ops = { | |
f99d6034 MS |
125 | .alloc = arm_dma_alloc, |
126 | .free = arm_dma_free, | |
127 | .mmap = arm_dma_mmap, | |
dc2832e1 | 128 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
129 | .map_page = arm_dma_map_page, |
130 | .unmap_page = arm_dma_unmap_page, | |
131 | .map_sg = arm_dma_map_sg, | |
132 | .unmap_sg = arm_dma_unmap_sg, | |
133 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
134 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
135 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
136 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
137 | .set_dma_mask = arm_dma_set_mask, | |
138 | }; | |
139 | EXPORT_SYMBOL(arm_dma_ops); | |
140 | ||
ab6494f0 CM |
141 | static u64 get_coherent_dma_mask(struct device *dev) |
142 | { | |
022ae537 | 143 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
144 | |
145 | if (dev) { | |
146 | mask = dev->coherent_dma_mask; | |
147 | ||
148 | /* | |
149 | * Sanity check the DMA mask - it must be non-zero, and | |
150 | * must be able to be satisfied by a DMA allocation. | |
151 | */ | |
152 | if (mask == 0) { | |
153 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
154 | return 0; | |
155 | } | |
156 | ||
022ae537 | 157 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
158 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
159 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 160 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
161 | return 0; |
162 | } | |
163 | } | |
1da177e4 | 164 | |
ab6494f0 CM |
165 | return mask; |
166 | } | |
167 | ||
c7909509 MS |
168 | static void __dma_clear_buffer(struct page *page, size_t size) |
169 | { | |
170 | void *ptr; | |
171 | /* | |
172 | * Ensure that the allocated pages are zeroed, and that any data | |
173 | * lurking in the kernel direct-mapped region is invalidated. | |
174 | */ | |
175 | ptr = page_address(page); | |
4ce63fcd MS |
176 | if (ptr) { |
177 | memset(ptr, 0, size); | |
178 | dmac_flush_range(ptr, ptr + size); | |
179 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
180 | } | |
c7909509 MS |
181 | } |
182 | ||
7a9a32a9 RK |
183 | /* |
184 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
185 | * specified gfp mask. Note that 'size' must be page aligned. | |
186 | */ | |
187 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
188 | { | |
189 | unsigned long order = get_order(size); | |
190 | struct page *page, *p, *e; | |
7a9a32a9 RK |
191 | |
192 | page = alloc_pages(gfp, order); | |
193 | if (!page) | |
194 | return NULL; | |
195 | ||
196 | /* | |
197 | * Now split the huge page and free the excess pages | |
198 | */ | |
199 | split_page(page, order); | |
200 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
201 | __free_page(p); | |
202 | ||
c7909509 | 203 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
204 | |
205 | return page; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Free a DMA buffer. 'size' must be page aligned. | |
210 | */ | |
211 | static void __dma_free_buffer(struct page *page, size_t size) | |
212 | { | |
213 | struct page *e = page + (size >> PAGE_SHIFT); | |
214 | ||
215 | while (page < e) { | |
216 | __free_page(page); | |
217 | page++; | |
218 | } | |
219 | } | |
220 | ||
ab6494f0 | 221 | #ifdef CONFIG_MMU |
e9da6e99 MS |
222 | #ifdef CONFIG_HUGETLB_PAGE |
223 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
224 | #endif | |
a5e9d38b | 225 | |
e9da6e99 MS |
226 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
227 | pgprot_t prot, struct page **ret_page); | |
99d1717d | 228 | |
e9da6e99 MS |
229 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
230 | pgprot_t prot, struct page **ret_page, | |
231 | const void *caller); | |
99d1717d | 232 | |
e9da6e99 MS |
233 | static void * |
234 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
235 | const void *caller) | |
99d1717d | 236 | { |
e9da6e99 MS |
237 | struct vm_struct *area; |
238 | unsigned long addr; | |
99d1717d | 239 | |
e9da6e99 MS |
240 | /* |
241 | * DMA allocation can be mapped to user space, so lets | |
242 | * set VM_USERMAP flags too. | |
243 | */ | |
244 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
245 | caller); | |
246 | if (!area) | |
247 | return NULL; | |
248 | addr = (unsigned long)area->addr; | |
249 | area->phys_addr = __pfn_to_phys(page_to_pfn(page)); | |
99d1717d | 250 | |
e9da6e99 MS |
251 | if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { |
252 | vunmap((void *)addr); | |
253 | return NULL; | |
254 | } | |
255 | return (void *)addr; | |
99d1717d | 256 | } |
1da177e4 | 257 | |
e9da6e99 | 258 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 259 | { |
e9da6e99 MS |
260 | unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; |
261 | struct vm_struct *area = find_vm_area(cpu_addr); | |
262 | if (!area || (area->flags & flags) != flags) { | |
263 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
264 | return; | |
99d1717d | 265 | } |
e9da6e99 MS |
266 | unmap_kernel_range((unsigned long)cpu_addr, size); |
267 | vunmap(cpu_addr); | |
88c58f3b | 268 | } |
88c58f3b | 269 | |
6e5267aa MS |
270 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
271 | ||
e9da6e99 MS |
272 | struct dma_pool { |
273 | size_t size; | |
274 | spinlock_t lock; | |
275 | unsigned long *bitmap; | |
276 | unsigned long nr_pages; | |
277 | void *vaddr; | |
278 | struct page *page; | |
c7909509 MS |
279 | }; |
280 | ||
e9da6e99 | 281 | static struct dma_pool atomic_pool = { |
6e5267aa | 282 | .size = DEFAULT_DMA_COHERENT_POOL_SIZE, |
e9da6e99 | 283 | }; |
c7909509 MS |
284 | |
285 | static int __init early_coherent_pool(char *p) | |
286 | { | |
e9da6e99 | 287 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
288 | return 0; |
289 | } | |
290 | early_param("coherent_pool", early_coherent_pool); | |
291 | ||
6e5267aa MS |
292 | void __init init_dma_coherent_pool_size(unsigned long size) |
293 | { | |
294 | /* | |
295 | * Catch any attempt to set the pool size too late. | |
296 | */ | |
297 | BUG_ON(atomic_pool.vaddr); | |
298 | ||
299 | /* | |
300 | * Set architecture specific coherent pool size only if | |
301 | * it has not been changed by kernel command line parameter. | |
302 | */ | |
303 | if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
304 | atomic_pool.size = size; | |
305 | } | |
306 | ||
c7909509 MS |
307 | /* |
308 | * Initialise the coherent pool for atomic allocations. | |
309 | */ | |
e9da6e99 | 310 | static int __init atomic_pool_init(void) |
c7909509 | 311 | { |
e9da6e99 | 312 | struct dma_pool *pool = &atomic_pool; |
c7909509 | 313 | pgprot_t prot = pgprot_dmacoherent(pgprot_kernel); |
e9da6e99 MS |
314 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
315 | unsigned long *bitmap; | |
c7909509 MS |
316 | struct page *page; |
317 | void *ptr; | |
e9da6e99 | 318 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 319 | |
e9da6e99 MS |
320 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
321 | if (!bitmap) | |
322 | goto no_bitmap; | |
c7909509 | 323 | |
e9da6e99 MS |
324 | if (IS_ENABLED(CONFIG_CMA)) |
325 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page); | |
326 | else | |
327 | ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot, | |
328 | &page, NULL); | |
c7909509 | 329 | if (ptr) { |
e9da6e99 MS |
330 | spin_lock_init(&pool->lock); |
331 | pool->vaddr = ptr; | |
332 | pool->page = page; | |
333 | pool->bitmap = bitmap; | |
334 | pool->nr_pages = nr_pages; | |
335 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
336 | (unsigned)pool->size / 1024); | |
c7909509 MS |
337 | return 0; |
338 | } | |
e9da6e99 MS |
339 | kfree(bitmap); |
340 | no_bitmap: | |
341 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
342 | (unsigned)pool->size / 1024); | |
c7909509 MS |
343 | return -ENOMEM; |
344 | } | |
345 | /* | |
346 | * CMA is activated by core_initcall, so we must be called after it. | |
347 | */ | |
e9da6e99 | 348 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
349 | |
350 | struct dma_contig_early_reserve { | |
351 | phys_addr_t base; | |
352 | unsigned long size; | |
353 | }; | |
354 | ||
355 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
356 | ||
357 | static int dma_mmu_remap_num __initdata; | |
358 | ||
359 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
360 | { | |
361 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
362 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
363 | dma_mmu_remap_num++; | |
364 | } | |
365 | ||
366 | void __init dma_contiguous_remap(void) | |
367 | { | |
368 | int i; | |
369 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
370 | phys_addr_t start = dma_mmu_remap[i].base; | |
371 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
372 | struct map_desc map; | |
373 | unsigned long addr; | |
374 | ||
375 | if (end > arm_lowmem_limit) | |
376 | end = arm_lowmem_limit; | |
377 | if (start >= end) | |
39f78e70 | 378 | continue; |
c7909509 MS |
379 | |
380 | map.pfn = __phys_to_pfn(start); | |
381 | map.virtual = __phys_to_virt(start); | |
382 | map.length = end - start; | |
383 | map.type = MT_MEMORY_DMA_READY; | |
384 | ||
385 | /* | |
386 | * Clear previous low-memory mapping | |
387 | */ | |
388 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 389 | addr += PMD_SIZE) |
c7909509 MS |
390 | pmd_clear(pmd_off_k(addr)); |
391 | ||
392 | iotable_init(&map, 1); | |
393 | } | |
394 | } | |
395 | ||
c7909509 MS |
396 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
397 | void *data) | |
398 | { | |
399 | struct page *page = virt_to_page(addr); | |
400 | pgprot_t prot = *(pgprot_t *)data; | |
401 | ||
402 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
407 | { | |
408 | unsigned long start = (unsigned long) page_address(page); | |
409 | unsigned end = start + size; | |
410 | ||
411 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
412 | dsb(); | |
413 | flush_tlb_kernel_range(start, end); | |
414 | } | |
415 | ||
416 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
417 | pgprot_t prot, struct page **ret_page, | |
418 | const void *caller) | |
419 | { | |
420 | struct page *page; | |
421 | void *ptr; | |
422 | page = __dma_alloc_buffer(dev, size, gfp); | |
423 | if (!page) | |
424 | return NULL; | |
425 | ||
426 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
427 | if (!ptr) { | |
428 | __dma_free_buffer(page, size); | |
429 | return NULL; | |
430 | } | |
431 | ||
432 | *ret_page = page; | |
433 | return ptr; | |
434 | } | |
435 | ||
e9da6e99 | 436 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 437 | { |
e9da6e99 MS |
438 | struct dma_pool *pool = &atomic_pool; |
439 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
440 | unsigned int pageno; | |
441 | unsigned long flags; | |
442 | void *ptr = NULL; | |
e4ea6918 | 443 | unsigned long align_mask; |
c7909509 | 444 | |
e9da6e99 MS |
445 | if (!pool->vaddr) { |
446 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
447 | return NULL; |
448 | } | |
449 | ||
450 | /* | |
451 | * Align the region allocation - allocations from pool are rather | |
452 | * small, so align them to their order in pages, minimum is a page | |
453 | * size. This helps reduce fragmentation of the DMA space. | |
454 | */ | |
e4ea6918 | 455 | align_mask = (1 << get_order(size)) - 1; |
e9da6e99 MS |
456 | |
457 | spin_lock_irqsave(&pool->lock, flags); | |
458 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
e4ea6918 | 459 | 0, count, align_mask); |
e9da6e99 MS |
460 | if (pageno < pool->nr_pages) { |
461 | bitmap_set(pool->bitmap, pageno, count); | |
462 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
463 | *ret_page = pool->page + pageno; | |
fb71285f MS |
464 | } else { |
465 | pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" | |
466 | "Please increase it with coherent_pool= kernel parameter!\n", | |
467 | (unsigned)pool->size / 1024); | |
c7909509 | 468 | } |
e9da6e99 MS |
469 | spin_unlock_irqrestore(&pool->lock, flags); |
470 | ||
471 | return ptr; | |
c7909509 MS |
472 | } |
473 | ||
e9da6e99 | 474 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 475 | { |
e9da6e99 MS |
476 | struct dma_pool *pool = &atomic_pool; |
477 | unsigned long pageno, count; | |
478 | unsigned long flags; | |
c7909509 | 479 | |
e9da6e99 | 480 | if (start < pool->vaddr || start > pool->vaddr + pool->size) |
c7909509 MS |
481 | return 0; |
482 | ||
e9da6e99 MS |
483 | if (start + size > pool->vaddr + pool->size) { |
484 | WARN(1, "freeing wrong coherent size from pool\n"); | |
485 | return 0; | |
c7909509 MS |
486 | } |
487 | ||
e9da6e99 MS |
488 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
489 | count = size >> PAGE_SHIFT; | |
490 | ||
491 | spin_lock_irqsave(&pool->lock, flags); | |
492 | bitmap_clear(pool->bitmap, pageno, count); | |
493 | spin_unlock_irqrestore(&pool->lock, flags); | |
494 | ||
c7909509 MS |
495 | return 1; |
496 | } | |
497 | ||
498 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
499 | pgprot_t prot, struct page **ret_page) | |
500 | { | |
501 | unsigned long order = get_order(size); | |
502 | size_t count = size >> PAGE_SHIFT; | |
503 | struct page *page; | |
504 | ||
505 | page = dma_alloc_from_contiguous(dev, count, order); | |
506 | if (!page) | |
507 | return NULL; | |
508 | ||
509 | __dma_clear_buffer(page, size); | |
510 | __dma_remap(page, size, prot); | |
511 | ||
512 | *ret_page = page; | |
513 | return page_address(page); | |
514 | } | |
515 | ||
516 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
517 | size_t size) | |
518 | { | |
519 | __dma_remap(page, size, pgprot_kernel); | |
520 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
521 | } | |
522 | ||
f99d6034 MS |
523 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
524 | { | |
525 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
526 | pgprot_writecombine(prot) : | |
527 | pgprot_dmacoherent(prot); | |
528 | return prot; | |
529 | } | |
530 | ||
c7909509 MS |
531 | #define nommu() 0 |
532 | ||
ab6494f0 | 533 | #else /* !CONFIG_MMU */ |
695ae0af | 534 | |
c7909509 MS |
535 | #define nommu() 1 |
536 | ||
f99d6034 | 537 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 538 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 539 | #define __alloc_from_pool(size, ret_page) NULL |
c7909509 MS |
540 | #define __alloc_from_contiguous(dev, size, prot, ret) NULL |
541 | #define __free_from_pool(cpu_addr, size) 0 | |
542 | #define __free_from_contiguous(dev, page, size) do { } while (0) | |
543 | #define __dma_free_remap(cpu_addr, size) do { } while (0) | |
31ebf944 RK |
544 | |
545 | #endif /* CONFIG_MMU */ | |
546 | ||
c7909509 MS |
547 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
548 | struct page **ret_page) | |
ab6494f0 | 549 | { |
c7909509 MS |
550 | struct page *page; |
551 | page = __dma_alloc_buffer(dev, size, gfp); | |
552 | if (!page) | |
553 | return NULL; | |
554 | ||
555 | *ret_page = page; | |
556 | return page_address(page); | |
557 | } | |
558 | ||
559 | ||
560 | ||
561 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
562 | gfp_t gfp, pgprot_t prot, const void *caller) | |
563 | { | |
564 | u64 mask = get_coherent_dma_mask(dev); | |
04da5694 | 565 | struct page *page; |
31ebf944 | 566 | void *addr; |
ab6494f0 | 567 | |
c7909509 MS |
568 | #ifdef CONFIG_DMA_API_DEBUG |
569 | u64 limit = (mask + 1) & ~mask; | |
570 | if (limit && size >= limit) { | |
571 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
572 | size, mask); | |
573 | return NULL; | |
574 | } | |
575 | #endif | |
576 | ||
577 | if (!mask) | |
578 | return NULL; | |
579 | ||
580 | if (mask < 0xffffffffULL) | |
581 | gfp |= GFP_DMA; | |
582 | ||
ea2e7057 SB |
583 | /* |
584 | * Following is a work-around (a.k.a. hack) to prevent pages | |
585 | * with __GFP_COMP being passed to split_page() which cannot | |
586 | * handle them. The real problem is that this flag probably | |
587 | * should be 0 on ARM as it is not supported on this | |
588 | * platform; see CONFIG_HUGETLBFS. | |
589 | */ | |
590 | gfp &= ~(__GFP_COMP); | |
591 | ||
553ac788 | 592 | *handle = DMA_ERROR_CODE; |
04da5694 | 593 | size = PAGE_ALIGN(size); |
ab6494f0 | 594 | |
c7909509 MS |
595 | if (arch_is_coherent() || nommu()) |
596 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
e9da6e99 MS |
597 | else if (gfp & GFP_ATOMIC) |
598 | addr = __alloc_from_pool(size, &page); | |
f1ae98da | 599 | else if (!IS_ENABLED(CONFIG_CMA)) |
c7909509 | 600 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 601 | else |
c7909509 | 602 | addr = __alloc_from_contiguous(dev, size, prot, &page); |
695ae0af | 603 | |
31ebf944 | 604 | if (addr) |
9eedd963 | 605 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 606 | |
31ebf944 RK |
607 | return addr; |
608 | } | |
1da177e4 LT |
609 | |
610 | /* | |
611 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
612 | * virtual and bus address for that space. | |
613 | */ | |
f99d6034 MS |
614 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
615 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 616 | { |
f99d6034 | 617 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); |
1fe53268 DB |
618 | void *memory; |
619 | ||
620 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
621 | return memory; | |
622 | ||
f99d6034 | 623 | return __dma_alloc(dev, size, handle, gfp, prot, |
45cd5290 | 624 | __builtin_return_address(0)); |
1da177e4 | 625 | } |
1da177e4 LT |
626 | |
627 | /* | |
f99d6034 | 628 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 629 | */ |
f99d6034 MS |
630 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
631 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
632 | struct dma_attrs *attrs) | |
1da177e4 | 633 | { |
ab6494f0 CM |
634 | int ret = -ENXIO; |
635 | #ifdef CONFIG_MMU | |
50262a4b MS |
636 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
637 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 638 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
639 | unsigned long off = vma->vm_pgoff; |
640 | ||
f99d6034 MS |
641 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
642 | ||
47142f07 MS |
643 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
644 | return ret; | |
645 | ||
50262a4b MS |
646 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
647 | ret = remap_pfn_range(vma, vma->vm_start, | |
648 | pfn + off, | |
649 | vma->vm_end - vma->vm_start, | |
650 | vma->vm_page_prot); | |
651 | } | |
ab6494f0 | 652 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
653 | |
654 | return ret; | |
655 | } | |
656 | ||
1da177e4 | 657 | /* |
c7909509 | 658 | * Free a buffer as defined by the above mapping. |
1da177e4 | 659 | */ |
f99d6034 MS |
660 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
661 | dma_addr_t handle, struct dma_attrs *attrs) | |
1da177e4 | 662 | { |
c7909509 | 663 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 664 | |
1fe53268 DB |
665 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
666 | return; | |
667 | ||
3e82d012 RK |
668 | size = PAGE_ALIGN(size); |
669 | ||
c7909509 MS |
670 | if (arch_is_coherent() || nommu()) { |
671 | __dma_free_buffer(page, size); | |
d9e0d149 AK |
672 | } else if (__free_from_pool(cpu_addr, size)) { |
673 | return; | |
f1ae98da | 674 | } else if (!IS_ENABLED(CONFIG_CMA)) { |
695ae0af | 675 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
676 | __dma_free_buffer(page, size); |
677 | } else { | |
c7909509 MS |
678 | /* |
679 | * Non-atomic allocations cannot be freed with IRQs disabled | |
680 | */ | |
681 | WARN_ON(irqs_disabled()); | |
682 | __free_from_contiguous(dev, page, size); | |
683 | } | |
1da177e4 | 684 | } |
afd1a321 | 685 | |
dc2832e1 MS |
686 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
687 | void *cpu_addr, dma_addr_t handle, size_t size, | |
688 | struct dma_attrs *attrs) | |
689 | { | |
690 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
691 | int ret; | |
692 | ||
693 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
694 | if (unlikely(ret)) | |
695 | return ret; | |
696 | ||
697 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
698 | return 0; | |
699 | } | |
700 | ||
4ea0d737 | 701 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
702 | size_t size, enum dma_data_direction dir, |
703 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
704 | { |
705 | /* | |
706 | * A single sg entry may refer to multiple physically contiguous | |
707 | * pages. But we still need to process highmem pages individually. | |
708 | * If highmem is not configured then the bulk of this loop gets | |
709 | * optimized out. | |
710 | */ | |
711 | size_t left = size; | |
712 | do { | |
713 | size_t len = left; | |
93f1d629 RK |
714 | void *vaddr; |
715 | ||
716 | if (PageHighMem(page)) { | |
717 | if (len + offset > PAGE_SIZE) { | |
718 | if (offset >= PAGE_SIZE) { | |
719 | page += offset / PAGE_SIZE; | |
720 | offset %= PAGE_SIZE; | |
721 | } | |
722 | len = PAGE_SIZE - offset; | |
723 | } | |
724 | vaddr = kmap_high_get(page); | |
725 | if (vaddr) { | |
726 | vaddr += offset; | |
a9c9147e | 727 | op(vaddr, len, dir); |
93f1d629 | 728 | kunmap_high(page); |
7e5a69e8 | 729 | } else if (cache_is_vipt()) { |
39af22a7 NP |
730 | /* unmapped pages might still be cached */ |
731 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 732 | op(vaddr + offset, len, dir); |
39af22a7 | 733 | kunmap_atomic(vaddr); |
43377453 | 734 | } |
93f1d629 RK |
735 | } else { |
736 | vaddr = page_address(page) + offset; | |
a9c9147e | 737 | op(vaddr, len, dir); |
43377453 | 738 | } |
43377453 NP |
739 | offset = 0; |
740 | page++; | |
741 | left -= len; | |
742 | } while (left); | |
743 | } | |
4ea0d737 | 744 | |
51fde349 MS |
745 | /* |
746 | * Make an area consistent for devices. | |
747 | * Note: Drivers should NOT use this function directly, as it will break | |
748 | * platforms with CONFIG_DMABOUNCE. | |
749 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
750 | */ | |
751 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
752 | size_t size, enum dma_data_direction dir) |
753 | { | |
65af191a | 754 | unsigned long paddr; |
65af191a | 755 | |
a9c9147e | 756 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
757 | |
758 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
759 | if (dir == DMA_FROM_DEVICE) { |
760 | outer_inv_range(paddr, paddr + size); | |
761 | } else { | |
762 | outer_clean_range(paddr, paddr + size); | |
763 | } | |
764 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 765 | } |
4ea0d737 | 766 | |
51fde349 | 767 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
768 | size_t size, enum dma_data_direction dir) |
769 | { | |
2ffe2da3 RK |
770 | unsigned long paddr = page_to_phys(page) + off; |
771 | ||
772 | /* FIXME: non-speculating: not required */ | |
773 | /* don't bother invalidating if DMA to device */ | |
774 | if (dir != DMA_TO_DEVICE) | |
775 | outer_inv_range(paddr, paddr + size); | |
776 | ||
a9c9147e | 777 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
778 | |
779 | /* | |
780 | * Mark the D-cache clean for this page to avoid extra flushing. | |
781 | */ | |
782 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
783 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 | 784 | } |
43377453 | 785 | |
afd1a321 | 786 | /** |
2a550e73 | 787 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
788 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
789 | * @sg: list of buffers | |
790 | * @nents: number of buffers to map | |
791 | * @dir: DMA transfer direction | |
792 | * | |
793 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
794 | * This is the scatter-gather version of the dma_map_single interface. | |
795 | * Here the scatter gather list elements are each tagged with the | |
796 | * appropriate dma address and length. They are obtained via | |
797 | * sg_dma_{address,length}. | |
798 | * | |
799 | * Device ownership issues as mentioned for dma_map_single are the same | |
800 | * here. | |
801 | */ | |
2dc6a016 MS |
802 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
803 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 804 | { |
2a550e73 | 805 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 806 | struct scatterlist *s; |
01135d92 | 807 | int i, j; |
afd1a321 RK |
808 | |
809 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
810 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
811 | s->dma_length = s->length; | |
812 | #endif | |
2a550e73 MS |
813 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
814 | s->length, dir, attrs); | |
01135d92 RK |
815 | if (dma_mapping_error(dev, s->dma_address)) |
816 | goto bad_mapping; | |
afd1a321 | 817 | } |
afd1a321 | 818 | return nents; |
01135d92 RK |
819 | |
820 | bad_mapping: | |
821 | for_each_sg(sg, s, i, j) | |
2a550e73 | 822 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 823 | return 0; |
afd1a321 | 824 | } |
afd1a321 RK |
825 | |
826 | /** | |
2a550e73 | 827 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
828 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
829 | * @sg: list of buffers | |
0adfca6f | 830 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
831 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
832 | * | |
833 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
834 | * rules concerning calls here are the same as for dma_unmap_single(). | |
835 | */ | |
2dc6a016 MS |
836 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
837 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 838 | { |
2a550e73 | 839 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 840 | struct scatterlist *s; |
01135d92 | 841 | |
01135d92 | 842 | int i; |
24056f52 | 843 | |
01135d92 | 844 | for_each_sg(sg, s, nents, i) |
2a550e73 | 845 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 846 | } |
afd1a321 RK |
847 | |
848 | /** | |
2a550e73 | 849 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
850 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
851 | * @sg: list of buffers | |
852 | * @nents: number of buffers to map (returned from dma_map_sg) | |
853 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
854 | */ | |
2dc6a016 | 855 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
856 | int nents, enum dma_data_direction dir) |
857 | { | |
2a550e73 | 858 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
859 | struct scatterlist *s; |
860 | int i; | |
861 | ||
2a550e73 MS |
862 | for_each_sg(sg, s, nents, i) |
863 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
864 | dir); | |
afd1a321 | 865 | } |
afd1a321 RK |
866 | |
867 | /** | |
2a550e73 | 868 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
869 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
870 | * @sg: list of buffers | |
871 | * @nents: number of buffers to map (returned from dma_map_sg) | |
872 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
873 | */ | |
2dc6a016 | 874 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
875 | int nents, enum dma_data_direction dir) |
876 | { | |
2a550e73 | 877 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
878 | struct scatterlist *s; |
879 | int i; | |
880 | ||
2a550e73 MS |
881 | for_each_sg(sg, s, nents, i) |
882 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
883 | dir); | |
afd1a321 | 884 | } |
24056f52 | 885 | |
022ae537 RK |
886 | /* |
887 | * Return whether the given device DMA address mask can be supported | |
888 | * properly. For example, if your device can only drive the low 24-bits | |
889 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
890 | * to this function. | |
891 | */ | |
892 | int dma_supported(struct device *dev, u64 mask) | |
893 | { | |
894 | if (mask < (u64)arm_dma_limit) | |
895 | return 0; | |
896 | return 1; | |
897 | } | |
898 | EXPORT_SYMBOL(dma_supported); | |
899 | ||
2dc6a016 | 900 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
901 | { |
902 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
903 | return -EIO; | |
904 | ||
022ae537 | 905 | *dev->dma_mask = dma_mask; |
022ae537 RK |
906 | |
907 | return 0; | |
908 | } | |
022ae537 | 909 | |
24056f52 RK |
910 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
911 | ||
912 | static int __init dma_debug_do_init(void) | |
913 | { | |
914 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
915 | return 0; | |
916 | } | |
917 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
918 | |
919 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
920 | ||
921 | /* IOMMU */ | |
922 | ||
923 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, | |
924 | size_t size) | |
925 | { | |
926 | unsigned int order = get_order(size); | |
927 | unsigned int align = 0; | |
928 | unsigned int count, start; | |
929 | unsigned long flags; | |
930 | ||
931 | count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) + | |
932 | (1 << mapping->order) - 1) >> mapping->order; | |
933 | ||
934 | if (order > mapping->order) | |
935 | align = (1 << (order - mapping->order)) - 1; | |
936 | ||
937 | spin_lock_irqsave(&mapping->lock, flags); | |
938 | start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0, | |
939 | count, align); | |
940 | if (start > mapping->bits) { | |
941 | spin_unlock_irqrestore(&mapping->lock, flags); | |
942 | return DMA_ERROR_CODE; | |
943 | } | |
944 | ||
945 | bitmap_set(mapping->bitmap, start, count); | |
946 | spin_unlock_irqrestore(&mapping->lock, flags); | |
947 | ||
948 | return mapping->base + (start << (mapping->order + PAGE_SHIFT)); | |
949 | } | |
950 | ||
951 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
952 | dma_addr_t addr, size_t size) | |
953 | { | |
954 | unsigned int start = (addr - mapping->base) >> | |
955 | (mapping->order + PAGE_SHIFT); | |
956 | unsigned int count = ((size >> PAGE_SHIFT) + | |
957 | (1 << mapping->order) - 1) >> mapping->order; | |
958 | unsigned long flags; | |
959 | ||
960 | spin_lock_irqsave(&mapping->lock, flags); | |
961 | bitmap_clear(mapping->bitmap, start, count); | |
962 | spin_unlock_irqrestore(&mapping->lock, flags); | |
963 | } | |
964 | ||
965 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
966 | { | |
967 | struct page **pages; | |
968 | int count = size >> PAGE_SHIFT; | |
969 | int array_size = count * sizeof(struct page *); | |
970 | int i = 0; | |
971 | ||
972 | if (array_size <= PAGE_SIZE) | |
973 | pages = kzalloc(array_size, gfp); | |
974 | else | |
975 | pages = vzalloc(array_size); | |
976 | if (!pages) | |
977 | return NULL; | |
978 | ||
979 | while (count) { | |
593f4735 | 980 | int j, order = __fls(count); |
4ce63fcd MS |
981 | |
982 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, order); | |
983 | while (!pages[i] && order) | |
984 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order); | |
985 | if (!pages[i]) | |
986 | goto error; | |
987 | ||
988 | if (order) | |
989 | split_page(pages[i], order); | |
990 | j = 1 << order; | |
991 | while (--j) | |
992 | pages[i + j] = pages[i] + j; | |
993 | ||
994 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
995 | i += 1 << order; | |
996 | count -= 1 << order; | |
997 | } | |
998 | ||
999 | return pages; | |
1000 | error: | |
9fa8af91 | 1001 | while (i--) |
4ce63fcd MS |
1002 | if (pages[i]) |
1003 | __free_pages(pages[i], 0); | |
46c87852 | 1004 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1005 | kfree(pages); |
1006 | else | |
1007 | vfree(pages); | |
1008 | return NULL; | |
1009 | } | |
1010 | ||
1011 | static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size) | |
1012 | { | |
1013 | int count = size >> PAGE_SHIFT; | |
1014 | int array_size = count * sizeof(struct page *); | |
1015 | int i; | |
1016 | for (i = 0; i < count; i++) | |
1017 | if (pages[i]) | |
1018 | __free_pages(pages[i], 0); | |
46c87852 | 1019 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1020 | kfree(pages); |
1021 | else | |
1022 | vfree(pages); | |
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * Create a CPU mapping for a specified pages | |
1028 | */ | |
1029 | static void * | |
e9da6e99 MS |
1030 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1031 | const void *caller) | |
4ce63fcd | 1032 | { |
e9da6e99 MS |
1033 | unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1034 | struct vm_struct *area; | |
1035 | unsigned long p; | |
4ce63fcd | 1036 | |
e9da6e99 MS |
1037 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, |
1038 | caller); | |
1039 | if (!area) | |
4ce63fcd | 1040 | return NULL; |
4ce63fcd | 1041 | |
e9da6e99 MS |
1042 | area->pages = pages; |
1043 | area->nr_pages = nr_pages; | |
1044 | p = (unsigned long)area->addr; | |
4ce63fcd | 1045 | |
e9da6e99 MS |
1046 | for (i = 0; i < nr_pages; i++) { |
1047 | phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i])); | |
1048 | if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot)) | |
1049 | goto err; | |
1050 | p += PAGE_SIZE; | |
4ce63fcd | 1051 | } |
e9da6e99 MS |
1052 | return area->addr; |
1053 | err: | |
1054 | unmap_kernel_range((unsigned long)area->addr, size); | |
1055 | vunmap(area->addr); | |
4ce63fcd MS |
1056 | return NULL; |
1057 | } | |
1058 | ||
1059 | /* | |
1060 | * Create a mapping in device IO address space for specified pages | |
1061 | */ | |
1062 | static dma_addr_t | |
1063 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1064 | { | |
1065 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1066 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1067 | dma_addr_t dma_addr, iova; | |
1068 | int i, ret = DMA_ERROR_CODE; | |
1069 | ||
1070 | dma_addr = __alloc_iova(mapping, size); | |
1071 | if (dma_addr == DMA_ERROR_CODE) | |
1072 | return dma_addr; | |
1073 | ||
1074 | iova = dma_addr; | |
1075 | for (i = 0; i < count; ) { | |
1076 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1077 | phys_addr_t phys = page_to_phys(pages[i]); | |
1078 | unsigned int len, j; | |
1079 | ||
1080 | for (j = i + 1; j < count; j++, next_pfn++) | |
1081 | if (page_to_pfn(pages[j]) != next_pfn) | |
1082 | break; | |
1083 | ||
1084 | len = (j - i) << PAGE_SHIFT; | |
1085 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1086 | if (ret < 0) | |
1087 | goto fail; | |
1088 | iova += len; | |
1089 | i = j; | |
1090 | } | |
1091 | return dma_addr; | |
1092 | fail: | |
1093 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1094 | __free_iova(mapping, dma_addr, size); | |
1095 | return DMA_ERROR_CODE; | |
1096 | } | |
1097 | ||
1098 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1099 | { | |
1100 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1101 | ||
1102 | /* | |
1103 | * add optional in-page offset from iova to size and align | |
1104 | * result to page size | |
1105 | */ | |
1106 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1107 | iova &= PAGE_MASK; | |
1108 | ||
1109 | iommu_unmap(mapping->domain, iova, size); | |
1110 | __free_iova(mapping, iova, size); | |
1111 | return 0; | |
1112 | } | |
1113 | ||
955c757e | 1114 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1115 | { |
1116 | struct vm_struct *area; | |
1117 | ||
955c757e MS |
1118 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1119 | return cpu_addr; | |
1120 | ||
e9da6e99 MS |
1121 | area = find_vm_area(cpu_addr); |
1122 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1123 | return area->pages; | |
1124 | return NULL; | |
1125 | } | |
1126 | ||
4ce63fcd MS |
1127 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1128 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1129 | { | |
1130 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); | |
1131 | struct page **pages; | |
1132 | void *addr = NULL; | |
1133 | ||
1134 | *handle = DMA_ERROR_CODE; | |
1135 | size = PAGE_ALIGN(size); | |
1136 | ||
1137 | pages = __iommu_alloc_buffer(dev, size, gfp); | |
1138 | if (!pages) | |
1139 | return NULL; | |
1140 | ||
1141 | *handle = __iommu_create_mapping(dev, pages, size); | |
1142 | if (*handle == DMA_ERROR_CODE) | |
1143 | goto err_buffer; | |
1144 | ||
955c757e MS |
1145 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1146 | return pages; | |
1147 | ||
e9da6e99 MS |
1148 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1149 | __builtin_return_address(0)); | |
4ce63fcd MS |
1150 | if (!addr) |
1151 | goto err_mapping; | |
1152 | ||
1153 | return addr; | |
1154 | ||
1155 | err_mapping: | |
1156 | __iommu_remove_mapping(dev, *handle, size); | |
1157 | err_buffer: | |
1158 | __iommu_free_buffer(dev, pages, size); | |
1159 | return NULL; | |
1160 | } | |
1161 | ||
1162 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1163 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1164 | struct dma_attrs *attrs) | |
1165 | { | |
e9da6e99 MS |
1166 | unsigned long uaddr = vma->vm_start; |
1167 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1168 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1169 | |
1170 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1171 | |
e9da6e99 MS |
1172 | if (!pages) |
1173 | return -ENXIO; | |
4ce63fcd | 1174 | |
e9da6e99 MS |
1175 | do { |
1176 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1177 | if (ret) { | |
1178 | pr_err("Remapping memory failed: %d\n", ret); | |
1179 | return ret; | |
1180 | } | |
1181 | uaddr += PAGE_SIZE; | |
1182 | usize -= PAGE_SIZE; | |
1183 | } while (usize > 0); | |
4ce63fcd | 1184 | |
4ce63fcd MS |
1185 | return 0; |
1186 | } | |
1187 | ||
1188 | /* | |
1189 | * free a page as defined by the above mapping. | |
1190 | * Must not be called with IRQs disabled. | |
1191 | */ | |
1192 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1193 | dma_addr_t handle, struct dma_attrs *attrs) | |
1194 | { | |
955c757e | 1195 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1196 | size = PAGE_ALIGN(size); |
1197 | ||
e9da6e99 MS |
1198 | if (!pages) { |
1199 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
1200 | return; | |
4ce63fcd | 1201 | } |
e9da6e99 | 1202 | |
955c757e MS |
1203 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
1204 | unmap_kernel_range((unsigned long)cpu_addr, size); | |
1205 | vunmap(cpu_addr); | |
1206 | } | |
e9da6e99 MS |
1207 | |
1208 | __iommu_remove_mapping(dev, handle, size); | |
1209 | __iommu_free_buffer(dev, pages, size); | |
4ce63fcd MS |
1210 | } |
1211 | ||
dc2832e1 MS |
1212 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1213 | void *cpu_addr, dma_addr_t dma_addr, | |
1214 | size_t size, struct dma_attrs *attrs) | |
1215 | { | |
1216 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1217 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1218 | ||
1219 | if (!pages) | |
1220 | return -ENXIO; | |
1221 | ||
1222 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1223 | GFP_KERNEL); | |
4ce63fcd MS |
1224 | } |
1225 | ||
1226 | /* | |
1227 | * Map a part of the scatter-gather list into contiguous io address space | |
1228 | */ | |
1229 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1230 | size_t size, dma_addr_t *handle, | |
97ef952a | 1231 | enum dma_data_direction dir, struct dma_attrs *attrs) |
4ce63fcd MS |
1232 | { |
1233 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1234 | dma_addr_t iova, iova_base; | |
1235 | int ret = 0; | |
1236 | unsigned int count; | |
1237 | struct scatterlist *s; | |
1238 | ||
1239 | size = PAGE_ALIGN(size); | |
1240 | *handle = DMA_ERROR_CODE; | |
1241 | ||
1242 | iova_base = iova = __alloc_iova(mapping, size); | |
1243 | if (iova == DMA_ERROR_CODE) | |
1244 | return -ENOMEM; | |
1245 | ||
1246 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1247 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1248 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1249 | ||
97ef952a MS |
1250 | if (!arch_is_coherent() && |
1251 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1252 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1253 | ||
1254 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1255 | if (ret < 0) | |
1256 | goto fail; | |
1257 | count += len >> PAGE_SHIFT; | |
1258 | iova += len; | |
1259 | } | |
1260 | *handle = iova_base; | |
1261 | ||
1262 | return 0; | |
1263 | fail: | |
1264 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1265 | __free_iova(mapping, iova_base, size); | |
1266 | return ret; | |
1267 | } | |
1268 | ||
1269 | /** | |
1270 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1271 | * @dev: valid struct device pointer | |
1272 | * @sg: list of buffers | |
1273 | * @nents: number of buffers to map | |
1274 | * @dir: DMA transfer direction | |
1275 | * | |
1276 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1277 | * The scatter gather list elements are merged together (if possible) and | |
1278 | * tagged with the appropriate dma address and length. They are obtained via | |
1279 | * sg_dma_{address,length}. | |
1280 | */ | |
1281 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1282 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1283 | { | |
1284 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1285 | int i, count = 0; | |
1286 | unsigned int offset = s->offset; | |
1287 | unsigned int size = s->offset + s->length; | |
1288 | unsigned int max = dma_get_max_seg_size(dev); | |
1289 | ||
1290 | for (i = 1; i < nents; i++) { | |
1291 | s = sg_next(s); | |
1292 | ||
1293 | s->dma_address = DMA_ERROR_CODE; | |
1294 | s->dma_length = 0; | |
1295 | ||
1296 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1297 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
97ef952a | 1298 | dir, attrs) < 0) |
4ce63fcd MS |
1299 | goto bad_mapping; |
1300 | ||
1301 | dma->dma_address += offset; | |
1302 | dma->dma_length = size - offset; | |
1303 | ||
1304 | size = offset = s->offset; | |
1305 | start = s; | |
1306 | dma = sg_next(dma); | |
1307 | count += 1; | |
1308 | } | |
1309 | size += s->length; | |
1310 | } | |
97ef952a | 1311 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0) |
4ce63fcd MS |
1312 | goto bad_mapping; |
1313 | ||
1314 | dma->dma_address += offset; | |
1315 | dma->dma_length = size - offset; | |
1316 | ||
1317 | return count+1; | |
1318 | ||
1319 | bad_mapping: | |
1320 | for_each_sg(sg, s, count, i) | |
1321 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1322 | return 0; | |
1323 | } | |
1324 | ||
1325 | /** | |
1326 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1327 | * @dev: valid struct device pointer | |
1328 | * @sg: list of buffers | |
1329 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1330 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1331 | * | |
1332 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1333 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1334 | */ | |
1335 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1336 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1337 | { | |
1338 | struct scatterlist *s; | |
1339 | int i; | |
1340 | ||
1341 | for_each_sg(sg, s, nents, i) { | |
1342 | if (sg_dma_len(s)) | |
1343 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1344 | sg_dma_len(s)); | |
97ef952a MS |
1345 | if (!arch_is_coherent() && |
1346 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1347 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1348 | s->length, dir); | |
1349 | } | |
1350 | } | |
1351 | ||
1352 | /** | |
1353 | * arm_iommu_sync_sg_for_cpu | |
1354 | * @dev: valid struct device pointer | |
1355 | * @sg: list of buffers | |
1356 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1357 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1358 | */ | |
1359 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1360 | int nents, enum dma_data_direction dir) | |
1361 | { | |
1362 | struct scatterlist *s; | |
1363 | int i; | |
1364 | ||
1365 | for_each_sg(sg, s, nents, i) | |
1366 | if (!arch_is_coherent()) | |
1367 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); | |
1368 | ||
1369 | } | |
1370 | ||
1371 | /** | |
1372 | * arm_iommu_sync_sg_for_device | |
1373 | * @dev: valid struct device pointer | |
1374 | * @sg: list of buffers | |
1375 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1376 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1377 | */ | |
1378 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1379 | int nents, enum dma_data_direction dir) | |
1380 | { | |
1381 | struct scatterlist *s; | |
1382 | int i; | |
1383 | ||
1384 | for_each_sg(sg, s, nents, i) | |
1385 | if (!arch_is_coherent()) | |
1386 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1387 | } | |
1388 | ||
1389 | ||
1390 | /** | |
1391 | * arm_iommu_map_page | |
1392 | * @dev: valid struct device pointer | |
1393 | * @page: page that buffer resides in | |
1394 | * @offset: offset into page for start of buffer | |
1395 | * @size: size of buffer to map | |
1396 | * @dir: DMA transfer direction | |
1397 | * | |
1398 | * IOMMU aware version of arm_dma_map_page() | |
1399 | */ | |
1400 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1401 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1402 | struct dma_attrs *attrs) | |
1403 | { | |
1404 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1405 | dma_addr_t dma_addr; | |
1406 | int ret, len = PAGE_ALIGN(size + offset); | |
1407 | ||
97ef952a | 1408 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1409 | __dma_page_cpu_to_dev(page, offset, size, dir); |
1410 | ||
1411 | dma_addr = __alloc_iova(mapping, len); | |
1412 | if (dma_addr == DMA_ERROR_CODE) | |
1413 | return dma_addr; | |
1414 | ||
1415 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0); | |
1416 | if (ret < 0) | |
1417 | goto fail; | |
1418 | ||
1419 | return dma_addr + offset; | |
1420 | fail: | |
1421 | __free_iova(mapping, dma_addr, len); | |
1422 | return DMA_ERROR_CODE; | |
1423 | } | |
1424 | ||
1425 | /** | |
1426 | * arm_iommu_unmap_page | |
1427 | * @dev: valid struct device pointer | |
1428 | * @handle: DMA address of buffer | |
1429 | * @size: size of buffer (same as passed to dma_map_page) | |
1430 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1431 | * | |
1432 | * IOMMU aware version of arm_dma_unmap_page() | |
1433 | */ | |
1434 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1435 | size_t size, enum dma_data_direction dir, | |
1436 | struct dma_attrs *attrs) | |
1437 | { | |
1438 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1439 | dma_addr_t iova = handle & PAGE_MASK; | |
1440 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1441 | int offset = handle & ~PAGE_MASK; | |
1442 | int len = PAGE_ALIGN(size + offset); | |
1443 | ||
1444 | if (!iova) | |
1445 | return; | |
1446 | ||
97ef952a | 1447 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1448 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1449 | ||
1450 | iommu_unmap(mapping->domain, iova, len); | |
1451 | __free_iova(mapping, iova, len); | |
1452 | } | |
1453 | ||
1454 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1455 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1456 | { | |
1457 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1458 | dma_addr_t iova = handle & PAGE_MASK; | |
1459 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1460 | unsigned int offset = handle & ~PAGE_MASK; | |
1461 | ||
1462 | if (!iova) | |
1463 | return; | |
1464 | ||
1465 | if (!arch_is_coherent()) | |
1466 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1467 | } | |
1468 | ||
1469 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1470 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1471 | { | |
1472 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1473 | dma_addr_t iova = handle & PAGE_MASK; | |
1474 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1475 | unsigned int offset = handle & ~PAGE_MASK; | |
1476 | ||
1477 | if (!iova) | |
1478 | return; | |
1479 | ||
1480 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1481 | } | |
1482 | ||
1483 | struct dma_map_ops iommu_ops = { | |
1484 | .alloc = arm_iommu_alloc_attrs, | |
1485 | .free = arm_iommu_free_attrs, | |
1486 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1487 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1488 | |
1489 | .map_page = arm_iommu_map_page, | |
1490 | .unmap_page = arm_iommu_unmap_page, | |
1491 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1492 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1493 | ||
1494 | .map_sg = arm_iommu_map_sg, | |
1495 | .unmap_sg = arm_iommu_unmap_sg, | |
1496 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1497 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
1498 | }; | |
1499 | ||
1500 | /** | |
1501 | * arm_iommu_create_mapping | |
1502 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1503 | * @base: start address of the valid IO address space | |
1504 | * @size: size of the valid IO address space | |
1505 | * @order: accuracy of the IO addresses allocations | |
1506 | * | |
1507 | * Creates a mapping structure which holds information about used/unused | |
1508 | * IO address ranges, which is required to perform memory allocation and | |
1509 | * mapping with IOMMU aware functions. | |
1510 | * | |
1511 | * The client device need to be attached to the mapping with | |
1512 | * arm_iommu_attach_device function. | |
1513 | */ | |
1514 | struct dma_iommu_mapping * | |
1515 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size, | |
1516 | int order) | |
1517 | { | |
1518 | unsigned int count = size >> (PAGE_SHIFT + order); | |
1519 | unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long); | |
1520 | struct dma_iommu_mapping *mapping; | |
1521 | int err = -ENOMEM; | |
1522 | ||
1523 | if (!count) | |
1524 | return ERR_PTR(-EINVAL); | |
1525 | ||
1526 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); | |
1527 | if (!mapping) | |
1528 | goto err; | |
1529 | ||
1530 | mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
1531 | if (!mapping->bitmap) | |
1532 | goto err2; | |
1533 | ||
1534 | mapping->base = base; | |
1535 | mapping->bits = BITS_PER_BYTE * bitmap_size; | |
1536 | mapping->order = order; | |
1537 | spin_lock_init(&mapping->lock); | |
1538 | ||
1539 | mapping->domain = iommu_domain_alloc(bus); | |
1540 | if (!mapping->domain) | |
1541 | goto err3; | |
1542 | ||
1543 | kref_init(&mapping->kref); | |
1544 | return mapping; | |
1545 | err3: | |
1546 | kfree(mapping->bitmap); | |
1547 | err2: | |
1548 | kfree(mapping); | |
1549 | err: | |
1550 | return ERR_PTR(err); | |
1551 | } | |
1552 | ||
1553 | static void release_iommu_mapping(struct kref *kref) | |
1554 | { | |
1555 | struct dma_iommu_mapping *mapping = | |
1556 | container_of(kref, struct dma_iommu_mapping, kref); | |
1557 | ||
1558 | iommu_domain_free(mapping->domain); | |
1559 | kfree(mapping->bitmap); | |
1560 | kfree(mapping); | |
1561 | } | |
1562 | ||
1563 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) | |
1564 | { | |
1565 | if (mapping) | |
1566 | kref_put(&mapping->kref, release_iommu_mapping); | |
1567 | } | |
1568 | ||
1569 | /** | |
1570 | * arm_iommu_attach_device | |
1571 | * @dev: valid struct device pointer | |
1572 | * @mapping: io address space mapping structure (returned from | |
1573 | * arm_iommu_create_mapping) | |
1574 | * | |
1575 | * Attaches specified io address space mapping to the provided device, | |
1576 | * this replaces the dma operations (dma_map_ops pointer) with the | |
1577 | * IOMMU aware version. More than one client might be attached to | |
1578 | * the same io address space mapping. | |
1579 | */ | |
1580 | int arm_iommu_attach_device(struct device *dev, | |
1581 | struct dma_iommu_mapping *mapping) | |
1582 | { | |
1583 | int err; | |
1584 | ||
1585 | err = iommu_attach_device(mapping->domain, dev); | |
1586 | if (err) | |
1587 | return err; | |
1588 | ||
1589 | kref_get(&mapping->kref); | |
1590 | dev->archdata.mapping = mapping; | |
1591 | set_dma_ops(dev, &iommu_ops); | |
1592 | ||
1593 | pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
1594 | return 0; | |
1595 | } | |
1596 | ||
1597 | #endif |