Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
1da177e4 LT |
16 | #include <linux/errno.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/dma-mapping.h> | |
c7909509 | 21 | #include <linux/dma-contiguous.h> |
39af22a7 | 22 | #include <linux/highmem.h> |
c7909509 | 23 | #include <linux/memblock.h> |
99d1717d | 24 | #include <linux/slab.h> |
4ce63fcd | 25 | #include <linux/iommu.h> |
e9da6e99 | 26 | #include <linux/io.h> |
4ce63fcd | 27 | #include <linux/vmalloc.h> |
158e8bfe | 28 | #include <linux/sizes.h> |
a254129e | 29 | #include <linux/cma.h> |
1da177e4 | 30 | |
23759dc6 | 31 | #include <asm/memory.h> |
43377453 | 32 | #include <asm/highmem.h> |
1da177e4 | 33 | #include <asm/cacheflush.h> |
1da177e4 | 34 | #include <asm/tlbflush.h> |
99d1717d | 35 | #include <asm/mach/arch.h> |
4ce63fcd | 36 | #include <asm/dma-iommu.h> |
c7909509 MS |
37 | #include <asm/mach/map.h> |
38 | #include <asm/system_info.h> | |
39 | #include <asm/dma-contiguous.h> | |
37134cd5 | 40 | |
022ae537 RK |
41 | #include "mm.h" |
42 | ||
15237e1f MS |
43 | /* |
44 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
45 | * is either exclusively owned by the CPU (and therefore may be accessed | |
46 | * by it) or exclusively owned by the DMA device. These helper functions | |
47 | * represent the transitions between these two ownership states. | |
48 | * | |
49 | * Note, however, that on later ARMs, this notion does not work due to | |
50 | * speculative prefetches. We model our approach on the assumption that | |
51 | * the CPU does do speculative prefetches, which means we clean caches | |
52 | * before transfers and delay cache invalidation until transfer completion. | |
53 | * | |
15237e1f | 54 | */ |
51fde349 | 55 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 56 | size_t, enum dma_data_direction); |
51fde349 | 57 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
58 | size_t, enum dma_data_direction); |
59 | ||
2dc6a016 MS |
60 | /** |
61 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
62 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
63 | * @page: page that buffer resides in | |
64 | * @offset: offset into page for start of buffer | |
65 | * @size: size of buffer to map | |
66 | * @dir: DMA transfer direction | |
67 | * | |
68 | * Ensure that any data held in the cache is appropriately discarded | |
69 | * or written back. | |
70 | * | |
71 | * The device owns this memory once this call has completed. The CPU | |
72 | * can regain ownership by calling dma_unmap_page(). | |
73 | */ | |
51fde349 | 74 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
75 | unsigned long offset, size_t size, enum dma_data_direction dir, |
76 | struct dma_attrs *attrs) | |
77 | { | |
dd37e940 | 78 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
79 | __dma_page_cpu_to_dev(page, offset, size, dir); |
80 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
81 | } |
82 | ||
dd37e940 RH |
83 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
84 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
85 | struct dma_attrs *attrs) | |
86 | { | |
87 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
88 | } | |
89 | ||
2dc6a016 MS |
90 | /** |
91 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
92 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
93 | * @handle: DMA address of buffer | |
94 | * @size: size of buffer (same as passed to dma_map_page) | |
95 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
96 | * | |
97 | * Unmap a page streaming mode DMA translation. The handle and size | |
98 | * must match what was provided in the previous dma_map_page() call. | |
99 | * All other usages are undefined. | |
100 | * | |
101 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
102 | * whatever the device wrote there. | |
103 | */ | |
51fde349 | 104 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
105 | size_t size, enum dma_data_direction dir, |
106 | struct dma_attrs *attrs) | |
107 | { | |
dd37e940 | 108 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
109 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
110 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
51fde349 | 113 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
114 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
115 | { | |
116 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
117 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 118 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
119 | } |
120 | ||
51fde349 | 121 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
122 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
123 | { | |
124 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
125 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 126 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
127 | } |
128 | ||
2dc6a016 | 129 | struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
130 | .alloc = arm_dma_alloc, |
131 | .free = arm_dma_free, | |
132 | .mmap = arm_dma_mmap, | |
dc2832e1 | 133 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
134 | .map_page = arm_dma_map_page, |
135 | .unmap_page = arm_dma_unmap_page, | |
136 | .map_sg = arm_dma_map_sg, | |
137 | .unmap_sg = arm_dma_unmap_sg, | |
138 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
139 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
140 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
141 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
142 | .set_dma_mask = arm_dma_set_mask, | |
143 | }; | |
144 | EXPORT_SYMBOL(arm_dma_ops); | |
145 | ||
dd37e940 RH |
146 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
147 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); | |
148 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
149 | dma_addr_t handle, struct dma_attrs *attrs); | |
150 | ||
151 | struct dma_map_ops arm_coherent_dma_ops = { | |
152 | .alloc = arm_coherent_dma_alloc, | |
153 | .free = arm_coherent_dma_free, | |
154 | .mmap = arm_dma_mmap, | |
155 | .get_sgtable = arm_dma_get_sgtable, | |
156 | .map_page = arm_coherent_dma_map_page, | |
157 | .map_sg = arm_dma_map_sg, | |
158 | .set_dma_mask = arm_dma_set_mask, | |
159 | }; | |
160 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
161 | ||
9f28cde0 RK |
162 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
163 | { | |
164 | unsigned long max_dma_pfn; | |
165 | ||
166 | /* | |
167 | * If the mask allows for more memory than we can address, | |
168 | * and we actually have that much memory, then we must | |
169 | * indicate that DMA to this device is not supported. | |
170 | */ | |
171 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
172 | mask > (dma_addr_t)~0 && | |
173 | dma_to_pfn(dev, ~0) < max_pfn) { | |
174 | if (warn) { | |
175 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
176 | mask); | |
177 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
178 | } | |
179 | return 0; | |
180 | } | |
181 | ||
182 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
183 | ||
184 | /* | |
185 | * Translate the device's DMA mask to a PFN limit. This | |
186 | * PFN number includes the page which we can DMA to. | |
187 | */ | |
188 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
189 | if (warn) | |
190 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
191 | mask, | |
192 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
193 | max_dma_pfn + 1); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | return 1; | |
198 | } | |
199 | ||
ab6494f0 CM |
200 | static u64 get_coherent_dma_mask(struct device *dev) |
201 | { | |
4dcfa600 | 202 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
203 | |
204 | if (dev) { | |
205 | mask = dev->coherent_dma_mask; | |
206 | ||
207 | /* | |
208 | * Sanity check the DMA mask - it must be non-zero, and | |
209 | * must be able to be satisfied by a DMA allocation. | |
210 | */ | |
211 | if (mask == 0) { | |
212 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
213 | return 0; | |
214 | } | |
215 | ||
9f28cde0 | 216 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 217 | return 0; |
ab6494f0 | 218 | } |
1da177e4 | 219 | |
ab6494f0 CM |
220 | return mask; |
221 | } | |
222 | ||
c7909509 MS |
223 | static void __dma_clear_buffer(struct page *page, size_t size) |
224 | { | |
c7909509 MS |
225 | /* |
226 | * Ensure that the allocated pages are zeroed, and that any data | |
227 | * lurking in the kernel direct-mapped region is invalidated. | |
228 | */ | |
9848e48f MS |
229 | if (PageHighMem(page)) { |
230 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
231 | phys_addr_t end = base + size; | |
232 | while (size > 0) { | |
233 | void *ptr = kmap_atomic(page); | |
234 | memset(ptr, 0, PAGE_SIZE); | |
235 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
236 | kunmap_atomic(ptr); | |
237 | page++; | |
238 | size -= PAGE_SIZE; | |
239 | } | |
240 | outer_flush_range(base, end); | |
241 | } else { | |
242 | void *ptr = page_address(page); | |
4ce63fcd MS |
243 | memset(ptr, 0, size); |
244 | dmac_flush_range(ptr, ptr + size); | |
245 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
246 | } | |
c7909509 MS |
247 | } |
248 | ||
7a9a32a9 RK |
249 | /* |
250 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
251 | * specified gfp mask. Note that 'size' must be page aligned. | |
252 | */ | |
253 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
254 | { | |
255 | unsigned long order = get_order(size); | |
256 | struct page *page, *p, *e; | |
7a9a32a9 RK |
257 | |
258 | page = alloc_pages(gfp, order); | |
259 | if (!page) | |
260 | return NULL; | |
261 | ||
262 | /* | |
263 | * Now split the huge page and free the excess pages | |
264 | */ | |
265 | split_page(page, order); | |
266 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
267 | __free_page(p); | |
268 | ||
c7909509 | 269 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
270 | |
271 | return page; | |
272 | } | |
273 | ||
274 | /* | |
275 | * Free a DMA buffer. 'size' must be page aligned. | |
276 | */ | |
277 | static void __dma_free_buffer(struct page *page, size_t size) | |
278 | { | |
279 | struct page *e = page + (size >> PAGE_SHIFT); | |
280 | ||
281 | while (page < e) { | |
282 | __free_page(page); | |
283 | page++; | |
284 | } | |
285 | } | |
286 | ||
ab6494f0 | 287 | #ifdef CONFIG_MMU |
a5e9d38b | 288 | |
e9da6e99 | 289 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f MS |
290 | pgprot_t prot, struct page **ret_page, |
291 | const void *caller); | |
99d1717d | 292 | |
e9da6e99 MS |
293 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
294 | pgprot_t prot, struct page **ret_page, | |
295 | const void *caller); | |
99d1717d | 296 | |
e9da6e99 MS |
297 | static void * |
298 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
299 | const void *caller) | |
99d1717d | 300 | { |
e9da6e99 MS |
301 | struct vm_struct *area; |
302 | unsigned long addr; | |
99d1717d | 303 | |
e9da6e99 MS |
304 | /* |
305 | * DMA allocation can be mapped to user space, so lets | |
306 | * set VM_USERMAP flags too. | |
307 | */ | |
308 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
309 | caller); | |
310 | if (!area) | |
311 | return NULL; | |
312 | addr = (unsigned long)area->addr; | |
313 | area->phys_addr = __pfn_to_phys(page_to_pfn(page)); | |
99d1717d | 314 | |
e9da6e99 MS |
315 | if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { |
316 | vunmap((void *)addr); | |
317 | return NULL; | |
318 | } | |
319 | return (void *)addr; | |
99d1717d | 320 | } |
1da177e4 | 321 | |
e9da6e99 | 322 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 323 | { |
e9da6e99 MS |
324 | unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; |
325 | struct vm_struct *area = find_vm_area(cpu_addr); | |
326 | if (!area || (area->flags & flags) != flags) { | |
327 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
328 | return; | |
99d1717d | 329 | } |
e9da6e99 MS |
330 | unmap_kernel_range((unsigned long)cpu_addr, size); |
331 | vunmap(cpu_addr); | |
88c58f3b | 332 | } |
88c58f3b | 333 | |
6e5267aa MS |
334 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
335 | ||
e9da6e99 MS |
336 | struct dma_pool { |
337 | size_t size; | |
338 | spinlock_t lock; | |
339 | unsigned long *bitmap; | |
340 | unsigned long nr_pages; | |
341 | void *vaddr; | |
6b3fe472 | 342 | struct page **pages; |
c7909509 MS |
343 | }; |
344 | ||
e9da6e99 | 345 | static struct dma_pool atomic_pool = { |
6e5267aa | 346 | .size = DEFAULT_DMA_COHERENT_POOL_SIZE, |
e9da6e99 | 347 | }; |
c7909509 MS |
348 | |
349 | static int __init early_coherent_pool(char *p) | |
350 | { | |
e9da6e99 | 351 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
352 | return 0; |
353 | } | |
354 | early_param("coherent_pool", early_coherent_pool); | |
355 | ||
6e5267aa MS |
356 | void __init init_dma_coherent_pool_size(unsigned long size) |
357 | { | |
358 | /* | |
359 | * Catch any attempt to set the pool size too late. | |
360 | */ | |
361 | BUG_ON(atomic_pool.vaddr); | |
362 | ||
363 | /* | |
364 | * Set architecture specific coherent pool size only if | |
365 | * it has not been changed by kernel command line parameter. | |
366 | */ | |
367 | if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
368 | atomic_pool.size = size; | |
369 | } | |
370 | ||
c7909509 MS |
371 | /* |
372 | * Initialise the coherent pool for atomic allocations. | |
373 | */ | |
e9da6e99 | 374 | static int __init atomic_pool_init(void) |
c7909509 | 375 | { |
e9da6e99 | 376 | struct dma_pool *pool = &atomic_pool; |
71b55663 | 377 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 378 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
e9da6e99 MS |
379 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
380 | unsigned long *bitmap; | |
c7909509 | 381 | struct page *page; |
6b3fe472 | 382 | struct page **pages; |
c7909509 | 383 | void *ptr; |
e9da6e99 | 384 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 385 | |
e9da6e99 MS |
386 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
387 | if (!bitmap) | |
388 | goto no_bitmap; | |
c7909509 | 389 | |
6b3fe472 HD |
390 | pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); |
391 | if (!pages) | |
392 | goto no_pages; | |
393 | ||
e464ef16 | 394 | if (dev_get_cma_area(NULL)) |
9848e48f MS |
395 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page, |
396 | atomic_pool_init); | |
e9da6e99 | 397 | else |
9d1400cf MS |
398 | ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page, |
399 | atomic_pool_init); | |
c7909509 | 400 | if (ptr) { |
6b3fe472 HD |
401 | int i; |
402 | ||
403 | for (i = 0; i < nr_pages; i++) | |
404 | pages[i] = page + i; | |
405 | ||
e9da6e99 MS |
406 | spin_lock_init(&pool->lock); |
407 | pool->vaddr = ptr; | |
6b3fe472 | 408 | pool->pages = pages; |
e9da6e99 MS |
409 | pool->bitmap = bitmap; |
410 | pool->nr_pages = nr_pages; | |
411 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
412 | (unsigned)pool->size / 1024); | |
c7909509 MS |
413 | return 0; |
414 | } | |
ec10665c SK |
415 | |
416 | kfree(pages); | |
6b3fe472 | 417 | no_pages: |
e9da6e99 MS |
418 | kfree(bitmap); |
419 | no_bitmap: | |
420 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
421 | (unsigned)pool->size / 1024); | |
c7909509 MS |
422 | return -ENOMEM; |
423 | } | |
424 | /* | |
425 | * CMA is activated by core_initcall, so we must be called after it. | |
426 | */ | |
e9da6e99 | 427 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
428 | |
429 | struct dma_contig_early_reserve { | |
430 | phys_addr_t base; | |
431 | unsigned long size; | |
432 | }; | |
433 | ||
434 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
435 | ||
436 | static int dma_mmu_remap_num __initdata; | |
437 | ||
438 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
439 | { | |
440 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
441 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
442 | dma_mmu_remap_num++; | |
443 | } | |
444 | ||
445 | void __init dma_contiguous_remap(void) | |
446 | { | |
447 | int i; | |
448 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
449 | phys_addr_t start = dma_mmu_remap[i].base; | |
450 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
451 | struct map_desc map; | |
452 | unsigned long addr; | |
453 | ||
454 | if (end > arm_lowmem_limit) | |
455 | end = arm_lowmem_limit; | |
456 | if (start >= end) | |
39f78e70 | 457 | continue; |
c7909509 MS |
458 | |
459 | map.pfn = __phys_to_pfn(start); | |
460 | map.virtual = __phys_to_virt(start); | |
461 | map.length = end - start; | |
462 | map.type = MT_MEMORY_DMA_READY; | |
463 | ||
464 | /* | |
6b076991 RK |
465 | * Clear previous low-memory mapping to ensure that the |
466 | * TLB does not see any conflicting entries, then flush | |
467 | * the TLB of the old entries before creating new mappings. | |
468 | * | |
469 | * This ensures that any speculatively loaded TLB entries | |
470 | * (even though they may be rare) can not cause any problems, | |
471 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
472 | */ |
473 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 474 | addr += PMD_SIZE) |
c7909509 MS |
475 | pmd_clear(pmd_off_k(addr)); |
476 | ||
6b076991 RK |
477 | flush_tlb_kernel_range(__phys_to_virt(start), |
478 | __phys_to_virt(end)); | |
479 | ||
c7909509 MS |
480 | iotable_init(&map, 1); |
481 | } | |
482 | } | |
483 | ||
c7909509 MS |
484 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
485 | void *data) | |
486 | { | |
487 | struct page *page = virt_to_page(addr); | |
488 | pgprot_t prot = *(pgprot_t *)data; | |
489 | ||
490 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
491 | return 0; | |
492 | } | |
493 | ||
494 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
495 | { | |
496 | unsigned long start = (unsigned long) page_address(page); | |
497 | unsigned end = start + size; | |
498 | ||
499 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
500 | flush_tlb_kernel_range(start, end); |
501 | } | |
502 | ||
503 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
504 | pgprot_t prot, struct page **ret_page, | |
505 | const void *caller) | |
506 | { | |
507 | struct page *page; | |
508 | void *ptr; | |
509 | page = __dma_alloc_buffer(dev, size, gfp); | |
510 | if (!page) | |
511 | return NULL; | |
512 | ||
513 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
514 | if (!ptr) { | |
515 | __dma_free_buffer(page, size); | |
516 | return NULL; | |
517 | } | |
518 | ||
519 | *ret_page = page; | |
520 | return ptr; | |
521 | } | |
522 | ||
e9da6e99 | 523 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 524 | { |
e9da6e99 MS |
525 | struct dma_pool *pool = &atomic_pool; |
526 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
527 | unsigned int pageno; | |
528 | unsigned long flags; | |
529 | void *ptr = NULL; | |
e4ea6918 | 530 | unsigned long align_mask; |
c7909509 | 531 | |
e9da6e99 MS |
532 | if (!pool->vaddr) { |
533 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
534 | return NULL; |
535 | } | |
536 | ||
537 | /* | |
538 | * Align the region allocation - allocations from pool are rather | |
539 | * small, so align them to their order in pages, minimum is a page | |
540 | * size. This helps reduce fragmentation of the DMA space. | |
541 | */ | |
e4ea6918 | 542 | align_mask = (1 << get_order(size)) - 1; |
e9da6e99 MS |
543 | |
544 | spin_lock_irqsave(&pool->lock, flags); | |
545 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
e4ea6918 | 546 | 0, count, align_mask); |
e9da6e99 MS |
547 | if (pageno < pool->nr_pages) { |
548 | bitmap_set(pool->bitmap, pageno, count); | |
549 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
6b3fe472 | 550 | *ret_page = pool->pages[pageno]; |
fb71285f MS |
551 | } else { |
552 | pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" | |
553 | "Please increase it with coherent_pool= kernel parameter!\n", | |
554 | (unsigned)pool->size / 1024); | |
c7909509 | 555 | } |
e9da6e99 MS |
556 | spin_unlock_irqrestore(&pool->lock, flags); |
557 | ||
558 | return ptr; | |
c7909509 MS |
559 | } |
560 | ||
21d0a759 HD |
561 | static bool __in_atomic_pool(void *start, size_t size) |
562 | { | |
563 | struct dma_pool *pool = &atomic_pool; | |
564 | void *end = start + size; | |
565 | void *pool_start = pool->vaddr; | |
566 | void *pool_end = pool->vaddr + pool->size; | |
567 | ||
f3d87524 | 568 | if (start < pool_start || start >= pool_end) |
21d0a759 HD |
569 | return false; |
570 | ||
571 | if (end <= pool_end) | |
572 | return true; | |
573 | ||
574 | WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n", | |
575 | start, end - 1, pool_start, pool_end - 1); | |
576 | ||
577 | return false; | |
578 | } | |
579 | ||
e9da6e99 | 580 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 581 | { |
e9da6e99 MS |
582 | struct dma_pool *pool = &atomic_pool; |
583 | unsigned long pageno, count; | |
584 | unsigned long flags; | |
c7909509 | 585 | |
21d0a759 | 586 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
587 | return 0; |
588 | ||
e9da6e99 MS |
589 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
590 | count = size >> PAGE_SHIFT; | |
591 | ||
592 | spin_lock_irqsave(&pool->lock, flags); | |
593 | bitmap_clear(pool->bitmap, pageno, count); | |
594 | spin_unlock_irqrestore(&pool->lock, flags); | |
595 | ||
c7909509 MS |
596 | return 1; |
597 | } | |
598 | ||
599 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f MS |
600 | pgprot_t prot, struct page **ret_page, |
601 | const void *caller) | |
c7909509 MS |
602 | { |
603 | unsigned long order = get_order(size); | |
604 | size_t count = size >> PAGE_SHIFT; | |
605 | struct page *page; | |
9848e48f | 606 | void *ptr; |
c7909509 MS |
607 | |
608 | page = dma_alloc_from_contiguous(dev, count, order); | |
609 | if (!page) | |
610 | return NULL; | |
611 | ||
612 | __dma_clear_buffer(page, size); | |
c7909509 | 613 | |
9848e48f MS |
614 | if (PageHighMem(page)) { |
615 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
616 | if (!ptr) { | |
617 | dma_release_from_contiguous(dev, page, count); | |
618 | return NULL; | |
619 | } | |
620 | } else { | |
621 | __dma_remap(page, size, prot); | |
622 | ptr = page_address(page); | |
623 | } | |
c7909509 | 624 | *ret_page = page; |
9848e48f | 625 | return ptr; |
c7909509 MS |
626 | } |
627 | ||
628 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
9848e48f | 629 | void *cpu_addr, size_t size) |
c7909509 | 630 | { |
9848e48f MS |
631 | if (PageHighMem(page)) |
632 | __dma_free_remap(cpu_addr, size); | |
633 | else | |
71b55663 | 634 | __dma_remap(page, size, PAGE_KERNEL); |
c7909509 MS |
635 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
636 | } | |
637 | ||
f99d6034 MS |
638 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
639 | { | |
640 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
641 | pgprot_writecombine(prot) : | |
642 | pgprot_dmacoherent(prot); | |
643 | return prot; | |
644 | } | |
645 | ||
c7909509 MS |
646 | #define nommu() 0 |
647 | ||
ab6494f0 | 648 | #else /* !CONFIG_MMU */ |
695ae0af | 649 | |
c7909509 MS |
650 | #define nommu() 1 |
651 | ||
f99d6034 | 652 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 653 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 654 | #define __alloc_from_pool(size, ret_page) NULL |
9848e48f | 655 | #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL |
c7909509 | 656 | #define __free_from_pool(cpu_addr, size) 0 |
9848e48f | 657 | #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0) |
c7909509 | 658 | #define __dma_free_remap(cpu_addr, size) do { } while (0) |
31ebf944 RK |
659 | |
660 | #endif /* CONFIG_MMU */ | |
661 | ||
c7909509 MS |
662 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
663 | struct page **ret_page) | |
ab6494f0 | 664 | { |
c7909509 MS |
665 | struct page *page; |
666 | page = __dma_alloc_buffer(dev, size, gfp); | |
667 | if (!page) | |
668 | return NULL; | |
669 | ||
670 | *ret_page = page; | |
671 | return page_address(page); | |
672 | } | |
673 | ||
674 | ||
675 | ||
676 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
dd37e940 | 677 | gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller) |
c7909509 MS |
678 | { |
679 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 680 | struct page *page = NULL; |
31ebf944 | 681 | void *addr; |
ab6494f0 | 682 | |
c7909509 MS |
683 | #ifdef CONFIG_DMA_API_DEBUG |
684 | u64 limit = (mask + 1) & ~mask; | |
685 | if (limit && size >= limit) { | |
686 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
687 | size, mask); | |
688 | return NULL; | |
689 | } | |
690 | #endif | |
691 | ||
692 | if (!mask) | |
693 | return NULL; | |
694 | ||
695 | if (mask < 0xffffffffULL) | |
696 | gfp |= GFP_DMA; | |
697 | ||
ea2e7057 SB |
698 | /* |
699 | * Following is a work-around (a.k.a. hack) to prevent pages | |
700 | * with __GFP_COMP being passed to split_page() which cannot | |
701 | * handle them. The real problem is that this flag probably | |
702 | * should be 0 on ARM as it is not supported on this | |
703 | * platform; see CONFIG_HUGETLBFS. | |
704 | */ | |
705 | gfp &= ~(__GFP_COMP); | |
706 | ||
553ac788 | 707 | *handle = DMA_ERROR_CODE; |
04da5694 | 708 | size = PAGE_ALIGN(size); |
ab6494f0 | 709 | |
dd37e940 | 710 | if (is_coherent || nommu()) |
c7909509 | 711 | addr = __alloc_simple_buffer(dev, size, gfp, &page); |
633dc92a | 712 | else if (!(gfp & __GFP_WAIT)) |
e9da6e99 | 713 | addr = __alloc_from_pool(size, &page); |
e464ef16 | 714 | else if (!dev_get_cma_area(dev)) |
c7909509 | 715 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 716 | else |
9848e48f | 717 | addr = __alloc_from_contiguous(dev, size, prot, &page, caller); |
695ae0af | 718 | |
31ebf944 | 719 | if (addr) |
9eedd963 | 720 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 721 | |
31ebf944 RK |
722 | return addr; |
723 | } | |
1da177e4 LT |
724 | |
725 | /* | |
726 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
727 | * virtual and bus address for that space. | |
728 | */ | |
f99d6034 MS |
729 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
730 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 731 | { |
0ea1ec71 | 732 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 DB |
733 | void *memory; |
734 | ||
735 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
736 | return memory; | |
737 | ||
dd37e940 RH |
738 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
739 | __builtin_return_address(0)); | |
740 | } | |
741 | ||
742 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
743 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
744 | { | |
0ea1ec71 | 745 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
dd37e940 RH |
746 | void *memory; |
747 | ||
748 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
749 | return memory; | |
750 | ||
751 | return __dma_alloc(dev, size, handle, gfp, prot, true, | |
45cd5290 | 752 | __builtin_return_address(0)); |
1da177e4 | 753 | } |
1da177e4 LT |
754 | |
755 | /* | |
f99d6034 | 756 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 757 | */ |
f99d6034 MS |
758 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
759 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
760 | struct dma_attrs *attrs) | |
1da177e4 | 761 | { |
ab6494f0 CM |
762 | int ret = -ENXIO; |
763 | #ifdef CONFIG_MMU | |
50262a4b MS |
764 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
765 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 766 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
767 | unsigned long off = vma->vm_pgoff; |
768 | ||
f99d6034 MS |
769 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
770 | ||
47142f07 MS |
771 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
772 | return ret; | |
773 | ||
50262a4b MS |
774 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
775 | ret = remap_pfn_range(vma, vma->vm_start, | |
776 | pfn + off, | |
777 | vma->vm_end - vma->vm_start, | |
778 | vma->vm_page_prot); | |
779 | } | |
ab6494f0 | 780 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
781 | |
782 | return ret; | |
783 | } | |
784 | ||
1da177e4 | 785 | /* |
c7909509 | 786 | * Free a buffer as defined by the above mapping. |
1da177e4 | 787 | */ |
dd37e940 RH |
788 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
789 | dma_addr_t handle, struct dma_attrs *attrs, | |
790 | bool is_coherent) | |
1da177e4 | 791 | { |
c7909509 | 792 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 793 | |
1fe53268 DB |
794 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
795 | return; | |
796 | ||
3e82d012 RK |
797 | size = PAGE_ALIGN(size); |
798 | ||
dd37e940 | 799 | if (is_coherent || nommu()) { |
c7909509 | 800 | __dma_free_buffer(page, size); |
d9e0d149 AK |
801 | } else if (__free_from_pool(cpu_addr, size)) { |
802 | return; | |
e464ef16 | 803 | } else if (!dev_get_cma_area(dev)) { |
695ae0af | 804 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
805 | __dma_free_buffer(page, size); |
806 | } else { | |
c7909509 MS |
807 | /* |
808 | * Non-atomic allocations cannot be freed with IRQs disabled | |
809 | */ | |
810 | WARN_ON(irqs_disabled()); | |
9848e48f | 811 | __free_from_contiguous(dev, page, cpu_addr, size); |
c7909509 | 812 | } |
1da177e4 | 813 | } |
afd1a321 | 814 | |
dd37e940 RH |
815 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
816 | dma_addr_t handle, struct dma_attrs *attrs) | |
817 | { | |
818 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
819 | } | |
820 | ||
821 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
822 | dma_addr_t handle, struct dma_attrs *attrs) | |
823 | { | |
824 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
825 | } | |
826 | ||
dc2832e1 MS |
827 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
828 | void *cpu_addr, dma_addr_t handle, size_t size, | |
829 | struct dma_attrs *attrs) | |
830 | { | |
831 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
832 | int ret; | |
833 | ||
834 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
835 | if (unlikely(ret)) | |
836 | return ret; | |
837 | ||
838 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
839 | return 0; | |
840 | } | |
841 | ||
4ea0d737 | 842 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
843 | size_t size, enum dma_data_direction dir, |
844 | void (*op)(const void *, size_t, int)) | |
43377453 | 845 | { |
15653371 RK |
846 | unsigned long pfn; |
847 | size_t left = size; | |
848 | ||
849 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
850 | offset %= PAGE_SIZE; | |
851 | ||
43377453 NP |
852 | /* |
853 | * A single sg entry may refer to multiple physically contiguous | |
854 | * pages. But we still need to process highmem pages individually. | |
855 | * If highmem is not configured then the bulk of this loop gets | |
856 | * optimized out. | |
857 | */ | |
43377453 NP |
858 | do { |
859 | size_t len = left; | |
93f1d629 RK |
860 | void *vaddr; |
861 | ||
15653371 RK |
862 | page = pfn_to_page(pfn); |
863 | ||
93f1d629 | 864 | if (PageHighMem(page)) { |
15653371 | 865 | if (len + offset > PAGE_SIZE) |
93f1d629 | 866 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
867 | |
868 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 869 | vaddr = kmap_atomic(page); |
7e5a69e8 | 870 | op(vaddr + offset, len, dir); |
39af22a7 | 871 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
872 | } else { |
873 | vaddr = kmap_high_get(page); | |
874 | if (vaddr) { | |
875 | op(vaddr + offset, len, dir); | |
876 | kunmap_high(page); | |
877 | } | |
43377453 | 878 | } |
93f1d629 RK |
879 | } else { |
880 | vaddr = page_address(page) + offset; | |
a9c9147e | 881 | op(vaddr, len, dir); |
43377453 | 882 | } |
43377453 | 883 | offset = 0; |
15653371 | 884 | pfn++; |
43377453 NP |
885 | left -= len; |
886 | } while (left); | |
887 | } | |
4ea0d737 | 888 | |
51fde349 MS |
889 | /* |
890 | * Make an area consistent for devices. | |
891 | * Note: Drivers should NOT use this function directly, as it will break | |
892 | * platforms with CONFIG_DMABOUNCE. | |
893 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
894 | */ | |
895 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
896 | size_t size, enum dma_data_direction dir) |
897 | { | |
2161c248 | 898 | phys_addr_t paddr; |
65af191a | 899 | |
a9c9147e | 900 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
901 | |
902 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
903 | if (dir == DMA_FROM_DEVICE) { |
904 | outer_inv_range(paddr, paddr + size); | |
905 | } else { | |
906 | outer_clean_range(paddr, paddr + size); | |
907 | } | |
908 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 909 | } |
4ea0d737 | 910 | |
51fde349 | 911 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
912 | size_t size, enum dma_data_direction dir) |
913 | { | |
2161c248 | 914 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
915 | |
916 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
917 | /* in any case, don't bother invalidating if DMA to device */ |
918 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
919 | outer_inv_range(paddr, paddr + size); |
920 | ||
deace4a6 RK |
921 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
922 | } | |
c0177800 CM |
923 | |
924 | /* | |
b2a234ed | 925 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 926 | */ |
b2a234ed ML |
927 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
928 | unsigned long pfn; | |
929 | size_t left = size; | |
930 | ||
931 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
932 | off %= PAGE_SIZE; | |
933 | if (off) { | |
934 | pfn++; | |
935 | left -= PAGE_SIZE - off; | |
936 | } | |
937 | while (left >= PAGE_SIZE) { | |
938 | page = pfn_to_page(pfn++); | |
939 | set_bit(PG_dcache_clean, &page->flags); | |
940 | left -= PAGE_SIZE; | |
941 | } | |
942 | } | |
4ea0d737 | 943 | } |
43377453 | 944 | |
afd1a321 | 945 | /** |
2a550e73 | 946 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
947 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
948 | * @sg: list of buffers | |
949 | * @nents: number of buffers to map | |
950 | * @dir: DMA transfer direction | |
951 | * | |
952 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
953 | * This is the scatter-gather version of the dma_map_single interface. | |
954 | * Here the scatter gather list elements are each tagged with the | |
955 | * appropriate dma address and length. They are obtained via | |
956 | * sg_dma_{address,length}. | |
957 | * | |
958 | * Device ownership issues as mentioned for dma_map_single are the same | |
959 | * here. | |
960 | */ | |
2dc6a016 MS |
961 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
962 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 963 | { |
2a550e73 | 964 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 965 | struct scatterlist *s; |
01135d92 | 966 | int i, j; |
afd1a321 RK |
967 | |
968 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
969 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
970 | s->dma_length = s->length; | |
971 | #endif | |
2a550e73 MS |
972 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
973 | s->length, dir, attrs); | |
01135d92 RK |
974 | if (dma_mapping_error(dev, s->dma_address)) |
975 | goto bad_mapping; | |
afd1a321 | 976 | } |
afd1a321 | 977 | return nents; |
01135d92 RK |
978 | |
979 | bad_mapping: | |
980 | for_each_sg(sg, s, i, j) | |
2a550e73 | 981 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 982 | return 0; |
afd1a321 | 983 | } |
afd1a321 RK |
984 | |
985 | /** | |
2a550e73 | 986 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
987 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
988 | * @sg: list of buffers | |
0adfca6f | 989 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
990 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
991 | * | |
992 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
993 | * rules concerning calls here are the same as for dma_unmap_single(). | |
994 | */ | |
2dc6a016 MS |
995 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
996 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 997 | { |
2a550e73 | 998 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 999 | struct scatterlist *s; |
01135d92 | 1000 | |
01135d92 | 1001 | int i; |
24056f52 | 1002 | |
01135d92 | 1003 | for_each_sg(sg, s, nents, i) |
2a550e73 | 1004 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 1005 | } |
afd1a321 RK |
1006 | |
1007 | /** | |
2a550e73 | 1008 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
1009 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1010 | * @sg: list of buffers | |
1011 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1012 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1013 | */ | |
2dc6a016 | 1014 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1015 | int nents, enum dma_data_direction dir) |
1016 | { | |
2a550e73 | 1017 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1018 | struct scatterlist *s; |
1019 | int i; | |
1020 | ||
2a550e73 MS |
1021 | for_each_sg(sg, s, nents, i) |
1022 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
1023 | dir); | |
afd1a321 | 1024 | } |
afd1a321 RK |
1025 | |
1026 | /** | |
2a550e73 | 1027 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
1028 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1029 | * @sg: list of buffers | |
1030 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1031 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1032 | */ | |
2dc6a016 | 1033 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1034 | int nents, enum dma_data_direction dir) |
1035 | { | |
2a550e73 | 1036 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1037 | struct scatterlist *s; |
1038 | int i; | |
1039 | ||
2a550e73 MS |
1040 | for_each_sg(sg, s, nents, i) |
1041 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
1042 | dir); | |
afd1a321 | 1043 | } |
24056f52 | 1044 | |
022ae537 RK |
1045 | /* |
1046 | * Return whether the given device DMA address mask can be supported | |
1047 | * properly. For example, if your device can only drive the low 24-bits | |
1048 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
1049 | * to this function. | |
1050 | */ | |
1051 | int dma_supported(struct device *dev, u64 mask) | |
1052 | { | |
9f28cde0 | 1053 | return __dma_supported(dev, mask, false); |
022ae537 RK |
1054 | } |
1055 | EXPORT_SYMBOL(dma_supported); | |
1056 | ||
87b54e78 | 1057 | int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
1058 | { |
1059 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
1060 | return -EIO; | |
1061 | ||
022ae537 | 1062 | *dev->dma_mask = dma_mask; |
022ae537 RK |
1063 | |
1064 | return 0; | |
1065 | } | |
022ae537 | 1066 | |
24056f52 RK |
1067 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1068 | ||
1069 | static int __init dma_debug_do_init(void) | |
1070 | { | |
1071 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1072 | return 0; | |
1073 | } | |
1074 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
1075 | |
1076 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1077 | ||
1078 | /* IOMMU */ | |
1079 | ||
4d852ef8 AH |
1080 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1081 | ||
4ce63fcd MS |
1082 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1083 | size_t size) | |
1084 | { | |
1085 | unsigned int order = get_order(size); | |
1086 | unsigned int align = 0; | |
1087 | unsigned int count, start; | |
006f841d | 1088 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1089 | unsigned long flags; |
4d852ef8 AH |
1090 | dma_addr_t iova; |
1091 | int i; | |
4ce63fcd | 1092 | |
60460abf SWK |
1093 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1094 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1095 | ||
68efd7d2 MS |
1096 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1097 | align = (1 << order) - 1; | |
4ce63fcd MS |
1098 | |
1099 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1100 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1101 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1102 | mapping->bits, 0, count, align); | |
1103 | ||
1104 | if (start > mapping->bits) | |
1105 | continue; | |
1106 | ||
1107 | bitmap_set(mapping->bitmaps[i], start, count); | |
1108 | break; | |
4ce63fcd MS |
1109 | } |
1110 | ||
4d852ef8 AH |
1111 | /* |
1112 | * No unused range found. Try to extend the existing mapping | |
1113 | * and perform a second attempt to reserve an IO virtual | |
1114 | * address range of size bytes. | |
1115 | */ | |
1116 | if (i == mapping->nr_bitmaps) { | |
1117 | if (extend_iommu_mapping(mapping)) { | |
1118 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1119 | return DMA_ERROR_CODE; | |
1120 | } | |
1121 | ||
1122 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1123 | mapping->bits, 0, count, align); | |
1124 | ||
1125 | if (start > mapping->bits) { | |
1126 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1127 | return DMA_ERROR_CODE; | |
1128 | } | |
1129 | ||
1130 | bitmap_set(mapping->bitmaps[i], start, count); | |
1131 | } | |
4ce63fcd MS |
1132 | spin_unlock_irqrestore(&mapping->lock, flags); |
1133 | ||
006f841d | 1134 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1135 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1136 | |
1137 | return iova; | |
4ce63fcd MS |
1138 | } |
1139 | ||
1140 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1141 | dma_addr_t addr, size_t size) | |
1142 | { | |
4d852ef8 | 1143 | unsigned int start, count; |
006f841d | 1144 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1145 | unsigned long flags; |
4d852ef8 AH |
1146 | dma_addr_t bitmap_base; |
1147 | u32 bitmap_index; | |
1148 | ||
1149 | if (!size) | |
1150 | return; | |
1151 | ||
006f841d | 1152 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1153 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1154 | ||
006f841d | 1155 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1156 | |
68efd7d2 | 1157 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1158 | |
006f841d | 1159 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1160 | /* |
1161 | * The address range to be freed reaches into the iova | |
1162 | * range of the next bitmap. This should not happen as | |
1163 | * we don't allow this in __alloc_iova (at the | |
1164 | * moment). | |
1165 | */ | |
1166 | BUG(); | |
1167 | } else | |
68efd7d2 | 1168 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1169 | |
1170 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1171 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1172 | spin_unlock_irqrestore(&mapping->lock, flags); |
1173 | } | |
1174 | ||
549a17e4 MS |
1175 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
1176 | gfp_t gfp, struct dma_attrs *attrs) | |
4ce63fcd MS |
1177 | { |
1178 | struct page **pages; | |
1179 | int count = size >> PAGE_SHIFT; | |
1180 | int array_size = count * sizeof(struct page *); | |
1181 | int i = 0; | |
1182 | ||
1183 | if (array_size <= PAGE_SIZE) | |
1184 | pages = kzalloc(array_size, gfp); | |
1185 | else | |
1186 | pages = vzalloc(array_size); | |
1187 | if (!pages) | |
1188 | return NULL; | |
1189 | ||
549a17e4 MS |
1190 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) |
1191 | { | |
1192 | unsigned long order = get_order(size); | |
1193 | struct page *page; | |
1194 | ||
1195 | page = dma_alloc_from_contiguous(dev, count, order); | |
1196 | if (!page) | |
1197 | goto error; | |
1198 | ||
1199 | __dma_clear_buffer(page, size); | |
1200 | ||
1201 | for (i = 0; i < count; i++) | |
1202 | pages[i] = page + i; | |
1203 | ||
1204 | return pages; | |
1205 | } | |
1206 | ||
f8669bef MS |
1207 | /* |
1208 | * IOMMU can map any pages, so himem can also be used here | |
1209 | */ | |
1210 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1211 | ||
4ce63fcd | 1212 | while (count) { |
593f4735 | 1213 | int j, order = __fls(count); |
4ce63fcd | 1214 | |
f8669bef | 1215 | pages[i] = alloc_pages(gfp, order); |
4ce63fcd | 1216 | while (!pages[i] && order) |
f8669bef | 1217 | pages[i] = alloc_pages(gfp, --order); |
4ce63fcd MS |
1218 | if (!pages[i]) |
1219 | goto error; | |
1220 | ||
5a796eeb | 1221 | if (order) { |
4ce63fcd | 1222 | split_page(pages[i], order); |
5a796eeb HD |
1223 | j = 1 << order; |
1224 | while (--j) | |
1225 | pages[i + j] = pages[i] + j; | |
1226 | } | |
4ce63fcd MS |
1227 | |
1228 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1229 | i += 1 << order; | |
1230 | count -= 1 << order; | |
1231 | } | |
1232 | ||
1233 | return pages; | |
1234 | error: | |
9fa8af91 | 1235 | while (i--) |
4ce63fcd MS |
1236 | if (pages[i]) |
1237 | __free_pages(pages[i], 0); | |
46c87852 | 1238 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1239 | kfree(pages); |
1240 | else | |
1241 | vfree(pages); | |
1242 | return NULL; | |
1243 | } | |
1244 | ||
549a17e4 MS |
1245 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
1246 | size_t size, struct dma_attrs *attrs) | |
4ce63fcd MS |
1247 | { |
1248 | int count = size >> PAGE_SHIFT; | |
1249 | int array_size = count * sizeof(struct page *); | |
1250 | int i; | |
549a17e4 MS |
1251 | |
1252 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { | |
1253 | dma_release_from_contiguous(dev, pages[0], count); | |
1254 | } else { | |
1255 | for (i = 0; i < count; i++) | |
1256 | if (pages[i]) | |
1257 | __free_pages(pages[i], 0); | |
1258 | } | |
1259 | ||
46c87852 | 1260 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1261 | kfree(pages); |
1262 | else | |
1263 | vfree(pages); | |
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | /* | |
1268 | * Create a CPU mapping for a specified pages | |
1269 | */ | |
1270 | static void * | |
e9da6e99 MS |
1271 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1272 | const void *caller) | |
4ce63fcd | 1273 | { |
e9da6e99 MS |
1274 | unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1275 | struct vm_struct *area; | |
1276 | unsigned long p; | |
4ce63fcd | 1277 | |
e9da6e99 MS |
1278 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, |
1279 | caller); | |
1280 | if (!area) | |
4ce63fcd | 1281 | return NULL; |
4ce63fcd | 1282 | |
e9da6e99 MS |
1283 | area->pages = pages; |
1284 | area->nr_pages = nr_pages; | |
1285 | p = (unsigned long)area->addr; | |
4ce63fcd | 1286 | |
e9da6e99 MS |
1287 | for (i = 0; i < nr_pages; i++) { |
1288 | phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i])); | |
1289 | if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot)) | |
1290 | goto err; | |
1291 | p += PAGE_SIZE; | |
4ce63fcd | 1292 | } |
e9da6e99 MS |
1293 | return area->addr; |
1294 | err: | |
1295 | unmap_kernel_range((unsigned long)area->addr, size); | |
1296 | vunmap(area->addr); | |
4ce63fcd MS |
1297 | return NULL; |
1298 | } | |
1299 | ||
1300 | /* | |
1301 | * Create a mapping in device IO address space for specified pages | |
1302 | */ | |
1303 | static dma_addr_t | |
1304 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1305 | { | |
1306 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1307 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1308 | dma_addr_t dma_addr, iova; | |
1309 | int i, ret = DMA_ERROR_CODE; | |
1310 | ||
1311 | dma_addr = __alloc_iova(mapping, size); | |
1312 | if (dma_addr == DMA_ERROR_CODE) | |
1313 | return dma_addr; | |
1314 | ||
1315 | iova = dma_addr; | |
1316 | for (i = 0; i < count; ) { | |
1317 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1318 | phys_addr_t phys = page_to_phys(pages[i]); | |
1319 | unsigned int len, j; | |
1320 | ||
1321 | for (j = i + 1; j < count; j++, next_pfn++) | |
1322 | if (page_to_pfn(pages[j]) != next_pfn) | |
1323 | break; | |
1324 | ||
1325 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 AH |
1326 | ret = iommu_map(mapping->domain, iova, phys, len, |
1327 | IOMMU_READ|IOMMU_WRITE); | |
4ce63fcd MS |
1328 | if (ret < 0) |
1329 | goto fail; | |
1330 | iova += len; | |
1331 | i = j; | |
1332 | } | |
1333 | return dma_addr; | |
1334 | fail: | |
1335 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1336 | __free_iova(mapping, dma_addr, size); | |
1337 | return DMA_ERROR_CODE; | |
1338 | } | |
1339 | ||
1340 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1341 | { | |
1342 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1343 | ||
1344 | /* | |
1345 | * add optional in-page offset from iova to size and align | |
1346 | * result to page size | |
1347 | */ | |
1348 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1349 | iova &= PAGE_MASK; | |
1350 | ||
1351 | iommu_unmap(mapping->domain, iova, size); | |
1352 | __free_iova(mapping, iova, size); | |
1353 | return 0; | |
1354 | } | |
1355 | ||
665bad7b HD |
1356 | static struct page **__atomic_get_pages(void *addr) |
1357 | { | |
1358 | struct dma_pool *pool = &atomic_pool; | |
1359 | struct page **pages = pool->pages; | |
1360 | int offs = (addr - pool->vaddr) >> PAGE_SHIFT; | |
1361 | ||
1362 | return pages + offs; | |
1363 | } | |
1364 | ||
955c757e | 1365 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1366 | { |
1367 | struct vm_struct *area; | |
1368 | ||
665bad7b HD |
1369 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1370 | return __atomic_get_pages(cpu_addr); | |
1371 | ||
955c757e MS |
1372 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1373 | return cpu_addr; | |
1374 | ||
e9da6e99 MS |
1375 | area = find_vm_area(cpu_addr); |
1376 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1377 | return area->pages; | |
1378 | return NULL; | |
1379 | } | |
1380 | ||
479ed93a HD |
1381 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, |
1382 | dma_addr_t *handle) | |
1383 | { | |
1384 | struct page *page; | |
1385 | void *addr; | |
1386 | ||
1387 | addr = __alloc_from_pool(size, &page); | |
1388 | if (!addr) | |
1389 | return NULL; | |
1390 | ||
1391 | *handle = __iommu_create_mapping(dev, &page, size); | |
1392 | if (*handle == DMA_ERROR_CODE) | |
1393 | goto err_mapping; | |
1394 | ||
1395 | return addr; | |
1396 | ||
1397 | err_mapping: | |
1398 | __free_from_pool(addr, size); | |
1399 | return NULL; | |
1400 | } | |
1401 | ||
d5898291 | 1402 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
479ed93a HD |
1403 | dma_addr_t handle, size_t size) |
1404 | { | |
1405 | __iommu_remove_mapping(dev, handle, size); | |
d5898291 | 1406 | __free_from_pool(cpu_addr, size); |
479ed93a HD |
1407 | } |
1408 | ||
4ce63fcd MS |
1409 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1410 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1411 | { | |
71b55663 | 1412 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1413 | struct page **pages; |
1414 | void *addr = NULL; | |
1415 | ||
1416 | *handle = DMA_ERROR_CODE; | |
1417 | size = PAGE_ALIGN(size); | |
1418 | ||
10c8562f | 1419 | if (!(gfp & __GFP_WAIT)) |
479ed93a HD |
1420 | return __iommu_alloc_atomic(dev, size, handle); |
1421 | ||
5b91a98c RZ |
1422 | /* |
1423 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1424 | * with __GFP_COMP being passed to split_page() which cannot | |
1425 | * handle them. The real problem is that this flag probably | |
1426 | * should be 0 on ARM as it is not supported on this | |
1427 | * platform; see CONFIG_HUGETLBFS. | |
1428 | */ | |
1429 | gfp &= ~(__GFP_COMP); | |
1430 | ||
549a17e4 | 1431 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs); |
4ce63fcd MS |
1432 | if (!pages) |
1433 | return NULL; | |
1434 | ||
1435 | *handle = __iommu_create_mapping(dev, pages, size); | |
1436 | if (*handle == DMA_ERROR_CODE) | |
1437 | goto err_buffer; | |
1438 | ||
955c757e MS |
1439 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1440 | return pages; | |
1441 | ||
e9da6e99 MS |
1442 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1443 | __builtin_return_address(0)); | |
4ce63fcd MS |
1444 | if (!addr) |
1445 | goto err_mapping; | |
1446 | ||
1447 | return addr; | |
1448 | ||
1449 | err_mapping: | |
1450 | __iommu_remove_mapping(dev, *handle, size); | |
1451 | err_buffer: | |
549a17e4 | 1452 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1453 | return NULL; |
1454 | } | |
1455 | ||
1456 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1457 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1458 | struct dma_attrs *attrs) | |
1459 | { | |
e9da6e99 MS |
1460 | unsigned long uaddr = vma->vm_start; |
1461 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1462 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1463 | |
1464 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1465 | |
e9da6e99 MS |
1466 | if (!pages) |
1467 | return -ENXIO; | |
4ce63fcd | 1468 | |
e9da6e99 MS |
1469 | do { |
1470 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1471 | if (ret) { | |
1472 | pr_err("Remapping memory failed: %d\n", ret); | |
1473 | return ret; | |
1474 | } | |
1475 | uaddr += PAGE_SIZE; | |
1476 | usize -= PAGE_SIZE; | |
1477 | } while (usize > 0); | |
4ce63fcd | 1478 | |
4ce63fcd MS |
1479 | return 0; |
1480 | } | |
1481 | ||
1482 | /* | |
1483 | * free a page as defined by the above mapping. | |
1484 | * Must not be called with IRQs disabled. | |
1485 | */ | |
1486 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1487 | dma_addr_t handle, struct dma_attrs *attrs) | |
1488 | { | |
836bfa0d | 1489 | struct page **pages; |
4ce63fcd MS |
1490 | size = PAGE_ALIGN(size); |
1491 | ||
836bfa0d YC |
1492 | if (__in_atomic_pool(cpu_addr, size)) { |
1493 | __iommu_free_atomic(dev, cpu_addr, handle, size); | |
e9da6e99 | 1494 | return; |
4ce63fcd | 1495 | } |
e9da6e99 | 1496 | |
836bfa0d YC |
1497 | pages = __iommu_get_pages(cpu_addr, attrs); |
1498 | if (!pages) { | |
1499 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1500 | return; |
1501 | } | |
1502 | ||
955c757e MS |
1503 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
1504 | unmap_kernel_range((unsigned long)cpu_addr, size); | |
1505 | vunmap(cpu_addr); | |
1506 | } | |
e9da6e99 MS |
1507 | |
1508 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1509 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1510 | } |
1511 | ||
dc2832e1 MS |
1512 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1513 | void *cpu_addr, dma_addr_t dma_addr, | |
1514 | size_t size, struct dma_attrs *attrs) | |
1515 | { | |
1516 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1517 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1518 | ||
1519 | if (!pages) | |
1520 | return -ENXIO; | |
1521 | ||
1522 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1523 | GFP_KERNEL); | |
4ce63fcd MS |
1524 | } |
1525 | ||
c9b24996 AH |
1526 | static int __dma_direction_to_prot(enum dma_data_direction dir) |
1527 | { | |
1528 | int prot; | |
1529 | ||
1530 | switch (dir) { | |
1531 | case DMA_BIDIRECTIONAL: | |
1532 | prot = IOMMU_READ | IOMMU_WRITE; | |
1533 | break; | |
1534 | case DMA_TO_DEVICE: | |
1535 | prot = IOMMU_READ; | |
1536 | break; | |
1537 | case DMA_FROM_DEVICE: | |
1538 | prot = IOMMU_WRITE; | |
1539 | break; | |
1540 | default: | |
1541 | prot = 0; | |
1542 | } | |
1543 | ||
1544 | return prot; | |
1545 | } | |
1546 | ||
4ce63fcd MS |
1547 | /* |
1548 | * Map a part of the scatter-gather list into contiguous io address space | |
1549 | */ | |
1550 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1551 | size_t size, dma_addr_t *handle, | |
0fa478df RH |
1552 | enum dma_data_direction dir, struct dma_attrs *attrs, |
1553 | bool is_coherent) | |
4ce63fcd MS |
1554 | { |
1555 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1556 | dma_addr_t iova, iova_base; | |
1557 | int ret = 0; | |
1558 | unsigned int count; | |
1559 | struct scatterlist *s; | |
c9b24996 | 1560 | int prot; |
4ce63fcd MS |
1561 | |
1562 | size = PAGE_ALIGN(size); | |
1563 | *handle = DMA_ERROR_CODE; | |
1564 | ||
1565 | iova_base = iova = __alloc_iova(mapping, size); | |
1566 | if (iova == DMA_ERROR_CODE) | |
1567 | return -ENOMEM; | |
1568 | ||
1569 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1570 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1571 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1572 | ||
0fa478df RH |
1573 | if (!is_coherent && |
1574 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1575 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1576 | ||
c9b24996 AH |
1577 | prot = __dma_direction_to_prot(dir); |
1578 | ||
1579 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1580 | if (ret < 0) |
1581 | goto fail; | |
1582 | count += len >> PAGE_SHIFT; | |
1583 | iova += len; | |
1584 | } | |
1585 | *handle = iova_base; | |
1586 | ||
1587 | return 0; | |
1588 | fail: | |
1589 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1590 | __free_iova(mapping, iova_base, size); | |
1591 | return ret; | |
1592 | } | |
1593 | ||
0fa478df RH |
1594 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
1595 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1596 | bool is_coherent) | |
4ce63fcd MS |
1597 | { |
1598 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1599 | int i, count = 0; | |
1600 | unsigned int offset = s->offset; | |
1601 | unsigned int size = s->offset + s->length; | |
1602 | unsigned int max = dma_get_max_seg_size(dev); | |
1603 | ||
1604 | for (i = 1; i < nents; i++) { | |
1605 | s = sg_next(s); | |
1606 | ||
1607 | s->dma_address = DMA_ERROR_CODE; | |
1608 | s->dma_length = 0; | |
1609 | ||
1610 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1611 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1612 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1613 | goto bad_mapping; |
1614 | ||
1615 | dma->dma_address += offset; | |
1616 | dma->dma_length = size - offset; | |
1617 | ||
1618 | size = offset = s->offset; | |
1619 | start = s; | |
1620 | dma = sg_next(dma); | |
1621 | count += 1; | |
1622 | } | |
1623 | size += s->length; | |
1624 | } | |
0fa478df RH |
1625 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1626 | is_coherent) < 0) | |
4ce63fcd MS |
1627 | goto bad_mapping; |
1628 | ||
1629 | dma->dma_address += offset; | |
1630 | dma->dma_length = size - offset; | |
1631 | ||
1632 | return count+1; | |
1633 | ||
1634 | bad_mapping: | |
1635 | for_each_sg(sg, s, count, i) | |
1636 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1637 | return 0; | |
1638 | } | |
1639 | ||
1640 | /** | |
0fa478df | 1641 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1642 | * @dev: valid struct device pointer |
1643 | * @sg: list of buffers | |
0fa478df RH |
1644 | * @nents: number of buffers to map |
1645 | * @dir: DMA transfer direction | |
4ce63fcd | 1646 | * |
0fa478df RH |
1647 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1648 | * mode for DMA. The scatter gather list elements are merged together (if | |
1649 | * possible) and tagged with the appropriate dma address and length. They are | |
1650 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1651 | */ |
0fa478df RH |
1652 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
1653 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1654 | { | |
1655 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1656 | } | |
1657 | ||
1658 | /** | |
1659 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1660 | * @dev: valid struct device pointer | |
1661 | * @sg: list of buffers | |
1662 | * @nents: number of buffers to map | |
1663 | * @dir: DMA transfer direction | |
1664 | * | |
1665 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1666 | * The scatter gather list elements are merged together (if possible) and | |
1667 | * tagged with the appropriate dma address and length. They are obtained via | |
1668 | * sg_dma_{address,length}. | |
1669 | */ | |
1670 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1671 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1672 | { | |
1673 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1674 | } | |
1675 | ||
1676 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1677 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs, | |
1678 | bool is_coherent) | |
4ce63fcd MS |
1679 | { |
1680 | struct scatterlist *s; | |
1681 | int i; | |
1682 | ||
1683 | for_each_sg(sg, s, nents, i) { | |
1684 | if (sg_dma_len(s)) | |
1685 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1686 | sg_dma_len(s)); | |
0fa478df | 1687 | if (!is_coherent && |
97ef952a | 1688 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1689 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1690 | s->length, dir); | |
1691 | } | |
1692 | } | |
1693 | ||
0fa478df RH |
1694 | /** |
1695 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1696 | * @dev: valid struct device pointer | |
1697 | * @sg: list of buffers | |
1698 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1699 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1700 | * | |
1701 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1702 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1703 | */ | |
1704 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1705 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1706 | { | |
1707 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1708 | } | |
1709 | ||
1710 | /** | |
1711 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1712 | * @dev: valid struct device pointer | |
1713 | * @sg: list of buffers | |
1714 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1715 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1716 | * | |
1717 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1718 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1719 | */ | |
1720 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1721 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1722 | { | |
1723 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1724 | } | |
1725 | ||
4ce63fcd MS |
1726 | /** |
1727 | * arm_iommu_sync_sg_for_cpu | |
1728 | * @dev: valid struct device pointer | |
1729 | * @sg: list of buffers | |
1730 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1731 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1732 | */ | |
1733 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1734 | int nents, enum dma_data_direction dir) | |
1735 | { | |
1736 | struct scatterlist *s; | |
1737 | int i; | |
1738 | ||
1739 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1740 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1741 | |
1742 | } | |
1743 | ||
1744 | /** | |
1745 | * arm_iommu_sync_sg_for_device | |
1746 | * @dev: valid struct device pointer | |
1747 | * @sg: list of buffers | |
1748 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1749 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1750 | */ | |
1751 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1752 | int nents, enum dma_data_direction dir) | |
1753 | { | |
1754 | struct scatterlist *s; | |
1755 | int i; | |
1756 | ||
1757 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1758 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1759 | } |
1760 | ||
1761 | ||
1762 | /** | |
0fa478df | 1763 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1764 | * @dev: valid struct device pointer |
1765 | * @page: page that buffer resides in | |
1766 | * @offset: offset into page for start of buffer | |
1767 | * @size: size of buffer to map | |
1768 | * @dir: DMA transfer direction | |
1769 | * | |
0fa478df | 1770 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1771 | */ |
0fa478df | 1772 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd MS |
1773 | unsigned long offset, size_t size, enum dma_data_direction dir, |
1774 | struct dma_attrs *attrs) | |
1775 | { | |
1776 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1777 | dma_addr_t dma_addr; | |
13987d68 | 1778 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1779 | |
4ce63fcd MS |
1780 | dma_addr = __alloc_iova(mapping, len); |
1781 | if (dma_addr == DMA_ERROR_CODE) | |
1782 | return dma_addr; | |
1783 | ||
c9b24996 | 1784 | prot = __dma_direction_to_prot(dir); |
13987d68 WD |
1785 | |
1786 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1787 | if (ret < 0) |
1788 | goto fail; | |
1789 | ||
1790 | return dma_addr + offset; | |
1791 | fail: | |
1792 | __free_iova(mapping, dma_addr, len); | |
1793 | return DMA_ERROR_CODE; | |
1794 | } | |
1795 | ||
0fa478df RH |
1796 | /** |
1797 | * arm_iommu_map_page | |
1798 | * @dev: valid struct device pointer | |
1799 | * @page: page that buffer resides in | |
1800 | * @offset: offset into page for start of buffer | |
1801 | * @size: size of buffer to map | |
1802 | * @dir: DMA transfer direction | |
1803 | * | |
1804 | * IOMMU aware version of arm_dma_map_page() | |
1805 | */ | |
1806 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1807 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1808 | struct dma_attrs *attrs) | |
1809 | { | |
1810 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1811 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1812 | ||
1813 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1814 | } | |
1815 | ||
1816 | /** | |
1817 | * arm_coherent_iommu_unmap_page | |
1818 | * @dev: valid struct device pointer | |
1819 | * @handle: DMA address of buffer | |
1820 | * @size: size of buffer (same as passed to dma_map_page) | |
1821 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1822 | * | |
1823 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1824 | */ | |
1825 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1826 | size_t size, enum dma_data_direction dir, | |
1827 | struct dma_attrs *attrs) | |
1828 | { | |
1829 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1830 | dma_addr_t iova = handle & PAGE_MASK; | |
0fa478df RH |
1831 | int offset = handle & ~PAGE_MASK; |
1832 | int len = PAGE_ALIGN(size + offset); | |
1833 | ||
1834 | if (!iova) | |
1835 | return; | |
1836 | ||
1837 | iommu_unmap(mapping->domain, iova, len); | |
1838 | __free_iova(mapping, iova, len); | |
1839 | } | |
1840 | ||
4ce63fcd MS |
1841 | /** |
1842 | * arm_iommu_unmap_page | |
1843 | * @dev: valid struct device pointer | |
1844 | * @handle: DMA address of buffer | |
1845 | * @size: size of buffer (same as passed to dma_map_page) | |
1846 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1847 | * | |
1848 | * IOMMU aware version of arm_dma_unmap_page() | |
1849 | */ | |
1850 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1851 | size_t size, enum dma_data_direction dir, | |
1852 | struct dma_attrs *attrs) | |
1853 | { | |
1854 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1855 | dma_addr_t iova = handle & PAGE_MASK; | |
1856 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1857 | int offset = handle & ~PAGE_MASK; | |
1858 | int len = PAGE_ALIGN(size + offset); | |
1859 | ||
1860 | if (!iova) | |
1861 | return; | |
1862 | ||
0fa478df | 1863 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1864 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1865 | ||
1866 | iommu_unmap(mapping->domain, iova, len); | |
1867 | __free_iova(mapping, iova, len); | |
1868 | } | |
1869 | ||
1870 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1871 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1872 | { | |
1873 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1874 | dma_addr_t iova = handle & PAGE_MASK; | |
1875 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1876 | unsigned int offset = handle & ~PAGE_MASK; | |
1877 | ||
1878 | if (!iova) | |
1879 | return; | |
1880 | ||
0fa478df | 1881 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
1882 | } |
1883 | ||
1884 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1885 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1886 | { | |
1887 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1888 | dma_addr_t iova = handle & PAGE_MASK; | |
1889 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1890 | unsigned int offset = handle & ~PAGE_MASK; | |
1891 | ||
1892 | if (!iova) | |
1893 | return; | |
1894 | ||
1895 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1896 | } | |
1897 | ||
1898 | struct dma_map_ops iommu_ops = { | |
1899 | .alloc = arm_iommu_alloc_attrs, | |
1900 | .free = arm_iommu_free_attrs, | |
1901 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1902 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1903 | |
1904 | .map_page = arm_iommu_map_page, | |
1905 | .unmap_page = arm_iommu_unmap_page, | |
1906 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1907 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1908 | ||
1909 | .map_sg = arm_iommu_map_sg, | |
1910 | .unmap_sg = arm_iommu_unmap_sg, | |
1911 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1912 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
d09e1333 HD |
1913 | |
1914 | .set_dma_mask = arm_dma_set_mask, | |
4ce63fcd MS |
1915 | }; |
1916 | ||
0fa478df RH |
1917 | struct dma_map_ops iommu_coherent_ops = { |
1918 | .alloc = arm_iommu_alloc_attrs, | |
1919 | .free = arm_iommu_free_attrs, | |
1920 | .mmap = arm_iommu_mmap_attrs, | |
1921 | .get_sgtable = arm_iommu_get_sgtable, | |
1922 | ||
1923 | .map_page = arm_coherent_iommu_map_page, | |
1924 | .unmap_page = arm_coherent_iommu_unmap_page, | |
1925 | ||
1926 | .map_sg = arm_coherent_iommu_map_sg, | |
1927 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
d09e1333 HD |
1928 | |
1929 | .set_dma_mask = arm_dma_set_mask, | |
0fa478df RH |
1930 | }; |
1931 | ||
4ce63fcd MS |
1932 | /** |
1933 | * arm_iommu_create_mapping | |
1934 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1935 | * @base: start address of the valid IO address space | |
68efd7d2 | 1936 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
1937 | * |
1938 | * Creates a mapping structure which holds information about used/unused | |
1939 | * IO address ranges, which is required to perform memory allocation and | |
1940 | * mapping with IOMMU aware functions. | |
1941 | * | |
1942 | * The client device need to be attached to the mapping with | |
1943 | * arm_iommu_attach_device function. | |
1944 | */ | |
1945 | struct dma_iommu_mapping * | |
68efd7d2 | 1946 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) |
4ce63fcd | 1947 | { |
68efd7d2 MS |
1948 | unsigned int bits = size >> PAGE_SHIFT; |
1949 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 1950 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 1951 | int extensions = 1; |
4ce63fcd MS |
1952 | int err = -ENOMEM; |
1953 | ||
68efd7d2 | 1954 | if (!bitmap_size) |
4ce63fcd MS |
1955 | return ERR_PTR(-EINVAL); |
1956 | ||
68efd7d2 MS |
1957 | if (bitmap_size > PAGE_SIZE) { |
1958 | extensions = bitmap_size / PAGE_SIZE; | |
1959 | bitmap_size = PAGE_SIZE; | |
1960 | } | |
1961 | ||
4ce63fcd MS |
1962 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
1963 | if (!mapping) | |
1964 | goto err; | |
1965 | ||
68efd7d2 MS |
1966 | mapping->bitmap_size = bitmap_size; |
1967 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
4d852ef8 AH |
1968 | GFP_KERNEL); |
1969 | if (!mapping->bitmaps) | |
4ce63fcd MS |
1970 | goto err2; |
1971 | ||
68efd7d2 | 1972 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
1973 | if (!mapping->bitmaps[0]) |
1974 | goto err3; | |
1975 | ||
1976 | mapping->nr_bitmaps = 1; | |
1977 | mapping->extensions = extensions; | |
4ce63fcd | 1978 | mapping->base = base; |
68efd7d2 | 1979 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 1980 | |
4ce63fcd MS |
1981 | spin_lock_init(&mapping->lock); |
1982 | ||
1983 | mapping->domain = iommu_domain_alloc(bus); | |
1984 | if (!mapping->domain) | |
4d852ef8 | 1985 | goto err4; |
4ce63fcd MS |
1986 | |
1987 | kref_init(&mapping->kref); | |
1988 | return mapping; | |
4d852ef8 AH |
1989 | err4: |
1990 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 1991 | err3: |
4d852ef8 | 1992 | kfree(mapping->bitmaps); |
4ce63fcd MS |
1993 | err2: |
1994 | kfree(mapping); | |
1995 | err: | |
1996 | return ERR_PTR(err); | |
1997 | } | |
18177d12 | 1998 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
1999 | |
2000 | static void release_iommu_mapping(struct kref *kref) | |
2001 | { | |
4d852ef8 | 2002 | int i; |
4ce63fcd MS |
2003 | struct dma_iommu_mapping *mapping = |
2004 | container_of(kref, struct dma_iommu_mapping, kref); | |
2005 | ||
2006 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
2007 | for (i = 0; i < mapping->nr_bitmaps; i++) |
2008 | kfree(mapping->bitmaps[i]); | |
2009 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
2010 | kfree(mapping); |
2011 | } | |
2012 | ||
4d852ef8 AH |
2013 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
2014 | { | |
2015 | int next_bitmap; | |
2016 | ||
2017 | if (mapping->nr_bitmaps > mapping->extensions) | |
2018 | return -EINVAL; | |
2019 | ||
2020 | next_bitmap = mapping->nr_bitmaps; | |
2021 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
2022 | GFP_ATOMIC); | |
2023 | if (!mapping->bitmaps[next_bitmap]) | |
2024 | return -ENOMEM; | |
2025 | ||
2026 | mapping->nr_bitmaps++; | |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | ||
4ce63fcd MS |
2031 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
2032 | { | |
2033 | if (mapping) | |
2034 | kref_put(&mapping->kref, release_iommu_mapping); | |
2035 | } | |
18177d12 | 2036 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd MS |
2037 | |
2038 | /** | |
2039 | * arm_iommu_attach_device | |
2040 | * @dev: valid struct device pointer | |
2041 | * @mapping: io address space mapping structure (returned from | |
2042 | * arm_iommu_create_mapping) | |
2043 | * | |
2044 | * Attaches specified io address space mapping to the provided device, | |
2045 | * this replaces the dma operations (dma_map_ops pointer) with the | |
2046 | * IOMMU aware version. More than one client might be attached to | |
2047 | * the same io address space mapping. | |
2048 | */ | |
2049 | int arm_iommu_attach_device(struct device *dev, | |
2050 | struct dma_iommu_mapping *mapping) | |
2051 | { | |
2052 | int err; | |
2053 | ||
2054 | err = iommu_attach_device(mapping->domain, dev); | |
2055 | if (err) | |
2056 | return err; | |
2057 | ||
2058 | kref_get(&mapping->kref); | |
2059 | dev->archdata.mapping = mapping; | |
2060 | set_dma_ops(dev, &iommu_ops); | |
2061 | ||
75c59716 | 2062 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); |
4ce63fcd MS |
2063 | return 0; |
2064 | } | |
18177d12 | 2065 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2066 | |
6fe36758 HD |
2067 | /** |
2068 | * arm_iommu_detach_device | |
2069 | * @dev: valid struct device pointer | |
2070 | * | |
2071 | * Detaches the provided device from a previously attached map. | |
2072 | * This voids the dma operations (dma_map_ops pointer) | |
2073 | */ | |
2074 | void arm_iommu_detach_device(struct device *dev) | |
2075 | { | |
2076 | struct dma_iommu_mapping *mapping; | |
2077 | ||
2078 | mapping = to_dma_iommu_mapping(dev); | |
2079 | if (!mapping) { | |
2080 | dev_warn(dev, "Not attached\n"); | |
2081 | return; | |
2082 | } | |
2083 | ||
2084 | iommu_detach_device(mapping->domain, dev); | |
2085 | kref_put(&mapping->kref, release_iommu_mapping); | |
9e4b259d | 2086 | dev->archdata.mapping = NULL; |
6fe36758 HD |
2087 | set_dma_ops(dev, NULL); |
2088 | ||
2089 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2090 | } | |
18177d12 | 2091 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2092 | |
4ce63fcd | 2093 | #endif |