Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
c7909509 | 20 | #include <linux/dma-contiguous.h> |
39af22a7 | 21 | #include <linux/highmem.h> |
c7909509 | 22 | #include <linux/memblock.h> |
99d1717d | 23 | #include <linux/slab.h> |
4ce63fcd | 24 | #include <linux/iommu.h> |
e9da6e99 | 25 | #include <linux/io.h> |
4ce63fcd | 26 | #include <linux/vmalloc.h> |
158e8bfe | 27 | #include <linux/sizes.h> |
1da177e4 | 28 | |
23759dc6 | 29 | #include <asm/memory.h> |
43377453 | 30 | #include <asm/highmem.h> |
1da177e4 | 31 | #include <asm/cacheflush.h> |
1da177e4 | 32 | #include <asm/tlbflush.h> |
99d1717d | 33 | #include <asm/mach/arch.h> |
4ce63fcd | 34 | #include <asm/dma-iommu.h> |
c7909509 MS |
35 | #include <asm/mach/map.h> |
36 | #include <asm/system_info.h> | |
37 | #include <asm/dma-contiguous.h> | |
37134cd5 | 38 | |
022ae537 RK |
39 | #include "mm.h" |
40 | ||
15237e1f MS |
41 | /* |
42 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
43 | * is either exclusively owned by the CPU (and therefore may be accessed | |
44 | * by it) or exclusively owned by the DMA device. These helper functions | |
45 | * represent the transitions between these two ownership states. | |
46 | * | |
47 | * Note, however, that on later ARMs, this notion does not work due to | |
48 | * speculative prefetches. We model our approach on the assumption that | |
49 | * the CPU does do speculative prefetches, which means we clean caches | |
50 | * before transfers and delay cache invalidation until transfer completion. | |
51 | * | |
15237e1f | 52 | */ |
51fde349 | 53 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 54 | size_t, enum dma_data_direction); |
51fde349 | 55 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
56 | size_t, enum dma_data_direction); |
57 | ||
2dc6a016 MS |
58 | /** |
59 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
60 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
61 | * @page: page that buffer resides in | |
62 | * @offset: offset into page for start of buffer | |
63 | * @size: size of buffer to map | |
64 | * @dir: DMA transfer direction | |
65 | * | |
66 | * Ensure that any data held in the cache is appropriately discarded | |
67 | * or written back. | |
68 | * | |
69 | * The device owns this memory once this call has completed. The CPU | |
70 | * can regain ownership by calling dma_unmap_page(). | |
71 | */ | |
51fde349 | 72 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
73 | unsigned long offset, size_t size, enum dma_data_direction dir, |
74 | struct dma_attrs *attrs) | |
75 | { | |
97ef952a | 76 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
77 | __dma_page_cpu_to_dev(page, offset, size, dir); |
78 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
79 | } |
80 | ||
81 | /** | |
82 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
83 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
84 | * @handle: DMA address of buffer | |
85 | * @size: size of buffer (same as passed to dma_map_page) | |
86 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
87 | * | |
88 | * Unmap a page streaming mode DMA translation. The handle and size | |
89 | * must match what was provided in the previous dma_map_page() call. | |
90 | * All other usages are undefined. | |
91 | * | |
92 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
93 | * whatever the device wrote there. | |
94 | */ | |
51fde349 | 95 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
96 | size_t size, enum dma_data_direction dir, |
97 | struct dma_attrs *attrs) | |
98 | { | |
97ef952a | 99 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
100 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
101 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
102 | } |
103 | ||
51fde349 | 104 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
105 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
106 | { | |
107 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
108 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
109 | if (!arch_is_coherent()) |
110 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
51fde349 | 113 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
114 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
115 | { | |
116 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
117 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
118 | if (!arch_is_coherent()) |
119 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2dc6a016 MS |
120 | } |
121 | ||
122 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
123 | ||
124 | struct dma_map_ops arm_dma_ops = { | |
f99d6034 MS |
125 | .alloc = arm_dma_alloc, |
126 | .free = arm_dma_free, | |
127 | .mmap = arm_dma_mmap, | |
dc2832e1 | 128 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
129 | .map_page = arm_dma_map_page, |
130 | .unmap_page = arm_dma_unmap_page, | |
131 | .map_sg = arm_dma_map_sg, | |
132 | .unmap_sg = arm_dma_unmap_sg, | |
133 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
134 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
135 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
136 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
137 | .set_dma_mask = arm_dma_set_mask, | |
138 | }; | |
139 | EXPORT_SYMBOL(arm_dma_ops); | |
140 | ||
ab6494f0 CM |
141 | static u64 get_coherent_dma_mask(struct device *dev) |
142 | { | |
022ae537 | 143 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
144 | |
145 | if (dev) { | |
146 | mask = dev->coherent_dma_mask; | |
147 | ||
148 | /* | |
149 | * Sanity check the DMA mask - it must be non-zero, and | |
150 | * must be able to be satisfied by a DMA allocation. | |
151 | */ | |
152 | if (mask == 0) { | |
153 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
154 | return 0; | |
155 | } | |
156 | ||
022ae537 | 157 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
158 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
159 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 160 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
161 | return 0; |
162 | } | |
163 | } | |
1da177e4 | 164 | |
ab6494f0 CM |
165 | return mask; |
166 | } | |
167 | ||
c7909509 MS |
168 | static void __dma_clear_buffer(struct page *page, size_t size) |
169 | { | |
170 | void *ptr; | |
171 | /* | |
172 | * Ensure that the allocated pages are zeroed, and that any data | |
173 | * lurking in the kernel direct-mapped region is invalidated. | |
174 | */ | |
175 | ptr = page_address(page); | |
4ce63fcd MS |
176 | if (ptr) { |
177 | memset(ptr, 0, size); | |
178 | dmac_flush_range(ptr, ptr + size); | |
179 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
180 | } | |
c7909509 MS |
181 | } |
182 | ||
7a9a32a9 RK |
183 | /* |
184 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
185 | * specified gfp mask. Note that 'size' must be page aligned. | |
186 | */ | |
187 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
188 | { | |
189 | unsigned long order = get_order(size); | |
190 | struct page *page, *p, *e; | |
7a9a32a9 RK |
191 | |
192 | page = alloc_pages(gfp, order); | |
193 | if (!page) | |
194 | return NULL; | |
195 | ||
196 | /* | |
197 | * Now split the huge page and free the excess pages | |
198 | */ | |
199 | split_page(page, order); | |
200 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
201 | __free_page(p); | |
202 | ||
c7909509 | 203 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
204 | |
205 | return page; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Free a DMA buffer. 'size' must be page aligned. | |
210 | */ | |
211 | static void __dma_free_buffer(struct page *page, size_t size) | |
212 | { | |
213 | struct page *e = page + (size >> PAGE_SHIFT); | |
214 | ||
215 | while (page < e) { | |
216 | __free_page(page); | |
217 | page++; | |
218 | } | |
219 | } | |
220 | ||
ab6494f0 | 221 | #ifdef CONFIG_MMU |
e9da6e99 MS |
222 | #ifdef CONFIG_HUGETLB_PAGE |
223 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
224 | #endif | |
a5e9d38b | 225 | |
e9da6e99 MS |
226 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
227 | pgprot_t prot, struct page **ret_page); | |
99d1717d | 228 | |
e9da6e99 MS |
229 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
230 | pgprot_t prot, struct page **ret_page, | |
231 | const void *caller); | |
99d1717d | 232 | |
e9da6e99 MS |
233 | static void * |
234 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
235 | const void *caller) | |
99d1717d | 236 | { |
e9da6e99 MS |
237 | struct vm_struct *area; |
238 | unsigned long addr; | |
99d1717d | 239 | |
e9da6e99 MS |
240 | /* |
241 | * DMA allocation can be mapped to user space, so lets | |
242 | * set VM_USERMAP flags too. | |
243 | */ | |
244 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
245 | caller); | |
246 | if (!area) | |
247 | return NULL; | |
248 | addr = (unsigned long)area->addr; | |
249 | area->phys_addr = __pfn_to_phys(page_to_pfn(page)); | |
99d1717d | 250 | |
e9da6e99 MS |
251 | if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { |
252 | vunmap((void *)addr); | |
253 | return NULL; | |
254 | } | |
255 | return (void *)addr; | |
99d1717d | 256 | } |
1da177e4 | 257 | |
e9da6e99 | 258 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 259 | { |
e9da6e99 MS |
260 | unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; |
261 | struct vm_struct *area = find_vm_area(cpu_addr); | |
262 | if (!area || (area->flags & flags) != flags) { | |
263 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
264 | return; | |
99d1717d | 265 | } |
e9da6e99 MS |
266 | unmap_kernel_range((unsigned long)cpu_addr, size); |
267 | vunmap(cpu_addr); | |
88c58f3b | 268 | } |
88c58f3b | 269 | |
6e5267aa MS |
270 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
271 | ||
e9da6e99 MS |
272 | struct dma_pool { |
273 | size_t size; | |
274 | spinlock_t lock; | |
275 | unsigned long *bitmap; | |
276 | unsigned long nr_pages; | |
277 | void *vaddr; | |
6b3fe472 | 278 | struct page **pages; |
c7909509 MS |
279 | }; |
280 | ||
e9da6e99 | 281 | static struct dma_pool atomic_pool = { |
6e5267aa | 282 | .size = DEFAULT_DMA_COHERENT_POOL_SIZE, |
e9da6e99 | 283 | }; |
c7909509 MS |
284 | |
285 | static int __init early_coherent_pool(char *p) | |
286 | { | |
e9da6e99 | 287 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
288 | return 0; |
289 | } | |
290 | early_param("coherent_pool", early_coherent_pool); | |
291 | ||
6e5267aa MS |
292 | void __init init_dma_coherent_pool_size(unsigned long size) |
293 | { | |
294 | /* | |
295 | * Catch any attempt to set the pool size too late. | |
296 | */ | |
297 | BUG_ON(atomic_pool.vaddr); | |
298 | ||
299 | /* | |
300 | * Set architecture specific coherent pool size only if | |
301 | * it has not been changed by kernel command line parameter. | |
302 | */ | |
303 | if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
304 | atomic_pool.size = size; | |
305 | } | |
306 | ||
c7909509 MS |
307 | /* |
308 | * Initialise the coherent pool for atomic allocations. | |
309 | */ | |
e9da6e99 | 310 | static int __init atomic_pool_init(void) |
c7909509 | 311 | { |
e9da6e99 | 312 | struct dma_pool *pool = &atomic_pool; |
c7909509 | 313 | pgprot_t prot = pgprot_dmacoherent(pgprot_kernel); |
e9da6e99 MS |
314 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
315 | unsigned long *bitmap; | |
c7909509 | 316 | struct page *page; |
6b3fe472 | 317 | struct page **pages; |
c7909509 | 318 | void *ptr; |
e9da6e99 | 319 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 320 | |
e9da6e99 MS |
321 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
322 | if (!bitmap) | |
323 | goto no_bitmap; | |
c7909509 | 324 | |
6b3fe472 HD |
325 | pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); |
326 | if (!pages) | |
327 | goto no_pages; | |
328 | ||
e9da6e99 MS |
329 | if (IS_ENABLED(CONFIG_CMA)) |
330 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page); | |
331 | else | |
332 | ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot, | |
333 | &page, NULL); | |
c7909509 | 334 | if (ptr) { |
6b3fe472 HD |
335 | int i; |
336 | ||
337 | for (i = 0; i < nr_pages; i++) | |
338 | pages[i] = page + i; | |
339 | ||
e9da6e99 MS |
340 | spin_lock_init(&pool->lock); |
341 | pool->vaddr = ptr; | |
6b3fe472 | 342 | pool->pages = pages; |
e9da6e99 MS |
343 | pool->bitmap = bitmap; |
344 | pool->nr_pages = nr_pages; | |
345 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
346 | (unsigned)pool->size / 1024); | |
c7909509 MS |
347 | return 0; |
348 | } | |
6b3fe472 | 349 | no_pages: |
e9da6e99 MS |
350 | kfree(bitmap); |
351 | no_bitmap: | |
352 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
353 | (unsigned)pool->size / 1024); | |
c7909509 MS |
354 | return -ENOMEM; |
355 | } | |
356 | /* | |
357 | * CMA is activated by core_initcall, so we must be called after it. | |
358 | */ | |
e9da6e99 | 359 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
360 | |
361 | struct dma_contig_early_reserve { | |
362 | phys_addr_t base; | |
363 | unsigned long size; | |
364 | }; | |
365 | ||
366 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
367 | ||
368 | static int dma_mmu_remap_num __initdata; | |
369 | ||
370 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
371 | { | |
372 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
373 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
374 | dma_mmu_remap_num++; | |
375 | } | |
376 | ||
377 | void __init dma_contiguous_remap(void) | |
378 | { | |
379 | int i; | |
380 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
381 | phys_addr_t start = dma_mmu_remap[i].base; | |
382 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
383 | struct map_desc map; | |
384 | unsigned long addr; | |
385 | ||
386 | if (end > arm_lowmem_limit) | |
387 | end = arm_lowmem_limit; | |
388 | if (start >= end) | |
39f78e70 | 389 | continue; |
c7909509 MS |
390 | |
391 | map.pfn = __phys_to_pfn(start); | |
392 | map.virtual = __phys_to_virt(start); | |
393 | map.length = end - start; | |
394 | map.type = MT_MEMORY_DMA_READY; | |
395 | ||
396 | /* | |
397 | * Clear previous low-memory mapping | |
398 | */ | |
399 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 400 | addr += PMD_SIZE) |
c7909509 MS |
401 | pmd_clear(pmd_off_k(addr)); |
402 | ||
403 | iotable_init(&map, 1); | |
404 | } | |
405 | } | |
406 | ||
c7909509 MS |
407 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
408 | void *data) | |
409 | { | |
410 | struct page *page = virt_to_page(addr); | |
411 | pgprot_t prot = *(pgprot_t *)data; | |
412 | ||
413 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
418 | { | |
419 | unsigned long start = (unsigned long) page_address(page); | |
420 | unsigned end = start + size; | |
421 | ||
422 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
423 | dsb(); | |
424 | flush_tlb_kernel_range(start, end); | |
425 | } | |
426 | ||
427 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
428 | pgprot_t prot, struct page **ret_page, | |
429 | const void *caller) | |
430 | { | |
431 | struct page *page; | |
432 | void *ptr; | |
433 | page = __dma_alloc_buffer(dev, size, gfp); | |
434 | if (!page) | |
435 | return NULL; | |
436 | ||
437 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
438 | if (!ptr) { | |
439 | __dma_free_buffer(page, size); | |
440 | return NULL; | |
441 | } | |
442 | ||
443 | *ret_page = page; | |
444 | return ptr; | |
445 | } | |
446 | ||
e9da6e99 | 447 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 448 | { |
e9da6e99 MS |
449 | struct dma_pool *pool = &atomic_pool; |
450 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
451 | unsigned int pageno; | |
452 | unsigned long flags; | |
453 | void *ptr = NULL; | |
e4ea6918 | 454 | unsigned long align_mask; |
c7909509 | 455 | |
e9da6e99 MS |
456 | if (!pool->vaddr) { |
457 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
458 | return NULL; |
459 | } | |
460 | ||
461 | /* | |
462 | * Align the region allocation - allocations from pool are rather | |
463 | * small, so align them to their order in pages, minimum is a page | |
464 | * size. This helps reduce fragmentation of the DMA space. | |
465 | */ | |
e4ea6918 | 466 | align_mask = (1 << get_order(size)) - 1; |
e9da6e99 MS |
467 | |
468 | spin_lock_irqsave(&pool->lock, flags); | |
469 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
e4ea6918 | 470 | 0, count, align_mask); |
e9da6e99 MS |
471 | if (pageno < pool->nr_pages) { |
472 | bitmap_set(pool->bitmap, pageno, count); | |
473 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
6b3fe472 | 474 | *ret_page = pool->pages[pageno]; |
fb71285f MS |
475 | } else { |
476 | pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" | |
477 | "Please increase it with coherent_pool= kernel parameter!\n", | |
478 | (unsigned)pool->size / 1024); | |
c7909509 | 479 | } |
e9da6e99 MS |
480 | spin_unlock_irqrestore(&pool->lock, flags); |
481 | ||
482 | return ptr; | |
c7909509 MS |
483 | } |
484 | ||
e9da6e99 | 485 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 486 | { |
e9da6e99 MS |
487 | struct dma_pool *pool = &atomic_pool; |
488 | unsigned long pageno, count; | |
489 | unsigned long flags; | |
c7909509 | 490 | |
e9da6e99 | 491 | if (start < pool->vaddr || start > pool->vaddr + pool->size) |
c7909509 MS |
492 | return 0; |
493 | ||
e9da6e99 MS |
494 | if (start + size > pool->vaddr + pool->size) { |
495 | WARN(1, "freeing wrong coherent size from pool\n"); | |
496 | return 0; | |
c7909509 MS |
497 | } |
498 | ||
e9da6e99 MS |
499 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
500 | count = size >> PAGE_SHIFT; | |
501 | ||
502 | spin_lock_irqsave(&pool->lock, flags); | |
503 | bitmap_clear(pool->bitmap, pageno, count); | |
504 | spin_unlock_irqrestore(&pool->lock, flags); | |
505 | ||
c7909509 MS |
506 | return 1; |
507 | } | |
508 | ||
509 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
510 | pgprot_t prot, struct page **ret_page) | |
511 | { | |
512 | unsigned long order = get_order(size); | |
513 | size_t count = size >> PAGE_SHIFT; | |
514 | struct page *page; | |
515 | ||
516 | page = dma_alloc_from_contiguous(dev, count, order); | |
517 | if (!page) | |
518 | return NULL; | |
519 | ||
520 | __dma_clear_buffer(page, size); | |
521 | __dma_remap(page, size, prot); | |
522 | ||
523 | *ret_page = page; | |
524 | return page_address(page); | |
525 | } | |
526 | ||
527 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
528 | size_t size) | |
529 | { | |
530 | __dma_remap(page, size, pgprot_kernel); | |
531 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
532 | } | |
533 | ||
f99d6034 MS |
534 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
535 | { | |
536 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
537 | pgprot_writecombine(prot) : | |
538 | pgprot_dmacoherent(prot); | |
539 | return prot; | |
540 | } | |
541 | ||
c7909509 MS |
542 | #define nommu() 0 |
543 | ||
ab6494f0 | 544 | #else /* !CONFIG_MMU */ |
695ae0af | 545 | |
c7909509 MS |
546 | #define nommu() 1 |
547 | ||
f99d6034 | 548 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 549 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 550 | #define __alloc_from_pool(size, ret_page) NULL |
c7909509 MS |
551 | #define __alloc_from_contiguous(dev, size, prot, ret) NULL |
552 | #define __free_from_pool(cpu_addr, size) 0 | |
553 | #define __free_from_contiguous(dev, page, size) do { } while (0) | |
554 | #define __dma_free_remap(cpu_addr, size) do { } while (0) | |
31ebf944 RK |
555 | |
556 | #endif /* CONFIG_MMU */ | |
557 | ||
c7909509 MS |
558 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
559 | struct page **ret_page) | |
ab6494f0 | 560 | { |
c7909509 MS |
561 | struct page *page; |
562 | page = __dma_alloc_buffer(dev, size, gfp); | |
563 | if (!page) | |
564 | return NULL; | |
565 | ||
566 | *ret_page = page; | |
567 | return page_address(page); | |
568 | } | |
569 | ||
570 | ||
571 | ||
572 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
573 | gfp_t gfp, pgprot_t prot, const void *caller) | |
574 | { | |
575 | u64 mask = get_coherent_dma_mask(dev); | |
04da5694 | 576 | struct page *page; |
31ebf944 | 577 | void *addr; |
ab6494f0 | 578 | |
c7909509 MS |
579 | #ifdef CONFIG_DMA_API_DEBUG |
580 | u64 limit = (mask + 1) & ~mask; | |
581 | if (limit && size >= limit) { | |
582 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
583 | size, mask); | |
584 | return NULL; | |
585 | } | |
586 | #endif | |
587 | ||
588 | if (!mask) | |
589 | return NULL; | |
590 | ||
591 | if (mask < 0xffffffffULL) | |
592 | gfp |= GFP_DMA; | |
593 | ||
ea2e7057 SB |
594 | /* |
595 | * Following is a work-around (a.k.a. hack) to prevent pages | |
596 | * with __GFP_COMP being passed to split_page() which cannot | |
597 | * handle them. The real problem is that this flag probably | |
598 | * should be 0 on ARM as it is not supported on this | |
599 | * platform; see CONFIG_HUGETLBFS. | |
600 | */ | |
601 | gfp &= ~(__GFP_COMP); | |
602 | ||
553ac788 | 603 | *handle = DMA_ERROR_CODE; |
04da5694 | 604 | size = PAGE_ALIGN(size); |
ab6494f0 | 605 | |
c7909509 MS |
606 | if (arch_is_coherent() || nommu()) |
607 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
e9da6e99 MS |
608 | else if (gfp & GFP_ATOMIC) |
609 | addr = __alloc_from_pool(size, &page); | |
f1ae98da | 610 | else if (!IS_ENABLED(CONFIG_CMA)) |
c7909509 | 611 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 612 | else |
c7909509 | 613 | addr = __alloc_from_contiguous(dev, size, prot, &page); |
695ae0af | 614 | |
31ebf944 | 615 | if (addr) |
9eedd963 | 616 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 617 | |
31ebf944 RK |
618 | return addr; |
619 | } | |
1da177e4 LT |
620 | |
621 | /* | |
622 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
623 | * virtual and bus address for that space. | |
624 | */ | |
f99d6034 MS |
625 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
626 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 627 | { |
f99d6034 | 628 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); |
1fe53268 DB |
629 | void *memory; |
630 | ||
631 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
632 | return memory; | |
633 | ||
f99d6034 | 634 | return __dma_alloc(dev, size, handle, gfp, prot, |
45cd5290 | 635 | __builtin_return_address(0)); |
1da177e4 | 636 | } |
1da177e4 LT |
637 | |
638 | /* | |
f99d6034 | 639 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 640 | */ |
f99d6034 MS |
641 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
642 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
643 | struct dma_attrs *attrs) | |
1da177e4 | 644 | { |
ab6494f0 CM |
645 | int ret = -ENXIO; |
646 | #ifdef CONFIG_MMU | |
50262a4b MS |
647 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
648 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 649 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
650 | unsigned long off = vma->vm_pgoff; |
651 | ||
f99d6034 MS |
652 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
653 | ||
47142f07 MS |
654 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
655 | return ret; | |
656 | ||
50262a4b MS |
657 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
658 | ret = remap_pfn_range(vma, vma->vm_start, | |
659 | pfn + off, | |
660 | vma->vm_end - vma->vm_start, | |
661 | vma->vm_page_prot); | |
662 | } | |
ab6494f0 | 663 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
664 | |
665 | return ret; | |
666 | } | |
667 | ||
1da177e4 | 668 | /* |
c7909509 | 669 | * Free a buffer as defined by the above mapping. |
1da177e4 | 670 | */ |
f99d6034 MS |
671 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
672 | dma_addr_t handle, struct dma_attrs *attrs) | |
1da177e4 | 673 | { |
c7909509 | 674 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 675 | |
1fe53268 DB |
676 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
677 | return; | |
678 | ||
3e82d012 RK |
679 | size = PAGE_ALIGN(size); |
680 | ||
c7909509 MS |
681 | if (arch_is_coherent() || nommu()) { |
682 | __dma_free_buffer(page, size); | |
d9e0d149 AK |
683 | } else if (__free_from_pool(cpu_addr, size)) { |
684 | return; | |
f1ae98da | 685 | } else if (!IS_ENABLED(CONFIG_CMA)) { |
695ae0af | 686 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
687 | __dma_free_buffer(page, size); |
688 | } else { | |
c7909509 MS |
689 | /* |
690 | * Non-atomic allocations cannot be freed with IRQs disabled | |
691 | */ | |
692 | WARN_ON(irqs_disabled()); | |
693 | __free_from_contiguous(dev, page, size); | |
694 | } | |
1da177e4 | 695 | } |
afd1a321 | 696 | |
dc2832e1 MS |
697 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
698 | void *cpu_addr, dma_addr_t handle, size_t size, | |
699 | struct dma_attrs *attrs) | |
700 | { | |
701 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
702 | int ret; | |
703 | ||
704 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
705 | if (unlikely(ret)) | |
706 | return ret; | |
707 | ||
708 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
709 | return 0; | |
710 | } | |
711 | ||
4ea0d737 | 712 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
713 | size_t size, enum dma_data_direction dir, |
714 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
715 | { |
716 | /* | |
717 | * A single sg entry may refer to multiple physically contiguous | |
718 | * pages. But we still need to process highmem pages individually. | |
719 | * If highmem is not configured then the bulk of this loop gets | |
720 | * optimized out. | |
721 | */ | |
722 | size_t left = size; | |
723 | do { | |
724 | size_t len = left; | |
93f1d629 RK |
725 | void *vaddr; |
726 | ||
727 | if (PageHighMem(page)) { | |
728 | if (len + offset > PAGE_SIZE) { | |
729 | if (offset >= PAGE_SIZE) { | |
730 | page += offset / PAGE_SIZE; | |
731 | offset %= PAGE_SIZE; | |
732 | } | |
733 | len = PAGE_SIZE - offset; | |
734 | } | |
735 | vaddr = kmap_high_get(page); | |
736 | if (vaddr) { | |
737 | vaddr += offset; | |
a9c9147e | 738 | op(vaddr, len, dir); |
93f1d629 | 739 | kunmap_high(page); |
7e5a69e8 | 740 | } else if (cache_is_vipt()) { |
39af22a7 NP |
741 | /* unmapped pages might still be cached */ |
742 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 743 | op(vaddr + offset, len, dir); |
39af22a7 | 744 | kunmap_atomic(vaddr); |
43377453 | 745 | } |
93f1d629 RK |
746 | } else { |
747 | vaddr = page_address(page) + offset; | |
a9c9147e | 748 | op(vaddr, len, dir); |
43377453 | 749 | } |
43377453 NP |
750 | offset = 0; |
751 | page++; | |
752 | left -= len; | |
753 | } while (left); | |
754 | } | |
4ea0d737 | 755 | |
51fde349 MS |
756 | /* |
757 | * Make an area consistent for devices. | |
758 | * Note: Drivers should NOT use this function directly, as it will break | |
759 | * platforms with CONFIG_DMABOUNCE. | |
760 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
761 | */ | |
762 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
763 | size_t size, enum dma_data_direction dir) |
764 | { | |
65af191a | 765 | unsigned long paddr; |
65af191a | 766 | |
a9c9147e | 767 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
768 | |
769 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
770 | if (dir == DMA_FROM_DEVICE) { |
771 | outer_inv_range(paddr, paddr + size); | |
772 | } else { | |
773 | outer_clean_range(paddr, paddr + size); | |
774 | } | |
775 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 776 | } |
4ea0d737 | 777 | |
51fde349 | 778 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
779 | size_t size, enum dma_data_direction dir) |
780 | { | |
2ffe2da3 RK |
781 | unsigned long paddr = page_to_phys(page) + off; |
782 | ||
783 | /* FIXME: non-speculating: not required */ | |
784 | /* don't bother invalidating if DMA to device */ | |
785 | if (dir != DMA_TO_DEVICE) | |
786 | outer_inv_range(paddr, paddr + size); | |
787 | ||
a9c9147e | 788 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
789 | |
790 | /* | |
791 | * Mark the D-cache clean for this page to avoid extra flushing. | |
792 | */ | |
793 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
794 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 | 795 | } |
43377453 | 796 | |
afd1a321 | 797 | /** |
2a550e73 | 798 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
799 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
800 | * @sg: list of buffers | |
801 | * @nents: number of buffers to map | |
802 | * @dir: DMA transfer direction | |
803 | * | |
804 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
805 | * This is the scatter-gather version of the dma_map_single interface. | |
806 | * Here the scatter gather list elements are each tagged with the | |
807 | * appropriate dma address and length. They are obtained via | |
808 | * sg_dma_{address,length}. | |
809 | * | |
810 | * Device ownership issues as mentioned for dma_map_single are the same | |
811 | * here. | |
812 | */ | |
2dc6a016 MS |
813 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
814 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 815 | { |
2a550e73 | 816 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 817 | struct scatterlist *s; |
01135d92 | 818 | int i, j; |
afd1a321 RK |
819 | |
820 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
821 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
822 | s->dma_length = s->length; | |
823 | #endif | |
2a550e73 MS |
824 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
825 | s->length, dir, attrs); | |
01135d92 RK |
826 | if (dma_mapping_error(dev, s->dma_address)) |
827 | goto bad_mapping; | |
afd1a321 | 828 | } |
afd1a321 | 829 | return nents; |
01135d92 RK |
830 | |
831 | bad_mapping: | |
832 | for_each_sg(sg, s, i, j) | |
2a550e73 | 833 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 834 | return 0; |
afd1a321 | 835 | } |
afd1a321 RK |
836 | |
837 | /** | |
2a550e73 | 838 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
839 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
840 | * @sg: list of buffers | |
0adfca6f | 841 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
842 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
843 | * | |
844 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
845 | * rules concerning calls here are the same as for dma_unmap_single(). | |
846 | */ | |
2dc6a016 MS |
847 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
848 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 849 | { |
2a550e73 | 850 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 851 | struct scatterlist *s; |
01135d92 | 852 | |
01135d92 | 853 | int i; |
24056f52 | 854 | |
01135d92 | 855 | for_each_sg(sg, s, nents, i) |
2a550e73 | 856 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 857 | } |
afd1a321 RK |
858 | |
859 | /** | |
2a550e73 | 860 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
861 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
862 | * @sg: list of buffers | |
863 | * @nents: number of buffers to map (returned from dma_map_sg) | |
864 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
865 | */ | |
2dc6a016 | 866 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
867 | int nents, enum dma_data_direction dir) |
868 | { | |
2a550e73 | 869 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
870 | struct scatterlist *s; |
871 | int i; | |
872 | ||
2a550e73 MS |
873 | for_each_sg(sg, s, nents, i) |
874 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
875 | dir); | |
afd1a321 | 876 | } |
afd1a321 RK |
877 | |
878 | /** | |
2a550e73 | 879 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
880 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
881 | * @sg: list of buffers | |
882 | * @nents: number of buffers to map (returned from dma_map_sg) | |
883 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
884 | */ | |
2dc6a016 | 885 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
886 | int nents, enum dma_data_direction dir) |
887 | { | |
2a550e73 | 888 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
889 | struct scatterlist *s; |
890 | int i; | |
891 | ||
2a550e73 MS |
892 | for_each_sg(sg, s, nents, i) |
893 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
894 | dir); | |
afd1a321 | 895 | } |
24056f52 | 896 | |
022ae537 RK |
897 | /* |
898 | * Return whether the given device DMA address mask can be supported | |
899 | * properly. For example, if your device can only drive the low 24-bits | |
900 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
901 | * to this function. | |
902 | */ | |
903 | int dma_supported(struct device *dev, u64 mask) | |
904 | { | |
905 | if (mask < (u64)arm_dma_limit) | |
906 | return 0; | |
907 | return 1; | |
908 | } | |
909 | EXPORT_SYMBOL(dma_supported); | |
910 | ||
2dc6a016 | 911 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
912 | { |
913 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
914 | return -EIO; | |
915 | ||
022ae537 | 916 | *dev->dma_mask = dma_mask; |
022ae537 RK |
917 | |
918 | return 0; | |
919 | } | |
022ae537 | 920 | |
24056f52 RK |
921 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
922 | ||
923 | static int __init dma_debug_do_init(void) | |
924 | { | |
925 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
926 | return 0; | |
927 | } | |
928 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
929 | |
930 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
931 | ||
932 | /* IOMMU */ | |
933 | ||
934 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, | |
935 | size_t size) | |
936 | { | |
937 | unsigned int order = get_order(size); | |
938 | unsigned int align = 0; | |
939 | unsigned int count, start; | |
940 | unsigned long flags; | |
941 | ||
942 | count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) + | |
943 | (1 << mapping->order) - 1) >> mapping->order; | |
944 | ||
945 | if (order > mapping->order) | |
946 | align = (1 << (order - mapping->order)) - 1; | |
947 | ||
948 | spin_lock_irqsave(&mapping->lock, flags); | |
949 | start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0, | |
950 | count, align); | |
951 | if (start > mapping->bits) { | |
952 | spin_unlock_irqrestore(&mapping->lock, flags); | |
953 | return DMA_ERROR_CODE; | |
954 | } | |
955 | ||
956 | bitmap_set(mapping->bitmap, start, count); | |
957 | spin_unlock_irqrestore(&mapping->lock, flags); | |
958 | ||
959 | return mapping->base + (start << (mapping->order + PAGE_SHIFT)); | |
960 | } | |
961 | ||
962 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
963 | dma_addr_t addr, size_t size) | |
964 | { | |
965 | unsigned int start = (addr - mapping->base) >> | |
966 | (mapping->order + PAGE_SHIFT); | |
967 | unsigned int count = ((size >> PAGE_SHIFT) + | |
968 | (1 << mapping->order) - 1) >> mapping->order; | |
969 | unsigned long flags; | |
970 | ||
971 | spin_lock_irqsave(&mapping->lock, flags); | |
972 | bitmap_clear(mapping->bitmap, start, count); | |
973 | spin_unlock_irqrestore(&mapping->lock, flags); | |
974 | } | |
975 | ||
976 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
977 | { | |
978 | struct page **pages; | |
979 | int count = size >> PAGE_SHIFT; | |
980 | int array_size = count * sizeof(struct page *); | |
981 | int i = 0; | |
982 | ||
983 | if (array_size <= PAGE_SIZE) | |
984 | pages = kzalloc(array_size, gfp); | |
985 | else | |
986 | pages = vzalloc(array_size); | |
987 | if (!pages) | |
988 | return NULL; | |
989 | ||
990 | while (count) { | |
593f4735 | 991 | int j, order = __fls(count); |
4ce63fcd MS |
992 | |
993 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, order); | |
994 | while (!pages[i] && order) | |
995 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order); | |
996 | if (!pages[i]) | |
997 | goto error; | |
998 | ||
999 | if (order) | |
1000 | split_page(pages[i], order); | |
1001 | j = 1 << order; | |
1002 | while (--j) | |
1003 | pages[i + j] = pages[i] + j; | |
1004 | ||
1005 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1006 | i += 1 << order; | |
1007 | count -= 1 << order; | |
1008 | } | |
1009 | ||
1010 | return pages; | |
1011 | error: | |
9fa8af91 | 1012 | while (i--) |
4ce63fcd MS |
1013 | if (pages[i]) |
1014 | __free_pages(pages[i], 0); | |
46c87852 | 1015 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1016 | kfree(pages); |
1017 | else | |
1018 | vfree(pages); | |
1019 | return NULL; | |
1020 | } | |
1021 | ||
1022 | static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size) | |
1023 | { | |
1024 | int count = size >> PAGE_SHIFT; | |
1025 | int array_size = count * sizeof(struct page *); | |
1026 | int i; | |
1027 | for (i = 0; i < count; i++) | |
1028 | if (pages[i]) | |
1029 | __free_pages(pages[i], 0); | |
46c87852 | 1030 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1031 | kfree(pages); |
1032 | else | |
1033 | vfree(pages); | |
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | /* | |
1038 | * Create a CPU mapping for a specified pages | |
1039 | */ | |
1040 | static void * | |
e9da6e99 MS |
1041 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1042 | const void *caller) | |
4ce63fcd | 1043 | { |
e9da6e99 MS |
1044 | unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1045 | struct vm_struct *area; | |
1046 | unsigned long p; | |
4ce63fcd | 1047 | |
e9da6e99 MS |
1048 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, |
1049 | caller); | |
1050 | if (!area) | |
4ce63fcd | 1051 | return NULL; |
4ce63fcd | 1052 | |
e9da6e99 MS |
1053 | area->pages = pages; |
1054 | area->nr_pages = nr_pages; | |
1055 | p = (unsigned long)area->addr; | |
4ce63fcd | 1056 | |
e9da6e99 MS |
1057 | for (i = 0; i < nr_pages; i++) { |
1058 | phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i])); | |
1059 | if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot)) | |
1060 | goto err; | |
1061 | p += PAGE_SIZE; | |
4ce63fcd | 1062 | } |
e9da6e99 MS |
1063 | return area->addr; |
1064 | err: | |
1065 | unmap_kernel_range((unsigned long)area->addr, size); | |
1066 | vunmap(area->addr); | |
4ce63fcd MS |
1067 | return NULL; |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * Create a mapping in device IO address space for specified pages | |
1072 | */ | |
1073 | static dma_addr_t | |
1074 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1075 | { | |
1076 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1077 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1078 | dma_addr_t dma_addr, iova; | |
1079 | int i, ret = DMA_ERROR_CODE; | |
1080 | ||
1081 | dma_addr = __alloc_iova(mapping, size); | |
1082 | if (dma_addr == DMA_ERROR_CODE) | |
1083 | return dma_addr; | |
1084 | ||
1085 | iova = dma_addr; | |
1086 | for (i = 0; i < count; ) { | |
1087 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1088 | phys_addr_t phys = page_to_phys(pages[i]); | |
1089 | unsigned int len, j; | |
1090 | ||
1091 | for (j = i + 1; j < count; j++, next_pfn++) | |
1092 | if (page_to_pfn(pages[j]) != next_pfn) | |
1093 | break; | |
1094 | ||
1095 | len = (j - i) << PAGE_SHIFT; | |
1096 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1097 | if (ret < 0) | |
1098 | goto fail; | |
1099 | iova += len; | |
1100 | i = j; | |
1101 | } | |
1102 | return dma_addr; | |
1103 | fail: | |
1104 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1105 | __free_iova(mapping, dma_addr, size); | |
1106 | return DMA_ERROR_CODE; | |
1107 | } | |
1108 | ||
1109 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1110 | { | |
1111 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1112 | ||
1113 | /* | |
1114 | * add optional in-page offset from iova to size and align | |
1115 | * result to page size | |
1116 | */ | |
1117 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1118 | iova &= PAGE_MASK; | |
1119 | ||
1120 | iommu_unmap(mapping->domain, iova, size); | |
1121 | __free_iova(mapping, iova, size); | |
1122 | return 0; | |
1123 | } | |
1124 | ||
955c757e | 1125 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1126 | { |
1127 | struct vm_struct *area; | |
1128 | ||
955c757e MS |
1129 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1130 | return cpu_addr; | |
1131 | ||
e9da6e99 MS |
1132 | area = find_vm_area(cpu_addr); |
1133 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1134 | return area->pages; | |
1135 | return NULL; | |
1136 | } | |
1137 | ||
4ce63fcd MS |
1138 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1139 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1140 | { | |
1141 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); | |
1142 | struct page **pages; | |
1143 | void *addr = NULL; | |
1144 | ||
1145 | *handle = DMA_ERROR_CODE; | |
1146 | size = PAGE_ALIGN(size); | |
1147 | ||
1148 | pages = __iommu_alloc_buffer(dev, size, gfp); | |
1149 | if (!pages) | |
1150 | return NULL; | |
1151 | ||
1152 | *handle = __iommu_create_mapping(dev, pages, size); | |
1153 | if (*handle == DMA_ERROR_CODE) | |
1154 | goto err_buffer; | |
1155 | ||
955c757e MS |
1156 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1157 | return pages; | |
1158 | ||
e9da6e99 MS |
1159 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1160 | __builtin_return_address(0)); | |
4ce63fcd MS |
1161 | if (!addr) |
1162 | goto err_mapping; | |
1163 | ||
1164 | return addr; | |
1165 | ||
1166 | err_mapping: | |
1167 | __iommu_remove_mapping(dev, *handle, size); | |
1168 | err_buffer: | |
1169 | __iommu_free_buffer(dev, pages, size); | |
1170 | return NULL; | |
1171 | } | |
1172 | ||
1173 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1174 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1175 | struct dma_attrs *attrs) | |
1176 | { | |
e9da6e99 MS |
1177 | unsigned long uaddr = vma->vm_start; |
1178 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1179 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1180 | |
1181 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1182 | |
e9da6e99 MS |
1183 | if (!pages) |
1184 | return -ENXIO; | |
4ce63fcd | 1185 | |
e9da6e99 MS |
1186 | do { |
1187 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1188 | if (ret) { | |
1189 | pr_err("Remapping memory failed: %d\n", ret); | |
1190 | return ret; | |
1191 | } | |
1192 | uaddr += PAGE_SIZE; | |
1193 | usize -= PAGE_SIZE; | |
1194 | } while (usize > 0); | |
4ce63fcd | 1195 | |
4ce63fcd MS |
1196 | return 0; |
1197 | } | |
1198 | ||
1199 | /* | |
1200 | * free a page as defined by the above mapping. | |
1201 | * Must not be called with IRQs disabled. | |
1202 | */ | |
1203 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1204 | dma_addr_t handle, struct dma_attrs *attrs) | |
1205 | { | |
955c757e | 1206 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1207 | size = PAGE_ALIGN(size); |
1208 | ||
e9da6e99 MS |
1209 | if (!pages) { |
1210 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
1211 | return; | |
4ce63fcd | 1212 | } |
e9da6e99 | 1213 | |
955c757e MS |
1214 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
1215 | unmap_kernel_range((unsigned long)cpu_addr, size); | |
1216 | vunmap(cpu_addr); | |
1217 | } | |
e9da6e99 MS |
1218 | |
1219 | __iommu_remove_mapping(dev, handle, size); | |
1220 | __iommu_free_buffer(dev, pages, size); | |
4ce63fcd MS |
1221 | } |
1222 | ||
dc2832e1 MS |
1223 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1224 | void *cpu_addr, dma_addr_t dma_addr, | |
1225 | size_t size, struct dma_attrs *attrs) | |
1226 | { | |
1227 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1228 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1229 | ||
1230 | if (!pages) | |
1231 | return -ENXIO; | |
1232 | ||
1233 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1234 | GFP_KERNEL); | |
4ce63fcd MS |
1235 | } |
1236 | ||
1237 | /* | |
1238 | * Map a part of the scatter-gather list into contiguous io address space | |
1239 | */ | |
1240 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1241 | size_t size, dma_addr_t *handle, | |
97ef952a | 1242 | enum dma_data_direction dir, struct dma_attrs *attrs) |
4ce63fcd MS |
1243 | { |
1244 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1245 | dma_addr_t iova, iova_base; | |
1246 | int ret = 0; | |
1247 | unsigned int count; | |
1248 | struct scatterlist *s; | |
1249 | ||
1250 | size = PAGE_ALIGN(size); | |
1251 | *handle = DMA_ERROR_CODE; | |
1252 | ||
1253 | iova_base = iova = __alloc_iova(mapping, size); | |
1254 | if (iova == DMA_ERROR_CODE) | |
1255 | return -ENOMEM; | |
1256 | ||
1257 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1258 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1259 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1260 | ||
97ef952a MS |
1261 | if (!arch_is_coherent() && |
1262 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1263 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1264 | ||
1265 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1266 | if (ret < 0) | |
1267 | goto fail; | |
1268 | count += len >> PAGE_SHIFT; | |
1269 | iova += len; | |
1270 | } | |
1271 | *handle = iova_base; | |
1272 | ||
1273 | return 0; | |
1274 | fail: | |
1275 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1276 | __free_iova(mapping, iova_base, size); | |
1277 | return ret; | |
1278 | } | |
1279 | ||
1280 | /** | |
1281 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1282 | * @dev: valid struct device pointer | |
1283 | * @sg: list of buffers | |
1284 | * @nents: number of buffers to map | |
1285 | * @dir: DMA transfer direction | |
1286 | * | |
1287 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1288 | * The scatter gather list elements are merged together (if possible) and | |
1289 | * tagged with the appropriate dma address and length. They are obtained via | |
1290 | * sg_dma_{address,length}. | |
1291 | */ | |
1292 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1293 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1294 | { | |
1295 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1296 | int i, count = 0; | |
1297 | unsigned int offset = s->offset; | |
1298 | unsigned int size = s->offset + s->length; | |
1299 | unsigned int max = dma_get_max_seg_size(dev); | |
1300 | ||
1301 | for (i = 1; i < nents; i++) { | |
1302 | s = sg_next(s); | |
1303 | ||
1304 | s->dma_address = DMA_ERROR_CODE; | |
1305 | s->dma_length = 0; | |
1306 | ||
1307 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1308 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
97ef952a | 1309 | dir, attrs) < 0) |
4ce63fcd MS |
1310 | goto bad_mapping; |
1311 | ||
1312 | dma->dma_address += offset; | |
1313 | dma->dma_length = size - offset; | |
1314 | ||
1315 | size = offset = s->offset; | |
1316 | start = s; | |
1317 | dma = sg_next(dma); | |
1318 | count += 1; | |
1319 | } | |
1320 | size += s->length; | |
1321 | } | |
97ef952a | 1322 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0) |
4ce63fcd MS |
1323 | goto bad_mapping; |
1324 | ||
1325 | dma->dma_address += offset; | |
1326 | dma->dma_length = size - offset; | |
1327 | ||
1328 | return count+1; | |
1329 | ||
1330 | bad_mapping: | |
1331 | for_each_sg(sg, s, count, i) | |
1332 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1333 | return 0; | |
1334 | } | |
1335 | ||
1336 | /** | |
1337 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1338 | * @dev: valid struct device pointer | |
1339 | * @sg: list of buffers | |
1340 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1341 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1342 | * | |
1343 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1344 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1345 | */ | |
1346 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1347 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1348 | { | |
1349 | struct scatterlist *s; | |
1350 | int i; | |
1351 | ||
1352 | for_each_sg(sg, s, nents, i) { | |
1353 | if (sg_dma_len(s)) | |
1354 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1355 | sg_dma_len(s)); | |
97ef952a MS |
1356 | if (!arch_is_coherent() && |
1357 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1358 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1359 | s->length, dir); | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | /** | |
1364 | * arm_iommu_sync_sg_for_cpu | |
1365 | * @dev: valid struct device pointer | |
1366 | * @sg: list of buffers | |
1367 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1368 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1369 | */ | |
1370 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1371 | int nents, enum dma_data_direction dir) | |
1372 | { | |
1373 | struct scatterlist *s; | |
1374 | int i; | |
1375 | ||
1376 | for_each_sg(sg, s, nents, i) | |
1377 | if (!arch_is_coherent()) | |
1378 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); | |
1379 | ||
1380 | } | |
1381 | ||
1382 | /** | |
1383 | * arm_iommu_sync_sg_for_device | |
1384 | * @dev: valid struct device pointer | |
1385 | * @sg: list of buffers | |
1386 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1387 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1388 | */ | |
1389 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1390 | int nents, enum dma_data_direction dir) | |
1391 | { | |
1392 | struct scatterlist *s; | |
1393 | int i; | |
1394 | ||
1395 | for_each_sg(sg, s, nents, i) | |
1396 | if (!arch_is_coherent()) | |
1397 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1398 | } | |
1399 | ||
1400 | ||
1401 | /** | |
1402 | * arm_iommu_map_page | |
1403 | * @dev: valid struct device pointer | |
1404 | * @page: page that buffer resides in | |
1405 | * @offset: offset into page for start of buffer | |
1406 | * @size: size of buffer to map | |
1407 | * @dir: DMA transfer direction | |
1408 | * | |
1409 | * IOMMU aware version of arm_dma_map_page() | |
1410 | */ | |
1411 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1412 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1413 | struct dma_attrs *attrs) | |
1414 | { | |
1415 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1416 | dma_addr_t dma_addr; | |
1417 | int ret, len = PAGE_ALIGN(size + offset); | |
1418 | ||
97ef952a | 1419 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1420 | __dma_page_cpu_to_dev(page, offset, size, dir); |
1421 | ||
1422 | dma_addr = __alloc_iova(mapping, len); | |
1423 | if (dma_addr == DMA_ERROR_CODE) | |
1424 | return dma_addr; | |
1425 | ||
1426 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0); | |
1427 | if (ret < 0) | |
1428 | goto fail; | |
1429 | ||
1430 | return dma_addr + offset; | |
1431 | fail: | |
1432 | __free_iova(mapping, dma_addr, len); | |
1433 | return DMA_ERROR_CODE; | |
1434 | } | |
1435 | ||
1436 | /** | |
1437 | * arm_iommu_unmap_page | |
1438 | * @dev: valid struct device pointer | |
1439 | * @handle: DMA address of buffer | |
1440 | * @size: size of buffer (same as passed to dma_map_page) | |
1441 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1442 | * | |
1443 | * IOMMU aware version of arm_dma_unmap_page() | |
1444 | */ | |
1445 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1446 | size_t size, enum dma_data_direction dir, | |
1447 | struct dma_attrs *attrs) | |
1448 | { | |
1449 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1450 | dma_addr_t iova = handle & PAGE_MASK; | |
1451 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1452 | int offset = handle & ~PAGE_MASK; | |
1453 | int len = PAGE_ALIGN(size + offset); | |
1454 | ||
1455 | if (!iova) | |
1456 | return; | |
1457 | ||
97ef952a | 1458 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1459 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1460 | ||
1461 | iommu_unmap(mapping->domain, iova, len); | |
1462 | __free_iova(mapping, iova, len); | |
1463 | } | |
1464 | ||
1465 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1466 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1467 | { | |
1468 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1469 | dma_addr_t iova = handle & PAGE_MASK; | |
1470 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1471 | unsigned int offset = handle & ~PAGE_MASK; | |
1472 | ||
1473 | if (!iova) | |
1474 | return; | |
1475 | ||
1476 | if (!arch_is_coherent()) | |
1477 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1478 | } | |
1479 | ||
1480 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1481 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1482 | { | |
1483 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1484 | dma_addr_t iova = handle & PAGE_MASK; | |
1485 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1486 | unsigned int offset = handle & ~PAGE_MASK; | |
1487 | ||
1488 | if (!iova) | |
1489 | return; | |
1490 | ||
1491 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1492 | } | |
1493 | ||
1494 | struct dma_map_ops iommu_ops = { | |
1495 | .alloc = arm_iommu_alloc_attrs, | |
1496 | .free = arm_iommu_free_attrs, | |
1497 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1498 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1499 | |
1500 | .map_page = arm_iommu_map_page, | |
1501 | .unmap_page = arm_iommu_unmap_page, | |
1502 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1503 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1504 | ||
1505 | .map_sg = arm_iommu_map_sg, | |
1506 | .unmap_sg = arm_iommu_unmap_sg, | |
1507 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1508 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
1509 | }; | |
1510 | ||
1511 | /** | |
1512 | * arm_iommu_create_mapping | |
1513 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1514 | * @base: start address of the valid IO address space | |
1515 | * @size: size of the valid IO address space | |
1516 | * @order: accuracy of the IO addresses allocations | |
1517 | * | |
1518 | * Creates a mapping structure which holds information about used/unused | |
1519 | * IO address ranges, which is required to perform memory allocation and | |
1520 | * mapping with IOMMU aware functions. | |
1521 | * | |
1522 | * The client device need to be attached to the mapping with | |
1523 | * arm_iommu_attach_device function. | |
1524 | */ | |
1525 | struct dma_iommu_mapping * | |
1526 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size, | |
1527 | int order) | |
1528 | { | |
1529 | unsigned int count = size >> (PAGE_SHIFT + order); | |
1530 | unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long); | |
1531 | struct dma_iommu_mapping *mapping; | |
1532 | int err = -ENOMEM; | |
1533 | ||
1534 | if (!count) | |
1535 | return ERR_PTR(-EINVAL); | |
1536 | ||
1537 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); | |
1538 | if (!mapping) | |
1539 | goto err; | |
1540 | ||
1541 | mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
1542 | if (!mapping->bitmap) | |
1543 | goto err2; | |
1544 | ||
1545 | mapping->base = base; | |
1546 | mapping->bits = BITS_PER_BYTE * bitmap_size; | |
1547 | mapping->order = order; | |
1548 | spin_lock_init(&mapping->lock); | |
1549 | ||
1550 | mapping->domain = iommu_domain_alloc(bus); | |
1551 | if (!mapping->domain) | |
1552 | goto err3; | |
1553 | ||
1554 | kref_init(&mapping->kref); | |
1555 | return mapping; | |
1556 | err3: | |
1557 | kfree(mapping->bitmap); | |
1558 | err2: | |
1559 | kfree(mapping); | |
1560 | err: | |
1561 | return ERR_PTR(err); | |
1562 | } | |
1563 | ||
1564 | static void release_iommu_mapping(struct kref *kref) | |
1565 | { | |
1566 | struct dma_iommu_mapping *mapping = | |
1567 | container_of(kref, struct dma_iommu_mapping, kref); | |
1568 | ||
1569 | iommu_domain_free(mapping->domain); | |
1570 | kfree(mapping->bitmap); | |
1571 | kfree(mapping); | |
1572 | } | |
1573 | ||
1574 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) | |
1575 | { | |
1576 | if (mapping) | |
1577 | kref_put(&mapping->kref, release_iommu_mapping); | |
1578 | } | |
1579 | ||
1580 | /** | |
1581 | * arm_iommu_attach_device | |
1582 | * @dev: valid struct device pointer | |
1583 | * @mapping: io address space mapping structure (returned from | |
1584 | * arm_iommu_create_mapping) | |
1585 | * | |
1586 | * Attaches specified io address space mapping to the provided device, | |
1587 | * this replaces the dma operations (dma_map_ops pointer) with the | |
1588 | * IOMMU aware version. More than one client might be attached to | |
1589 | * the same io address space mapping. | |
1590 | */ | |
1591 | int arm_iommu_attach_device(struct device *dev, | |
1592 | struct dma_iommu_mapping *mapping) | |
1593 | { | |
1594 | int err; | |
1595 | ||
1596 | err = iommu_attach_device(mapping->domain, dev); | |
1597 | if (err) | |
1598 | return err; | |
1599 | ||
1600 | kref_get(&mapping->kref); | |
1601 | dev->archdata.mapping = mapping; | |
1602 | set_dma_ops(dev, &iommu_ops); | |
1603 | ||
1604 | pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
1605 | return 0; | |
1606 | } | |
1607 | ||
1608 | #endif |