Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | ||
23759dc6 | 21 | #include <asm/memory.h> |
43377453 | 22 | #include <asm/highmem.h> |
1da177e4 | 23 | #include <asm/cacheflush.h> |
1da177e4 | 24 | #include <asm/tlbflush.h> |
37134cd5 KH |
25 | #include <asm/sizes.h> |
26 | ||
27 | /* Sanity check size */ | |
28 | #if (CONSISTENT_DMA_SIZE % SZ_2M) | |
29 | #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" | |
30 | #endif | |
1da177e4 | 31 | |
1da177e4 | 32 | #define CONSISTENT_END (0xffe00000) |
37134cd5 KH |
33 | #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) |
34 | ||
1da177e4 | 35 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) |
37134cd5 KH |
36 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) |
37 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) | |
38 | ||
ab6494f0 CM |
39 | static u64 get_coherent_dma_mask(struct device *dev) |
40 | { | |
41 | u64 mask = ISA_DMA_THRESHOLD; | |
42 | ||
43 | if (dev) { | |
44 | mask = dev->coherent_dma_mask; | |
45 | ||
46 | /* | |
47 | * Sanity check the DMA mask - it must be non-zero, and | |
48 | * must be able to be satisfied by a DMA allocation. | |
49 | */ | |
50 | if (mask == 0) { | |
51 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
52 | return 0; | |
53 | } | |
54 | ||
55 | if ((~mask) & ISA_DMA_THRESHOLD) { | |
56 | dev_warn(dev, "coherent DMA mask %#llx is smaller " | |
57 | "than system GFP_DMA mask %#llx\n", | |
58 | mask, (unsigned long long)ISA_DMA_THRESHOLD); | |
59 | return 0; | |
60 | } | |
61 | } | |
1da177e4 | 62 | |
ab6494f0 CM |
63 | return mask; |
64 | } | |
65 | ||
7a9a32a9 RK |
66 | /* |
67 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
68 | * specified gfp mask. Note that 'size' must be page aligned. | |
69 | */ | |
70 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
71 | { | |
72 | unsigned long order = get_order(size); | |
73 | struct page *page, *p, *e; | |
74 | void *ptr; | |
75 | u64 mask = get_coherent_dma_mask(dev); | |
76 | ||
77 | #ifdef CONFIG_DMA_API_DEBUG | |
78 | u64 limit = (mask + 1) & ~mask; | |
79 | if (limit && size >= limit) { | |
80 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
81 | size, mask); | |
82 | return NULL; | |
83 | } | |
84 | #endif | |
85 | ||
86 | if (!mask) | |
87 | return NULL; | |
88 | ||
89 | if (mask < 0xffffffffULL) | |
90 | gfp |= GFP_DMA; | |
91 | ||
92 | page = alloc_pages(gfp, order); | |
93 | if (!page) | |
94 | return NULL; | |
95 | ||
96 | /* | |
97 | * Now split the huge page and free the excess pages | |
98 | */ | |
99 | split_page(page, order); | |
100 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
101 | __free_page(p); | |
102 | ||
103 | /* | |
104 | * Ensure that the allocated pages are zeroed, and that any data | |
105 | * lurking in the kernel direct-mapped region is invalidated. | |
106 | */ | |
107 | ptr = page_address(page); | |
108 | memset(ptr, 0, size); | |
109 | dmac_flush_range(ptr, ptr + size); | |
110 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
111 | ||
112 | return page; | |
113 | } | |
114 | ||
115 | /* | |
116 | * Free a DMA buffer. 'size' must be page aligned. | |
117 | */ | |
118 | static void __dma_free_buffer(struct page *page, size_t size) | |
119 | { | |
120 | struct page *e = page + (size >> PAGE_SHIFT); | |
121 | ||
122 | while (page < e) { | |
123 | __free_page(page); | |
124 | page++; | |
125 | } | |
126 | } | |
127 | ||
ab6494f0 | 128 | #ifdef CONFIG_MMU |
1da177e4 | 129 | /* |
37134cd5 | 130 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 131 | */ |
37134cd5 | 132 | static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; |
1da177e4 | 133 | |
13ccf3ad | 134 | #include "vmregion.h" |
1da177e4 | 135 | |
13ccf3ad RK |
136 | static struct arm_vmregion_head consistent_head = { |
137 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 LT |
138 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
139 | .vm_start = CONSISTENT_BASE, | |
140 | .vm_end = CONSISTENT_END, | |
141 | }; | |
142 | ||
1da177e4 LT |
143 | #ifdef CONFIG_HUGETLB_PAGE |
144 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
145 | #endif | |
146 | ||
147 | static void * | |
f9e3214a | 148 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, |
1da177e4 LT |
149 | pgprot_t prot) |
150 | { | |
151 | struct page *page; | |
13ccf3ad | 152 | struct arm_vmregion *c; |
1da177e4 | 153 | |
37134cd5 | 154 | if (!consistent_pte[0]) { |
1da177e4 LT |
155 | printk(KERN_ERR "%s: not initialised\n", __func__); |
156 | dump_stack(); | |
157 | return NULL; | |
158 | } | |
159 | ||
1da177e4 | 160 | size = PAGE_ALIGN(size); |
1da177e4 | 161 | |
7a9a32a9 | 162 | page = __dma_alloc_buffer(dev, size, gfp); |
1da177e4 LT |
163 | if (!page) |
164 | goto no_page; | |
165 | ||
1da177e4 LT |
166 | /* |
167 | * Allocate a virtual address in the consistent mapping region. | |
168 | */ | |
13ccf3ad | 169 | c = arm_vmregion_alloc(&consistent_head, size, |
1da177e4 LT |
170 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); |
171 | if (c) { | |
37134cd5 | 172 | pte_t *pte; |
37134cd5 KH |
173 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
174 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 175 | |
37134cd5 | 176 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
177 | c->vm_pages = page; |
178 | ||
179 | /* | |
180 | * Set the "dma handle" | |
181 | */ | |
182 | *handle = page_to_dma(dev, page); | |
183 | ||
184 | do { | |
185 | BUG_ON(!pte_none(*pte)); | |
186 | ||
1da177e4 LT |
187 | /* |
188 | * x86 does not mark the pages reserved... | |
189 | */ | |
190 | SetPageReserved(page); | |
ad1ae2fe | 191 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
192 | page++; |
193 | pte++; | |
37134cd5 KH |
194 | off++; |
195 | if (off >= PTRS_PER_PTE) { | |
196 | off = 0; | |
197 | pte = consistent_pte[++idx]; | |
198 | } | |
1da177e4 LT |
199 | } while (size -= PAGE_SIZE); |
200 | ||
1da177e4 LT |
201 | return (void *)c->vm_start; |
202 | } | |
203 | ||
204 | if (page) | |
7a9a32a9 | 205 | __dma_free_buffer(page, size); |
1da177e4 LT |
206 | no_page: |
207 | *handle = ~0; | |
208 | return NULL; | |
209 | } | |
695ae0af RK |
210 | |
211 | static void __dma_free_remap(void *cpu_addr, size_t size) | |
212 | { | |
213 | struct arm_vmregion *c; | |
214 | unsigned long addr; | |
215 | pte_t *ptep; | |
216 | int idx; | |
217 | u32 off; | |
218 | ||
219 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); | |
220 | if (!c) { | |
221 | printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n", | |
222 | __func__, cpu_addr); | |
223 | dump_stack(); | |
224 | return; | |
225 | } | |
226 | ||
227 | if ((c->vm_end - c->vm_start) != size) { | |
228 | printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n", | |
229 | __func__, c->vm_end - c->vm_start, size); | |
230 | dump_stack(); | |
231 | size = c->vm_end - c->vm_start; | |
232 | } | |
233 | ||
234 | idx = CONSISTENT_PTE_INDEX(c->vm_start); | |
235 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
236 | ptep = consistent_pte[idx] + off; | |
237 | addr = c->vm_start; | |
238 | do { | |
239 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
240 | unsigned long pfn; | |
241 | ||
242 | ptep++; | |
243 | addr += PAGE_SIZE; | |
244 | off++; | |
245 | if (off >= PTRS_PER_PTE) { | |
246 | off = 0; | |
247 | ptep = consistent_pte[++idx]; | |
248 | } | |
249 | ||
250 | if (!pte_none(pte) && pte_present(pte)) { | |
251 | pfn = pte_pfn(pte); | |
252 | ||
253 | if (pfn_valid(pfn)) { | |
254 | struct page *page = pfn_to_page(pfn); | |
255 | ||
256 | /* | |
257 | * x86 does not mark the pages reserved... | |
258 | */ | |
259 | ClearPageReserved(page); | |
260 | continue; | |
261 | } | |
262 | } | |
263 | printk(KERN_CRIT "%s: bad page in kernel page table\n", | |
264 | __func__); | |
265 | } while (size -= PAGE_SIZE); | |
266 | ||
267 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
268 | ||
269 | arm_vmregion_free(&consistent_head, c); | |
270 | } | |
271 | ||
ab6494f0 | 272 | #else /* !CONFIG_MMU */ |
695ae0af | 273 | |
ab6494f0 CM |
274 | static void * |
275 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |
276 | pgprot_t prot) | |
277 | { | |
04da5694 | 278 | struct page *page; |
ab6494f0 | 279 | |
04da5694 RK |
280 | *handle = ~0; |
281 | size = PAGE_ALIGN(size); | |
ab6494f0 | 282 | |
04da5694 RK |
283 | page = __dma_alloc_buffer(dev, size, gfp); |
284 | if (!page) | |
285 | return NULL; | |
ab6494f0 | 286 | |
04da5694 RK |
287 | *handle = page_to_dma(dev, page); |
288 | return page_address(page); | |
ab6494f0 | 289 | } |
695ae0af RK |
290 | |
291 | #define __dma_free_remap(addr, size) do { } while (0) | |
292 | ||
ab6494f0 | 293 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
294 | |
295 | /* | |
296 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
297 | * virtual and bus address for that space. | |
298 | */ | |
299 | void * | |
f9e3214a | 300 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 | 301 | { |
1fe53268 DB |
302 | void *memory; |
303 | ||
304 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
305 | return memory; | |
306 | ||
23759dc6 | 307 | if (arch_is_coherent()) { |
3e82d012 | 308 | struct page *page; |
23759dc6 | 309 | |
3e82d012 RK |
310 | page = __dma_alloc_buffer(dev, PAGE_ALIGN(size), gfp); |
311 | if (!page) { | |
312 | *handle = ~0; | |
23759dc6 | 313 | return NULL; |
3e82d012 | 314 | } |
23759dc6 | 315 | |
3e82d012 RK |
316 | *handle = page_to_dma(dev, page); |
317 | return page_address(page); | |
23759dc6 LB |
318 | } |
319 | ||
1da177e4 LT |
320 | return __dma_alloc(dev, size, handle, gfp, |
321 | pgprot_noncached(pgprot_kernel)); | |
322 | } | |
323 | EXPORT_SYMBOL(dma_alloc_coherent); | |
324 | ||
325 | /* | |
326 | * Allocate a writecombining region, in much the same way as | |
327 | * dma_alloc_coherent above. | |
328 | */ | |
329 | void * | |
f9e3214a | 330 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 LT |
331 | { |
332 | return __dma_alloc(dev, size, handle, gfp, | |
333 | pgprot_writecombine(pgprot_kernel)); | |
334 | } | |
335 | EXPORT_SYMBOL(dma_alloc_writecombine); | |
336 | ||
337 | static int dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
338 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
339 | { | |
ab6494f0 CM |
340 | int ret = -ENXIO; |
341 | #ifdef CONFIG_MMU | |
13ccf3ad RK |
342 | unsigned long user_size, kern_size; |
343 | struct arm_vmregion *c; | |
1da177e4 LT |
344 | |
345 | user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
346 | ||
13ccf3ad | 347 | c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
348 | if (c) { |
349 | unsigned long off = vma->vm_pgoff; | |
350 | ||
351 | kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT; | |
352 | ||
353 | if (off < kern_size && | |
354 | user_size <= (kern_size - off)) { | |
1da177e4 LT |
355 | ret = remap_pfn_range(vma, vma->vm_start, |
356 | page_to_pfn(c->vm_pages) + off, | |
357 | user_size << PAGE_SHIFT, | |
358 | vma->vm_page_prot); | |
359 | } | |
360 | } | |
ab6494f0 | 361 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
362 | |
363 | return ret; | |
364 | } | |
365 | ||
366 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | |
367 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
368 | { | |
369 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
370 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
371 | } | |
372 | EXPORT_SYMBOL(dma_mmap_coherent); | |
373 | ||
374 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | |
375 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
376 | { | |
377 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
378 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
379 | } | |
380 | EXPORT_SYMBOL(dma_mmap_writecombine); | |
381 | ||
382 | /* | |
383 | * free a page as defined by the above mapping. | |
5edf71ae | 384 | * Must not be called with IRQs disabled. |
1da177e4 LT |
385 | */ |
386 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) | |
387 | { | |
5edf71ae RK |
388 | WARN_ON(irqs_disabled()); |
389 | ||
1fe53268 DB |
390 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
391 | return; | |
392 | ||
3e82d012 RK |
393 | size = PAGE_ALIGN(size); |
394 | ||
695ae0af RK |
395 | if (!arch_is_coherent()) |
396 | __dma_free_remap(cpu_addr, size); | |
7a9a32a9 RK |
397 | |
398 | __dma_free_buffer(dma_to_page(dev, handle), size); | |
1da177e4 LT |
399 | } |
400 | EXPORT_SYMBOL(dma_free_coherent); | |
401 | ||
402 | /* | |
403 | * Initialise the consistent memory allocation. | |
404 | */ | |
405 | static int __init consistent_init(void) | |
406 | { | |
ab6494f0 CM |
407 | int ret = 0; |
408 | #ifdef CONFIG_MMU | |
1da177e4 LT |
409 | pgd_t *pgd; |
410 | pmd_t *pmd; | |
411 | pte_t *pte; | |
ab6494f0 | 412 | int i = 0; |
37134cd5 | 413 | u32 base = CONSISTENT_BASE; |
1da177e4 | 414 | |
1da177e4 | 415 | do { |
37134cd5 KH |
416 | pgd = pgd_offset(&init_mm, base); |
417 | pmd = pmd_alloc(&init_mm, pgd, base); | |
1da177e4 LT |
418 | if (!pmd) { |
419 | printk(KERN_ERR "%s: no pmd tables\n", __func__); | |
420 | ret = -ENOMEM; | |
421 | break; | |
422 | } | |
423 | WARN_ON(!pmd_none(*pmd)); | |
424 | ||
37134cd5 | 425 | pte = pte_alloc_kernel(pmd, base); |
1da177e4 LT |
426 | if (!pte) { |
427 | printk(KERN_ERR "%s: no pte tables\n", __func__); | |
428 | ret = -ENOMEM; | |
429 | break; | |
430 | } | |
431 | ||
37134cd5 KH |
432 | consistent_pte[i++] = pte; |
433 | base += (1 << PGDIR_SHIFT); | |
434 | } while (base < CONSISTENT_END); | |
ab6494f0 | 435 | #endif /* !CONFIG_MMU */ |
1da177e4 | 436 | |
1da177e4 LT |
437 | return ret; |
438 | } | |
439 | ||
440 | core_initcall(consistent_init); | |
441 | ||
442 | /* | |
443 | * Make an area consistent for devices. | |
105ef9a0 DW |
444 | * Note: Drivers should NOT use this function directly, as it will break |
445 | * platforms with CONFIG_DMABOUNCE. | |
446 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
1da177e4 | 447 | */ |
84aa462e | 448 | void dma_cache_maint(const void *start, size_t size, int direction) |
1da177e4 | 449 | { |
1522ac3e RK |
450 | void (*inner_op)(const void *, const void *); |
451 | void (*outer_op)(unsigned long, unsigned long); | |
1da177e4 | 452 | |
1522ac3e | 453 | BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1)); |
953233dc | 454 | |
1da177e4 LT |
455 | switch (direction) { |
456 | case DMA_FROM_DEVICE: /* invalidate only */ | |
1522ac3e RK |
457 | inner_op = dmac_inv_range; |
458 | outer_op = outer_inv_range; | |
1da177e4 LT |
459 | break; |
460 | case DMA_TO_DEVICE: /* writeback only */ | |
1522ac3e RK |
461 | inner_op = dmac_clean_range; |
462 | outer_op = outer_clean_range; | |
1da177e4 LT |
463 | break; |
464 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
1522ac3e RK |
465 | inner_op = dmac_flush_range; |
466 | outer_op = outer_flush_range; | |
1da177e4 LT |
467 | break; |
468 | default: | |
469 | BUG(); | |
470 | } | |
1522ac3e RK |
471 | |
472 | inner_op(start, start + size); | |
473 | outer_op(__pa(start), __pa(start) + size); | |
1da177e4 | 474 | } |
84aa462e | 475 | EXPORT_SYMBOL(dma_cache_maint); |
afd1a321 | 476 | |
43377453 NP |
477 | static void dma_cache_maint_contiguous(struct page *page, unsigned long offset, |
478 | size_t size, int direction) | |
479 | { | |
480 | void *vaddr; | |
481 | unsigned long paddr; | |
482 | void (*inner_op)(const void *, const void *); | |
483 | void (*outer_op)(unsigned long, unsigned long); | |
484 | ||
485 | switch (direction) { | |
486 | case DMA_FROM_DEVICE: /* invalidate only */ | |
487 | inner_op = dmac_inv_range; | |
488 | outer_op = outer_inv_range; | |
489 | break; | |
490 | case DMA_TO_DEVICE: /* writeback only */ | |
491 | inner_op = dmac_clean_range; | |
492 | outer_op = outer_clean_range; | |
493 | break; | |
494 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
495 | inner_op = dmac_flush_range; | |
496 | outer_op = outer_flush_range; | |
497 | break; | |
498 | default: | |
499 | BUG(); | |
500 | } | |
501 | ||
502 | if (!PageHighMem(page)) { | |
503 | vaddr = page_address(page) + offset; | |
504 | inner_op(vaddr, vaddr + size); | |
505 | } else { | |
506 | vaddr = kmap_high_get(page); | |
507 | if (vaddr) { | |
508 | vaddr += offset; | |
509 | inner_op(vaddr, vaddr + size); | |
510 | kunmap_high(page); | |
511 | } | |
512 | } | |
513 | ||
514 | paddr = page_to_phys(page) + offset; | |
515 | outer_op(paddr, paddr + size); | |
516 | } | |
517 | ||
518 | void dma_cache_maint_page(struct page *page, unsigned long offset, | |
519 | size_t size, int dir) | |
520 | { | |
521 | /* | |
522 | * A single sg entry may refer to multiple physically contiguous | |
523 | * pages. But we still need to process highmem pages individually. | |
524 | * If highmem is not configured then the bulk of this loop gets | |
525 | * optimized out. | |
526 | */ | |
527 | size_t left = size; | |
528 | do { | |
529 | size_t len = left; | |
530 | if (PageHighMem(page) && len + offset > PAGE_SIZE) { | |
531 | if (offset >= PAGE_SIZE) { | |
532 | page += offset / PAGE_SIZE; | |
533 | offset %= PAGE_SIZE; | |
534 | } | |
535 | len = PAGE_SIZE - offset; | |
536 | } | |
537 | dma_cache_maint_contiguous(page, offset, len, dir); | |
538 | offset = 0; | |
539 | page++; | |
540 | left -= len; | |
541 | } while (left); | |
542 | } | |
543 | EXPORT_SYMBOL(dma_cache_maint_page); | |
544 | ||
afd1a321 RK |
545 | /** |
546 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | |
547 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
548 | * @sg: list of buffers | |
549 | * @nents: number of buffers to map | |
550 | * @dir: DMA transfer direction | |
551 | * | |
552 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
553 | * This is the scatter-gather version of the dma_map_single interface. | |
554 | * Here the scatter gather list elements are each tagged with the | |
555 | * appropriate dma address and length. They are obtained via | |
556 | * sg_dma_{address,length}. | |
557 | * | |
558 | * Device ownership issues as mentioned for dma_map_single are the same | |
559 | * here. | |
560 | */ | |
561 | int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
562 | enum dma_data_direction dir) | |
563 | { | |
564 | struct scatterlist *s; | |
01135d92 | 565 | int i, j; |
afd1a321 RK |
566 | |
567 | for_each_sg(sg, s, nents, i) { | |
01135d92 RK |
568 | s->dma_address = dma_map_page(dev, sg_page(s), s->offset, |
569 | s->length, dir); | |
570 | if (dma_mapping_error(dev, s->dma_address)) | |
571 | goto bad_mapping; | |
afd1a321 | 572 | } |
afd1a321 | 573 | return nents; |
01135d92 RK |
574 | |
575 | bad_mapping: | |
576 | for_each_sg(sg, s, i, j) | |
577 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
578 | return 0; | |
afd1a321 RK |
579 | } |
580 | EXPORT_SYMBOL(dma_map_sg); | |
581 | ||
582 | /** | |
583 | * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
584 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
585 | * @sg: list of buffers | |
586 | * @nents: number of buffers to unmap (returned from dma_map_sg) | |
587 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
588 | * | |
589 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
590 | * rules concerning calls here are the same as for dma_unmap_single(). | |
591 | */ | |
592 | void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
593 | enum dma_data_direction dir) | |
594 | { | |
01135d92 RK |
595 | struct scatterlist *s; |
596 | int i; | |
597 | ||
598 | for_each_sg(sg, s, nents, i) | |
599 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
afd1a321 RK |
600 | } |
601 | EXPORT_SYMBOL(dma_unmap_sg); | |
602 | ||
603 | /** | |
604 | * dma_sync_sg_for_cpu | |
605 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
606 | * @sg: list of buffers | |
607 | * @nents: number of buffers to map (returned from dma_map_sg) | |
608 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
609 | */ | |
610 | void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
611 | int nents, enum dma_data_direction dir) | |
612 | { | |
613 | struct scatterlist *s; | |
614 | int i; | |
615 | ||
616 | for_each_sg(sg, s, nents, i) { | |
309dbbab RK |
617 | dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0, |
618 | sg_dma_len(s), dir); | |
afd1a321 RK |
619 | } |
620 | } | |
621 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); | |
622 | ||
623 | /** | |
624 | * dma_sync_sg_for_device | |
625 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
626 | * @sg: list of buffers | |
627 | * @nents: number of buffers to map (returned from dma_map_sg) | |
628 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
629 | */ | |
630 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
631 | int nents, enum dma_data_direction dir) | |
632 | { | |
633 | struct scatterlist *s; | |
634 | int i; | |
635 | ||
636 | for_each_sg(sg, s, nents, i) { | |
2638b4db RK |
637 | if (!dmabounce_sync_for_device(dev, sg_dma_address(s), 0, |
638 | sg_dma_len(s), dir)) | |
639 | continue; | |
640 | ||
afd1a321 | 641 | if (!arch_is_coherent()) |
43377453 NP |
642 | dma_cache_maint_page(sg_page(s), s->offset, |
643 | s->length, dir); | |
afd1a321 RK |
644 | } |
645 | } | |
646 | EXPORT_SYMBOL(dma_sync_sg_for_device); |