Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | ||
23759dc6 | 21 | #include <asm/memory.h> |
43377453 | 22 | #include <asm/highmem.h> |
1da177e4 | 23 | #include <asm/cacheflush.h> |
1da177e4 | 24 | #include <asm/tlbflush.h> |
37134cd5 KH |
25 | #include <asm/sizes.h> |
26 | ||
27 | /* Sanity check size */ | |
28 | #if (CONSISTENT_DMA_SIZE % SZ_2M) | |
29 | #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" | |
30 | #endif | |
1da177e4 | 31 | |
1da177e4 | 32 | #define CONSISTENT_END (0xffe00000) |
37134cd5 KH |
33 | #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) |
34 | ||
1da177e4 | 35 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) |
37134cd5 KH |
36 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) |
37 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) | |
38 | ||
ab6494f0 CM |
39 | static u64 get_coherent_dma_mask(struct device *dev) |
40 | { | |
41 | u64 mask = ISA_DMA_THRESHOLD; | |
42 | ||
43 | if (dev) { | |
44 | mask = dev->coherent_dma_mask; | |
45 | ||
46 | /* | |
47 | * Sanity check the DMA mask - it must be non-zero, and | |
48 | * must be able to be satisfied by a DMA allocation. | |
49 | */ | |
50 | if (mask == 0) { | |
51 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
52 | return 0; | |
53 | } | |
54 | ||
55 | if ((~mask) & ISA_DMA_THRESHOLD) { | |
56 | dev_warn(dev, "coherent DMA mask %#llx is smaller " | |
57 | "than system GFP_DMA mask %#llx\n", | |
58 | mask, (unsigned long long)ISA_DMA_THRESHOLD); | |
59 | return 0; | |
60 | } | |
61 | } | |
1da177e4 | 62 | |
ab6494f0 CM |
63 | return mask; |
64 | } | |
65 | ||
66 | #ifdef CONFIG_MMU | |
1da177e4 | 67 | /* |
37134cd5 | 68 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 69 | */ |
37134cd5 | 70 | static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; |
1da177e4 | 71 | |
13ccf3ad | 72 | #include "vmregion.h" |
1da177e4 | 73 | |
13ccf3ad RK |
74 | static struct arm_vmregion_head consistent_head = { |
75 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 LT |
76 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
77 | .vm_start = CONSISTENT_BASE, | |
78 | .vm_end = CONSISTENT_END, | |
79 | }; | |
80 | ||
1da177e4 LT |
81 | #ifdef CONFIG_HUGETLB_PAGE |
82 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
83 | #endif | |
84 | ||
85 | static void * | |
f9e3214a | 86 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, |
1da177e4 LT |
87 | pgprot_t prot) |
88 | { | |
89 | struct page *page; | |
13ccf3ad | 90 | struct arm_vmregion *c; |
1da177e4 | 91 | unsigned long order; |
ab6494f0 CM |
92 | u64 mask = get_coherent_dma_mask(dev); |
93 | u64 limit; | |
1da177e4 | 94 | |
37134cd5 | 95 | if (!consistent_pte[0]) { |
1da177e4 LT |
96 | printk(KERN_ERR "%s: not initialised\n", __func__); |
97 | dump_stack(); | |
98 | return NULL; | |
99 | } | |
100 | ||
ab6494f0 CM |
101 | if (!mask) |
102 | goto no_page; | |
1da177e4 | 103 | |
1da177e4 LT |
104 | size = PAGE_ALIGN(size); |
105 | limit = (mask + 1) & ~mask; | |
13ccf3ad | 106 | if (limit && size >= limit) { |
1da177e4 LT |
107 | printk(KERN_WARNING "coherent allocation too big " |
108 | "(requested %#x mask %#llx)\n", size, mask); | |
109 | goto no_page; | |
110 | } | |
111 | ||
112 | order = get_order(size); | |
113 | ||
c06e004c | 114 | if (mask < 0xffffffffULL) |
1da177e4 LT |
115 | gfp |= GFP_DMA; |
116 | ||
117 | page = alloc_pages(gfp, order); | |
118 | if (!page) | |
119 | goto no_page; | |
120 | ||
121 | /* | |
122 | * Invalidate any data that might be lurking in the | |
123 | * kernel direct-mapped region for device DMA. | |
124 | */ | |
125 | { | |
7ae5a761 RK |
126 | void *ptr = page_address(page); |
127 | memset(ptr, 0, size); | |
128 | dmac_flush_range(ptr, ptr + size); | |
129 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
1da177e4 LT |
130 | } |
131 | ||
132 | /* | |
133 | * Allocate a virtual address in the consistent mapping region. | |
134 | */ | |
13ccf3ad | 135 | c = arm_vmregion_alloc(&consistent_head, size, |
1da177e4 LT |
136 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); |
137 | if (c) { | |
37134cd5 | 138 | pte_t *pte; |
1da177e4 | 139 | struct page *end = page + (1 << order); |
37134cd5 KH |
140 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
141 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 142 | |
37134cd5 | 143 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
144 | c->vm_pages = page; |
145 | ||
8dfcc9ba NP |
146 | split_page(page, order); |
147 | ||
1da177e4 LT |
148 | /* |
149 | * Set the "dma handle" | |
150 | */ | |
151 | *handle = page_to_dma(dev, page); | |
152 | ||
153 | do { | |
154 | BUG_ON(!pte_none(*pte)); | |
155 | ||
1da177e4 LT |
156 | /* |
157 | * x86 does not mark the pages reserved... | |
158 | */ | |
159 | SetPageReserved(page); | |
ad1ae2fe | 160 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
161 | page++; |
162 | pte++; | |
37134cd5 KH |
163 | off++; |
164 | if (off >= PTRS_PER_PTE) { | |
165 | off = 0; | |
166 | pte = consistent_pte[++idx]; | |
167 | } | |
1da177e4 LT |
168 | } while (size -= PAGE_SIZE); |
169 | ||
170 | /* | |
171 | * Free the otherwise unused pages. | |
172 | */ | |
173 | while (page < end) { | |
1da177e4 LT |
174 | __free_page(page); |
175 | page++; | |
176 | } | |
177 | ||
178 | return (void *)c->vm_start; | |
179 | } | |
180 | ||
181 | if (page) | |
182 | __free_pages(page, order); | |
183 | no_page: | |
184 | *handle = ~0; | |
185 | return NULL; | |
186 | } | |
ab6494f0 CM |
187 | #else /* !CONFIG_MMU */ |
188 | static void * | |
189 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |
190 | pgprot_t prot) | |
191 | { | |
192 | void *virt; | |
193 | u64 mask = get_coherent_dma_mask(dev); | |
194 | ||
195 | if (!mask) | |
196 | goto error; | |
197 | ||
c06e004c | 198 | if (mask < 0xffffffffULL) |
ab6494f0 CM |
199 | gfp |= GFP_DMA; |
200 | virt = kmalloc(size, gfp); | |
201 | if (!virt) | |
202 | goto error; | |
203 | ||
204 | *handle = virt_to_dma(dev, virt); | |
205 | return virt; | |
206 | ||
207 | error: | |
208 | *handle = ~0; | |
209 | return NULL; | |
210 | } | |
211 | #endif /* CONFIG_MMU */ | |
1da177e4 LT |
212 | |
213 | /* | |
214 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
215 | * virtual and bus address for that space. | |
216 | */ | |
217 | void * | |
f9e3214a | 218 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 | 219 | { |
1fe53268 DB |
220 | void *memory; |
221 | ||
222 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
223 | return memory; | |
224 | ||
23759dc6 LB |
225 | if (arch_is_coherent()) { |
226 | void *virt; | |
227 | ||
228 | virt = kmalloc(size, gfp); | |
229 | if (!virt) | |
230 | return NULL; | |
231 | *handle = virt_to_dma(dev, virt); | |
232 | ||
233 | return virt; | |
234 | } | |
235 | ||
1da177e4 LT |
236 | return __dma_alloc(dev, size, handle, gfp, |
237 | pgprot_noncached(pgprot_kernel)); | |
238 | } | |
239 | EXPORT_SYMBOL(dma_alloc_coherent); | |
240 | ||
241 | /* | |
242 | * Allocate a writecombining region, in much the same way as | |
243 | * dma_alloc_coherent above. | |
244 | */ | |
245 | void * | |
f9e3214a | 246 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 LT |
247 | { |
248 | return __dma_alloc(dev, size, handle, gfp, | |
249 | pgprot_writecombine(pgprot_kernel)); | |
250 | } | |
251 | EXPORT_SYMBOL(dma_alloc_writecombine); | |
252 | ||
253 | static int dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
254 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
255 | { | |
ab6494f0 CM |
256 | int ret = -ENXIO; |
257 | #ifdef CONFIG_MMU | |
13ccf3ad RK |
258 | unsigned long user_size, kern_size; |
259 | struct arm_vmregion *c; | |
1da177e4 LT |
260 | |
261 | user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
262 | ||
13ccf3ad | 263 | c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
264 | if (c) { |
265 | unsigned long off = vma->vm_pgoff; | |
266 | ||
267 | kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT; | |
268 | ||
269 | if (off < kern_size && | |
270 | user_size <= (kern_size - off)) { | |
1da177e4 LT |
271 | ret = remap_pfn_range(vma, vma->vm_start, |
272 | page_to_pfn(c->vm_pages) + off, | |
273 | user_size << PAGE_SHIFT, | |
274 | vma->vm_page_prot); | |
275 | } | |
276 | } | |
ab6494f0 | 277 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
278 | |
279 | return ret; | |
280 | } | |
281 | ||
282 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | |
283 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
284 | { | |
285 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
286 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
287 | } | |
288 | EXPORT_SYMBOL(dma_mmap_coherent); | |
289 | ||
290 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | |
291 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
292 | { | |
293 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
294 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
295 | } | |
296 | EXPORT_SYMBOL(dma_mmap_writecombine); | |
297 | ||
298 | /* | |
299 | * free a page as defined by the above mapping. | |
5edf71ae | 300 | * Must not be called with IRQs disabled. |
1da177e4 | 301 | */ |
ab6494f0 | 302 | #ifdef CONFIG_MMU |
1da177e4 LT |
303 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) |
304 | { | |
13ccf3ad RK |
305 | struct arm_vmregion *c; |
306 | unsigned long addr; | |
1da177e4 | 307 | pte_t *ptep; |
37134cd5 KH |
308 | int idx; |
309 | u32 off; | |
1da177e4 | 310 | |
5edf71ae RK |
311 | WARN_ON(irqs_disabled()); |
312 | ||
1fe53268 DB |
313 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
314 | return; | |
315 | ||
23759dc6 LB |
316 | if (arch_is_coherent()) { |
317 | kfree(cpu_addr); | |
318 | return; | |
319 | } | |
320 | ||
1da177e4 LT |
321 | size = PAGE_ALIGN(size); |
322 | ||
13ccf3ad | 323 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
324 | if (!c) |
325 | goto no_area; | |
326 | ||
327 | if ((c->vm_end - c->vm_start) != size) { | |
328 | printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n", | |
329 | __func__, c->vm_end - c->vm_start, size); | |
330 | dump_stack(); | |
331 | size = c->vm_end - c->vm_start; | |
332 | } | |
333 | ||
37134cd5 KH |
334 | idx = CONSISTENT_PTE_INDEX(c->vm_start); |
335 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
336 | ptep = consistent_pte[idx] + off; | |
1da177e4 LT |
337 | addr = c->vm_start; |
338 | do { | |
339 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
340 | unsigned long pfn; | |
341 | ||
342 | ptep++; | |
343 | addr += PAGE_SIZE; | |
37134cd5 KH |
344 | off++; |
345 | if (off >= PTRS_PER_PTE) { | |
346 | off = 0; | |
347 | ptep = consistent_pte[++idx]; | |
348 | } | |
1da177e4 LT |
349 | |
350 | if (!pte_none(pte) && pte_present(pte)) { | |
351 | pfn = pte_pfn(pte); | |
352 | ||
353 | if (pfn_valid(pfn)) { | |
354 | struct page *page = pfn_to_page(pfn); | |
355 | ||
356 | /* | |
357 | * x86 does not mark the pages reserved... | |
358 | */ | |
359 | ClearPageReserved(page); | |
360 | ||
361 | __free_page(page); | |
362 | continue; | |
363 | } | |
364 | } | |
365 | ||
366 | printk(KERN_CRIT "%s: bad page in kernel page table\n", | |
367 | __func__); | |
368 | } while (size -= PAGE_SIZE); | |
369 | ||
370 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
371 | ||
13ccf3ad | 372 | arm_vmregion_free(&consistent_head, c); |
1da177e4 LT |
373 | return; |
374 | ||
375 | no_area: | |
1da177e4 LT |
376 | printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n", |
377 | __func__, cpu_addr); | |
378 | dump_stack(); | |
379 | } | |
ab6494f0 CM |
380 | #else /* !CONFIG_MMU */ |
381 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) | |
382 | { | |
383 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) | |
384 | return; | |
385 | kfree(cpu_addr); | |
386 | } | |
387 | #endif /* CONFIG_MMU */ | |
1da177e4 LT |
388 | EXPORT_SYMBOL(dma_free_coherent); |
389 | ||
390 | /* | |
391 | * Initialise the consistent memory allocation. | |
392 | */ | |
393 | static int __init consistent_init(void) | |
394 | { | |
ab6494f0 CM |
395 | int ret = 0; |
396 | #ifdef CONFIG_MMU | |
1da177e4 LT |
397 | pgd_t *pgd; |
398 | pmd_t *pmd; | |
399 | pte_t *pte; | |
ab6494f0 | 400 | int i = 0; |
37134cd5 | 401 | u32 base = CONSISTENT_BASE; |
1da177e4 | 402 | |
1da177e4 | 403 | do { |
37134cd5 KH |
404 | pgd = pgd_offset(&init_mm, base); |
405 | pmd = pmd_alloc(&init_mm, pgd, base); | |
1da177e4 LT |
406 | if (!pmd) { |
407 | printk(KERN_ERR "%s: no pmd tables\n", __func__); | |
408 | ret = -ENOMEM; | |
409 | break; | |
410 | } | |
411 | WARN_ON(!pmd_none(*pmd)); | |
412 | ||
37134cd5 | 413 | pte = pte_alloc_kernel(pmd, base); |
1da177e4 LT |
414 | if (!pte) { |
415 | printk(KERN_ERR "%s: no pte tables\n", __func__); | |
416 | ret = -ENOMEM; | |
417 | break; | |
418 | } | |
419 | ||
37134cd5 KH |
420 | consistent_pte[i++] = pte; |
421 | base += (1 << PGDIR_SHIFT); | |
422 | } while (base < CONSISTENT_END); | |
ab6494f0 | 423 | #endif /* !CONFIG_MMU */ |
1da177e4 | 424 | |
1da177e4 LT |
425 | return ret; |
426 | } | |
427 | ||
428 | core_initcall(consistent_init); | |
429 | ||
430 | /* | |
431 | * Make an area consistent for devices. | |
105ef9a0 DW |
432 | * Note: Drivers should NOT use this function directly, as it will break |
433 | * platforms with CONFIG_DMABOUNCE. | |
434 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
1da177e4 | 435 | */ |
84aa462e | 436 | void dma_cache_maint(const void *start, size_t size, int direction) |
1da177e4 | 437 | { |
1522ac3e RK |
438 | void (*inner_op)(const void *, const void *); |
439 | void (*outer_op)(unsigned long, unsigned long); | |
1da177e4 | 440 | |
1522ac3e | 441 | BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1)); |
953233dc | 442 | |
1da177e4 LT |
443 | switch (direction) { |
444 | case DMA_FROM_DEVICE: /* invalidate only */ | |
1522ac3e RK |
445 | inner_op = dmac_inv_range; |
446 | outer_op = outer_inv_range; | |
1da177e4 LT |
447 | break; |
448 | case DMA_TO_DEVICE: /* writeback only */ | |
1522ac3e RK |
449 | inner_op = dmac_clean_range; |
450 | outer_op = outer_clean_range; | |
1da177e4 LT |
451 | break; |
452 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
1522ac3e RK |
453 | inner_op = dmac_flush_range; |
454 | outer_op = outer_flush_range; | |
1da177e4 LT |
455 | break; |
456 | default: | |
457 | BUG(); | |
458 | } | |
1522ac3e RK |
459 | |
460 | inner_op(start, start + size); | |
461 | outer_op(__pa(start), __pa(start) + size); | |
1da177e4 | 462 | } |
84aa462e | 463 | EXPORT_SYMBOL(dma_cache_maint); |
afd1a321 | 464 | |
43377453 NP |
465 | static void dma_cache_maint_contiguous(struct page *page, unsigned long offset, |
466 | size_t size, int direction) | |
467 | { | |
468 | void *vaddr; | |
469 | unsigned long paddr; | |
470 | void (*inner_op)(const void *, const void *); | |
471 | void (*outer_op)(unsigned long, unsigned long); | |
472 | ||
473 | switch (direction) { | |
474 | case DMA_FROM_DEVICE: /* invalidate only */ | |
475 | inner_op = dmac_inv_range; | |
476 | outer_op = outer_inv_range; | |
477 | break; | |
478 | case DMA_TO_DEVICE: /* writeback only */ | |
479 | inner_op = dmac_clean_range; | |
480 | outer_op = outer_clean_range; | |
481 | break; | |
482 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
483 | inner_op = dmac_flush_range; | |
484 | outer_op = outer_flush_range; | |
485 | break; | |
486 | default: | |
487 | BUG(); | |
488 | } | |
489 | ||
490 | if (!PageHighMem(page)) { | |
491 | vaddr = page_address(page) + offset; | |
492 | inner_op(vaddr, vaddr + size); | |
493 | } else { | |
494 | vaddr = kmap_high_get(page); | |
495 | if (vaddr) { | |
496 | vaddr += offset; | |
497 | inner_op(vaddr, vaddr + size); | |
498 | kunmap_high(page); | |
499 | } | |
500 | } | |
501 | ||
502 | paddr = page_to_phys(page) + offset; | |
503 | outer_op(paddr, paddr + size); | |
504 | } | |
505 | ||
506 | void dma_cache_maint_page(struct page *page, unsigned long offset, | |
507 | size_t size, int dir) | |
508 | { | |
509 | /* | |
510 | * A single sg entry may refer to multiple physically contiguous | |
511 | * pages. But we still need to process highmem pages individually. | |
512 | * If highmem is not configured then the bulk of this loop gets | |
513 | * optimized out. | |
514 | */ | |
515 | size_t left = size; | |
516 | do { | |
517 | size_t len = left; | |
518 | if (PageHighMem(page) && len + offset > PAGE_SIZE) { | |
519 | if (offset >= PAGE_SIZE) { | |
520 | page += offset / PAGE_SIZE; | |
521 | offset %= PAGE_SIZE; | |
522 | } | |
523 | len = PAGE_SIZE - offset; | |
524 | } | |
525 | dma_cache_maint_contiguous(page, offset, len, dir); | |
526 | offset = 0; | |
527 | page++; | |
528 | left -= len; | |
529 | } while (left); | |
530 | } | |
531 | EXPORT_SYMBOL(dma_cache_maint_page); | |
532 | ||
afd1a321 RK |
533 | /** |
534 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | |
535 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
536 | * @sg: list of buffers | |
537 | * @nents: number of buffers to map | |
538 | * @dir: DMA transfer direction | |
539 | * | |
540 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
541 | * This is the scatter-gather version of the dma_map_single interface. | |
542 | * Here the scatter gather list elements are each tagged with the | |
543 | * appropriate dma address and length. They are obtained via | |
544 | * sg_dma_{address,length}. | |
545 | * | |
546 | * Device ownership issues as mentioned for dma_map_single are the same | |
547 | * here. | |
548 | */ | |
549 | int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
550 | enum dma_data_direction dir) | |
551 | { | |
552 | struct scatterlist *s; | |
01135d92 | 553 | int i, j; |
afd1a321 RK |
554 | |
555 | for_each_sg(sg, s, nents, i) { | |
01135d92 RK |
556 | s->dma_address = dma_map_page(dev, sg_page(s), s->offset, |
557 | s->length, dir); | |
558 | if (dma_mapping_error(dev, s->dma_address)) | |
559 | goto bad_mapping; | |
afd1a321 | 560 | } |
afd1a321 | 561 | return nents; |
01135d92 RK |
562 | |
563 | bad_mapping: | |
564 | for_each_sg(sg, s, i, j) | |
565 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
566 | return 0; | |
afd1a321 RK |
567 | } |
568 | EXPORT_SYMBOL(dma_map_sg); | |
569 | ||
570 | /** | |
571 | * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
572 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
573 | * @sg: list of buffers | |
574 | * @nents: number of buffers to unmap (returned from dma_map_sg) | |
575 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
576 | * | |
577 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
578 | * rules concerning calls here are the same as for dma_unmap_single(). | |
579 | */ | |
580 | void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
581 | enum dma_data_direction dir) | |
582 | { | |
01135d92 RK |
583 | struct scatterlist *s; |
584 | int i; | |
585 | ||
586 | for_each_sg(sg, s, nents, i) | |
587 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
afd1a321 RK |
588 | } |
589 | EXPORT_SYMBOL(dma_unmap_sg); | |
590 | ||
591 | /** | |
592 | * dma_sync_sg_for_cpu | |
593 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
594 | * @sg: list of buffers | |
595 | * @nents: number of buffers to map (returned from dma_map_sg) | |
596 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
597 | */ | |
598 | void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
599 | int nents, enum dma_data_direction dir) | |
600 | { | |
601 | struct scatterlist *s; | |
602 | int i; | |
603 | ||
604 | for_each_sg(sg, s, nents, i) { | |
309dbbab RK |
605 | dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0, |
606 | sg_dma_len(s), dir); | |
afd1a321 RK |
607 | } |
608 | } | |
609 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); | |
610 | ||
611 | /** | |
612 | * dma_sync_sg_for_device | |
613 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
614 | * @sg: list of buffers | |
615 | * @nents: number of buffers to map (returned from dma_map_sg) | |
616 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
617 | */ | |
618 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
619 | int nents, enum dma_data_direction dir) | |
620 | { | |
621 | struct scatterlist *s; | |
622 | int i; | |
623 | ||
624 | for_each_sg(sg, s, nents, i) { | |
2638b4db RK |
625 | if (!dmabounce_sync_for_device(dev, sg_dma_address(s), 0, |
626 | sg_dma_len(s), dir)) | |
627 | continue; | |
628 | ||
afd1a321 | 629 | if (!arch_is_coherent()) |
43377453 NP |
630 | dma_cache_maint_page(sg_page(s), s->offset, |
631 | s->length, dir); | |
afd1a321 RK |
632 | } |
633 | } | |
634 | EXPORT_SYMBOL(dma_sync_sg_for_device); |