[linux-2.6-block.git] / arch / arm / mach-ux500 / include / mach / hardware.h

/*
 * Copyright (C) 2009 ST-Ericsson.
 *
 * U8500 hardware definitions
 *
 * This file is licensed under  the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H

/* macros to get at IO space when running virtually
 * We dont map all the peripherals, let ioremap do
 * this for us. We map only very basic peripherals here.
 */
#define U8500_IO_VIRTUAL	0xf0000000
#define U8500_IO_PHYSICAL	0xa0000000

/* this macro is used in assembly, so no cast */
#define IO_ADDRESS(x)           \
	(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)

/* typesafe io address */
#define __io_address(n)		__io(IO_ADDRESS(n))

/*
 * Base address definitions for U8500 Onchip IPs. All the
 * peripherals are contained in a single 1 Mbyte region, with
 * AHB peripherals at the bottom and APB peripherals at the
 * top of the region. PER stands for PERIPHERAL region which
 * itself divided into sub regions.
 */
#define U8500_PER3_BASE		0x80000000
#define U8500_PER2_BASE		0x80110000
#define U8500_PER1_BASE		0x80120000
#define U8500_PER4_BASE		0x80150000

#define U8500_PER6_BASE		0xa03c0000
#define U8500_PER5_BASE		0xa03e0000
#define U8500_PER7_BASE		0xa03d0000

#define U8500_SVA_BASE		0xa0100000
#define U8500_SIA_BASE		0xa0200000

#define U8500_SGA_BASE		0xa0300000
#define U8500_MCDE_BASE		0xa0350000
#define U8500_DMA_BASE		0xa0362000

#define U8500_SCU_BASE		0xa0410000
#define U8500_GIC_CPU_BASE	0xa0410100
#define U8500_TWD_BASE		0xa0410600
#define U8500_GIC_DIST_BASE	0xa0411000
#define U8500_L2CC_BASE		0xa0412000

#define U8500_TWD_SIZE		0x100

/* per7 base addressess */
#define U8500_CR_BASE		(U8500_PER7_BASE + 0x8000)
#define U8500_MTU0_BASE		(U8500_PER7_BASE + 0xa000)
#define U8500_MTU1_BASE		(U8500_PER7_BASE + 0xb000)
#define U8500_TZPC0_BASE	(U8500_PER7_BASE + 0xc000)
#define U8500_CLKRST7_BASE	(U8500_PER7_BASE + 0xf000)

/* per6 base addressess */
#define U8500_RNG_BASE		(U8500_PER6_BASE + 0x0000)
#define U8500_PKA_BASE		(U8500_PER6_BASE + 0x1000)
#define U8500_PKAM_BASE		(U8500_PER6_BASE + 0x2000)
#define U8500_CRYPTO0_BASE	(U8500_PER6_BASE + 0xa000)
#define U8500_CRYPTO1_BASE	(U8500_PER6_BASE + 0xb000)
#define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)

/* per5 base addressess */
#define U8500_USBOTG_BASE	(U8500_PER5_BASE + 0x00000)
#define U8500_GPIO5_BASE	(U8500_PER5_BASE + 0x1e000)
#define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)

/* per4 base addressess */
#define U8500_BACKUPRAM0_BASE	(U8500_PER4_BASE + 0x0000)
#define U8500_BACKUPRAM1_BASE	(U8500_PER4_BASE + 0x1000)
#define U8500_RTT0_BASE		(U8500_PER4_BASE + 0x2000)
#define U8500_RTT1_BASE		(U8500_PER4_BASE + 0x3000)
#define U8500_RTC_BASE		(U8500_PER4_BASE + 0x4000)
#define U8500_SCR_BASE		(U8500_PER4_BASE + 0x5000)
#define U8500_DMC_BASE		(U8500_PER4_BASE + 0x6000)
#define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x7000)

/* per3 base addressess */
#define U8500_FSMC_BASE		(U8500_PER3_BASE + 0x0000)
#define U8500_SSP0_BASE		(U8500_PER3_BASE + 0x2000)
#define U8500_SSP1_BASE		(U8500_PER3_BASE + 0x3000)
#define U8500_I2C0_BASE		(U8500_PER3_BASE + 0x4000)
#define U8500_SDI2_BASE		(U8500_PER3_BASE + 0x5000)
#define U8500_SKE_BASE		(U8500_PER3_BASE + 0x6000)
#define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
#define U8500_SDI5_BASE		(U8500_PER3_BASE + 0x8000)
#define U8500_GPIO3_BASE	(U8500_PER3_BASE + 0xe000)
#define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)

/* per2 base addressess */
#define U8500_I2C3_BASE		(U8500_PER2_BASE + 0x0000)
#define U8500_SPI2_BASE		(U8500_PER2_BASE + 0x1000)
#define U8500_SPI1_BASE		(U8500_PER2_BASE + 0x2000)
#define U8500_PWL_BASE		(U8500_PER2_BASE + 0x3000)
#define U8500_SDI4_BASE		(U8500_PER2_BASE + 0x4000)
#define U8500_MSP2_BASE		(U8500_PER2_BASE + 0x7000)
#define U8500_SDI1_BASE		(U8500_PER2_BASE + 0x8000)
#define U8500_SDI3_BASE		(U8500_PER2_BASE + 0x9000)
#define U8500_SPI0_BASE		(U8500_PER2_BASE + 0xa000)
#define U8500_HSIR_BASE		(U8500_PER2_BASE + 0xb000)
#define U8500_HSIT_BASE		(U8500_PER2_BASE + 0xc000)
#define U8500_GPIO2_BASE	(U8500_PER2_BASE + 0xe000)
#define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)

/* per1 base addresses */
#define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
#define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
#define U8500_I2C1_BASE		(U8500_PER1_BASE + 0x2000)
#define U8500_MSP0_BASE		(U8500_PER1_BASE + 0x3000)
#define U8500_MSP1_BASE		(U8500_PER1_BASE + 0x4000)
#define U8500_SDI0_BASE		(U8500_PER1_BASE + 0x6000)
#define U8500_I2C2_BASE		(U8500_PER1_BASE + 0x8000)
#define U8500_SPI3_BASE		(U8500_PER1_BASE + 0x9000)
#define U8500_SLIM0_BASE	(U8500_PER1_BASE + 0xa000)
#define U8500_GPIO1_BASE	(U8500_PER1_BASE + 0xe000)
#define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)

/* ST-Ericsson modified pl022 id */
#define SSP_PER_ID		0x01080022

#endif				/* __MACH_HARDWARE_H */
Commit	Line	Data
ffae4e01 SK	1	/*
	2	* Copyright (C) 2009 ST-Ericsson.
	3	*
	4	* U8500 hardware definitions
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10	#ifndef __MACH_HARDWARE_H
	11	#define __MACH_HARDWARE_H
	12
	13	/* macros to get at IO space when running virtually
	14	* We dont map all the peripherals, let ioremap do
	15	* this for us. We map only very basic peripherals here.
	16	*/
	17	#define U8500_IO_VIRTUAL 0xf0000000
	18	#define U8500_IO_PHYSICAL 0xa0000000
	19
	20	/* this macro is used in assembly, so no cast */
	21	#define IO_ADDRESS(x) \
	22	(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
	23
	24	/* typesafe io address */
	25	#define __io_address(n) __io(IO_ADDRESS(n))
	26
	27	/*
	28	* Base address definitions for U8500 Onchip IPs. All the
	29	* peripherals are contained in a single 1 Mbyte region, with
	30	* AHB peripherals at the bottom and APB peripherals at the
	31	* top of the region. PER stands for PERIPHERAL region which
	32	* itself divided into sub regions.
	33	*/
	34	#define U8500_PER3_BASE 0x80000000
	35	#define U8500_PER2_BASE 0x80110000
	36	#define U8500_PER1_BASE 0x80120000
	37	#define U8500_PER4_BASE 0x80150000
	38
	39	#define U8500_PER6_BASE 0xa03c0000
	40	#define U8500_PER5_BASE 0xa03e0000
	41	#define U8500_PER7_BASE 0xa03d0000
	42
	43	#define U8500_SVA_BASE 0xa0100000
	44	#define U8500_SIA_BASE 0xa0200000
	45
	46	#define U8500_SGA_BASE 0xa0300000
	47	#define U8500_MCDE_BASE 0xa0350000
	48	#define U8500_DMA_BASE 0xa0362000
	49
	50	#define U8500_SCU_BASE 0xa0410000
	51	#define U8500_GIC_CPU_BASE 0xa0410100
	52	#define U8500_TWD_BASE 0xa0410600
	53	#define U8500_GIC_DIST_BASE 0xa0411000
	54	#define U8500_L2CC_BASE 0xa0412000
	55
	56	#define U8500_TWD_SIZE 0x100
	57
	58	/* per7 base addressess */
	59	#define U8500_CR_BASE (U8500_PER7_BASE + 0x8000)
	60	#define U8500_MTU0_BASE (U8500_PER7_BASE + 0xa000)
	61	#define U8500_MTU1_BASE (U8500_PER7_BASE + 0xb000)
	62	#define U8500_TZPC0_BASE (U8500_PER7_BASE + 0xc000)
	63	#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
	64
65	/* per6 base addressess */
66	#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
67	#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
68	#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
69	#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
70	#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
8d2b09f5	71	#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
ffae4e01 SK	72
	73	/* per5 base addressess */
	74	#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
	75	#define U8500_GPIO5_BASE (U8500_PER5_BASE + 0x1e000)
8d2b09f5	76	#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
ffae4e01 SK	77
	78	/* per4 base addressess */
	79	#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x0000)
	80	#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x1000)
	81	#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x2000)
	82	#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x3000)
	83	#define U8500_RTC_BASE (U8500_PER4_BASE + 0x4000)
	84	#define U8500_SCR_BASE (U8500_PER4_BASE + 0x5000)
	85	#define U8500_DMC_BASE (U8500_PER4_BASE + 0x6000)
	86	#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x7000)
	87
	88	/* per3 base addressess */
	89	#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
	90	#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
	91	#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
	92	#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
	93	#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
	94	#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
	95	#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
	96	#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
	97	#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xe000)
8d2b09f5	98	#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
ffae4e01 SK	99
	100	/* per2 base addressess */
	101	#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
	102	#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
	103	#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
	104	#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
	105	#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
	106	#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
	107	#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
	108	#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
	109	#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
	110	#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
	111	#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
	112	#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xe000)
	113	#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
	114
	115	/* per1 base addresses */
	116	#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
	117	#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
	118	#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
	119	#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
	120	#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
	121	#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
	122	#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
	123	#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
	124	#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xa000)
	125	#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
8d2b09f5	126	#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
ffae4e01 SK	127
	128	/* ST-Ericsson modified pl022 id */
	129	#define SSP_PER_ID 0x01080022
	130
	131	#endif /* __MACH_HARDWARE_H */