[linux-2.6-block.git] / arch / arm / mach-spear3xx / spear310.c

/*
 * arch/arm/mach-spear3xx/spear310.c
 *
 * SPEAr310 machine source file
 *
 * Copyright (C) 2009 ST Microelectronics
 * Viresh Kumar<viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/ptrace.h>
#include <asm/irq.h>
#include <mach/generic.h>
#include <mach/spear.h>
#include <plat/shirq.h>

/* pad multiplexing support */
/* muxing registers */
#define PAD_MUX_CONFIG_REG	0x08

/* devices */
struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_TIMER_3_4_MASK,
	},
};

struct pmx_dev pmx_emi_cs_0_1_4_5 = {
	.name = "emi_cs_0_1_4_5",
	.modes = pmx_emi_cs_0_1_4_5_modes,
	.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
	.enb_on_reset = 1,
};

struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_TIMER_1_2_MASK,
	},
};

struct pmx_dev pmx_emi_cs_2_3 = {
	.name = "emi_cs_2_3",
	.modes = pmx_emi_cs_2_3_modes,
	.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
	.enb_on_reset = 1,
};

struct pmx_dev_mode pmx_uart1_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_FIRDA_MASK,
	},
};

struct pmx_dev pmx_uart1 = {
	.name = "uart1",
	.modes = pmx_uart1_modes,
	.mode_count = ARRAY_SIZE(pmx_uart1_modes),
	.enb_on_reset = 1,
};

struct pmx_dev_mode pmx_uart2_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_TIMER_1_2_MASK,
	},
};

struct pmx_dev pmx_uart2 = {
	.name = "uart2",
	.modes = pmx_uart2_modes,
	.mode_count = ARRAY_SIZE(pmx_uart2_modes),
	.enb_on_reset = 1,
};

struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_UART0_MODEM_MASK,
	},
};

struct pmx_dev pmx_uart3_4_5 = {
	.name = "uart3_4_5",
	.modes = pmx_uart3_4_5_modes,
	.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
	.enb_on_reset = 1,
};

struct pmx_dev_mode pmx_fsmc_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_SSP_CS_MASK,
	},
};

struct pmx_dev pmx_fsmc = {
	.name = "fsmc",
	.modes = pmx_fsmc_modes,
	.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
	.enb_on_reset = 1,
};

struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev pmx_rs485_0_1 = {
	.name = "rs485_0_1",
	.modes = pmx_rs485_0_1_modes,
	.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
	.enb_on_reset = 1,
};

struct pmx_dev_mode pmx_tdm0_modes[] = {
	{
		.ids = 0x00,
		.mask = PMX_MII_MASK,
	},
};

struct pmx_dev pmx_tdm0 = {
	.name = "tdm0",
	.modes = pmx_tdm0_modes,
	.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
	.enb_on_reset = 1,
};

/* pmx driver structure */
struct pmx_driver pmx_driver = {
	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
};

/* Add spear310 specific devices here */

/* spear3xx shared irq */
struct shirq_dev_config shirq_ras1_config[] = {
	{
		.virq = VIRQ_SMII0,
		.status_mask = SMII0_IRQ_MASK,
	}, {
		.virq = VIRQ_SMII1,
		.status_mask = SMII1_IRQ_MASK,
	}, {
		.virq = VIRQ_SMII2,
		.status_mask = SMII2_IRQ_MASK,
	}, {
		.virq = VIRQ_SMII3,
		.status_mask = SMII3_IRQ_MASK,
	}, {
		.virq = VIRQ_WAKEUP_SMII0,
		.status_mask = WAKEUP_SMII0_IRQ_MASK,
	}, {
		.virq = VIRQ_WAKEUP_SMII1,
		.status_mask = WAKEUP_SMII1_IRQ_MASK,
	}, {
		.virq = VIRQ_WAKEUP_SMII2,
		.status_mask = WAKEUP_SMII2_IRQ_MASK,
	}, {
		.virq = VIRQ_WAKEUP_SMII3,
		.status_mask = WAKEUP_SMII3_IRQ_MASK,
	},
};

struct spear_shirq shirq_ras1 = {
	.irq = IRQ_GEN_RAS_1,
	.dev_config = shirq_ras1_config,
	.dev_count = ARRAY_SIZE(shirq_ras1_config),
	.regs = {
		.enb_reg = -1,
		.status_reg = INT_STS_MASK_REG,
		.status_reg_mask = SHIRQ_RAS1_MASK,
		.clear_reg = -1,
	},
};

struct shirq_dev_config shirq_ras2_config[] = {
	{
		.virq = VIRQ_UART1,
		.status_mask = UART1_IRQ_MASK,
	}, {
		.virq = VIRQ_UART2,
		.status_mask = UART2_IRQ_MASK,
	}, {
		.virq = VIRQ_UART3,
		.status_mask = UART3_IRQ_MASK,
	}, {
		.virq = VIRQ_UART4,
		.status_mask = UART4_IRQ_MASK,
	}, {
		.virq = VIRQ_UART5,
		.status_mask = UART5_IRQ_MASK,
	},
};

struct spear_shirq shirq_ras2 = {
	.irq = IRQ_GEN_RAS_2,
	.dev_config = shirq_ras2_config,
	.dev_count = ARRAY_SIZE(shirq_ras2_config),
	.regs = {
		.enb_reg = -1,
		.status_reg = INT_STS_MASK_REG,
		.status_reg_mask = SHIRQ_RAS2_MASK,
		.clear_reg = -1,
	},
};

struct shirq_dev_config shirq_ras3_config[] = {
	{
		.virq = VIRQ_EMI,
		.status_mask = EMI_IRQ_MASK,
	},
};

struct spear_shirq shirq_ras3 = {
	.irq = IRQ_GEN_RAS_3,
	.dev_config = shirq_ras3_config,
	.dev_count = ARRAY_SIZE(shirq_ras3_config),
	.regs = {
		.enb_reg = -1,
		.status_reg = INT_STS_MASK_REG,
		.status_reg_mask = SHIRQ_RAS3_MASK,
		.clear_reg = -1,
	},
};

struct shirq_dev_config shirq_intrcomm_ras_config[] = {
	{
		.virq = VIRQ_TDM_HDLC,
		.status_mask = TDM_HDLC_IRQ_MASK,
	}, {
		.virq = VIRQ_RS485_0,
		.status_mask = RS485_0_IRQ_MASK,
	}, {
		.virq = VIRQ_RS485_1,
		.status_mask = RS485_1_IRQ_MASK,
	},
};

struct spear_shirq shirq_intrcomm_ras = {
	.irq = IRQ_INTRCOMM_RAS_ARM,
	.dev_config = shirq_intrcomm_ras_config,
	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
	.regs = {
		.enb_reg = -1,
		.status_reg = INT_STS_MASK_REG,
		.status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
		.clear_reg = -1,
	},
};

/* spear310 routines */
void __init spear310_init(void)
{
	void __iomem *base;
	int ret = 0;

	/* call spear3xx family common init function */
	spear3xx_init();

	/* shared irq registration */
	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
	if (base) {
		/* shirq 1 */
		shirq_ras1.regs.base = base;
		ret = spear_shirq_register(&shirq_ras1);
		if (ret)
			printk(KERN_ERR "Error registering Shared IRQ 1\n");

		/* shirq 2 */
		shirq_ras2.regs.base = base;
		ret = spear_shirq_register(&shirq_ras2);
		if (ret)
			printk(KERN_ERR "Error registering Shared IRQ 2\n");

		/* shirq 3 */
		shirq_ras3.regs.base = base;
		ret = spear_shirq_register(&shirq_ras3);
		if (ret)
			printk(KERN_ERR "Error registering Shared IRQ 3\n");

		/* shirq 4 */
		shirq_intrcomm_ras.regs.base = base;
		ret = spear_shirq_register(&shirq_intrcomm_ras);
		if (ret)
			printk(KERN_ERR "Error registering Shared IRQ 4\n");
	}
}

void spear310_pmx_init(void)
{
	spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
			SPEAR310_SOC_CONFIG_SIZE);
}
Commit	Line	Data
bc4e814e	1	/*
	2	* arch/arm/mach-spear3xx/spear310.c
	3	*
	4	* SPEAr310 machine source file
	5	*
	6	* Copyright (C) 2009 ST Microelectronics
	7	* Viresh Kumar<viresh.kumar@st.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/ptrace.h>
	15	#include <asm/irq.h>
	16	#include <mach/generic.h>
	17	#include <mach/spear.h>
4c18e77f	18	#include <plat/shirq.h>
bc4e814e	19
70f4c0bf	20	/* pad multiplexing support */
	21	/* muxing registers */
	22	#define PAD_MUX_CONFIG_REG 0x08
	23
	24	/* devices */
	25	struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
	26	{
	27	.ids = 0x00,
	28	.mask = PMX_TIMER_3_4_MASK,
	29	},
	30	};
	31
	32	struct pmx_dev pmx_emi_cs_0_1_4_5 = {
	33	.name = "emi_cs_0_1_4_5",
	34	.modes = pmx_emi_cs_0_1_4_5_modes,
	35	.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
	36	.enb_on_reset = 1,
	37	};
	38
	39	struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
	40	{
	41	.ids = 0x00,
	42	.mask = PMX_TIMER_1_2_MASK,
	43	},
	44	};
	45
	46	struct pmx_dev pmx_emi_cs_2_3 = {
	47	.name = "emi_cs_2_3",
	48	.modes = pmx_emi_cs_2_3_modes,
	49	.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
	50	.enb_on_reset = 1,
	51	};
	52
	53	struct pmx_dev_mode pmx_uart1_modes[] = {
	54	{
	55	.ids = 0x00,
	56	.mask = PMX_FIRDA_MASK,
	57	},
	58	};
	59
	60	struct pmx_dev pmx_uart1 = {
	61	.name = "uart1",
	62	.modes = pmx_uart1_modes,
	63	.mode_count = ARRAY_SIZE(pmx_uart1_modes),
	64	.enb_on_reset = 1,
	65	};
	66
	67	struct pmx_dev_mode pmx_uart2_modes[] = {
	68	{
	69	.ids = 0x00,
	70	.mask = PMX_TIMER_1_2_MASK,
	71	},
	72	};
	73
	74	struct pmx_dev pmx_uart2 = {
	75	.name = "uart2",
	76	.modes = pmx_uart2_modes,
	77	.mode_count = ARRAY_SIZE(pmx_uart2_modes),
	78	.enb_on_reset = 1,
	79	};
	80
	81	struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
	82	{
	83	.ids = 0x00,
84	.mask = PMX_UART0_MODEM_MASK,
85	},
86	};
87
88	struct pmx_dev pmx_uart3_4_5 = {
89	.name = "uart3_4_5",
90	.modes = pmx_uart3_4_5_modes,
91	.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
92	.enb_on_reset = 1,
93	};
94
95	struct pmx_dev_mode pmx_fsmc_modes[] = {
96	{
97	.ids = 0x00,
98	.mask = PMX_SSP_CS_MASK,
99	},
100	};
101
102	struct pmx_dev pmx_fsmc = {
103	.name = "fsmc",
104	.modes = pmx_fsmc_modes,
105	.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
106	.enb_on_reset = 1,
107	};
108
109	struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
110	{
111	.ids = 0x00,
112	.mask = PMX_MII_MASK,
113	},
114	};
115
116	struct pmx_dev pmx_rs485_0_1 = {
117	.name = "rs485_0_1",
118	.modes = pmx_rs485_0_1_modes,
119	.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
120	.enb_on_reset = 1,
121	};
122
123	struct pmx_dev_mode pmx_tdm0_modes[] = {
124	{
125	.ids = 0x00,
126	.mask = PMX_MII_MASK,
127	},
128	};
129
130	struct pmx_dev pmx_tdm0 = {
131	.name = "tdm0",
132	.modes = pmx_tdm0_modes,
133	.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
134	.enb_on_reset = 1,
135	};
136
137	/* pmx driver structure */
138	struct pmx_driver pmx_driver = {
139	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
140	};
141
bc4e814e	142	/* Add spear310 specific devices here */
bc4e814e	143
4c18e77f	144	/* spear3xx shared irq */
	145	struct shirq_dev_config shirq_ras1_config[] = {
	146	{
	147	.virq = VIRQ_SMII0,
	148	.status_mask = SMII0_IRQ_MASK,
	149	}, {
	150	.virq = VIRQ_SMII1,
	151	.status_mask = SMII1_IRQ_MASK,
	152	}, {
	153	.virq = VIRQ_SMII2,
	154	.status_mask = SMII2_IRQ_MASK,
	155	}, {
	156	.virq = VIRQ_SMII3,
	157	.status_mask = SMII3_IRQ_MASK,
	158	}, {
	159	.virq = VIRQ_WAKEUP_SMII0,
	160	.status_mask = WAKEUP_SMII0_IRQ_MASK,
	161	}, {
	162	.virq = VIRQ_WAKEUP_SMII1,
	163	.status_mask = WAKEUP_SMII1_IRQ_MASK,
	164	}, {
	165	.virq = VIRQ_WAKEUP_SMII2,
	166	.status_mask = WAKEUP_SMII2_IRQ_MASK,
	167	}, {
	168	.virq = VIRQ_WAKEUP_SMII3,
	169	.status_mask = WAKEUP_SMII3_IRQ_MASK,
	170	},
	171	};
	172
	173	struct spear_shirq shirq_ras1 = {
	174	.irq = IRQ_GEN_RAS_1,
	175	.dev_config = shirq_ras1_config,
	176	.dev_count = ARRAY_SIZE(shirq_ras1_config),
	177	.regs = {
	178	.enb_reg = -1,
	179	.status_reg = INT_STS_MASK_REG,
	180	.status_reg_mask = SHIRQ_RAS1_MASK,
	181	.clear_reg = -1,
	182	},
	183	};
	184
	185	struct shirq_dev_config shirq_ras2_config[] = {
	186	{
	187	.virq = VIRQ_UART1,
	188	.status_mask = UART1_IRQ_MASK,
	189	}, {
	190	.virq = VIRQ_UART2,
	191	.status_mask = UART2_IRQ_MASK,
	192	}, {
	193	.virq = VIRQ_UART3,
	194	.status_mask = UART3_IRQ_MASK,
	195	}, {
	196	.virq = VIRQ_UART4,
	197	.status_mask = UART4_IRQ_MASK,
	198	}, {
	199	.virq = VIRQ_UART5,
	200	.status_mask = UART5_IRQ_MASK,
	201	},
	202	};
	203
	204	struct spear_shirq shirq_ras2 = {
	205	.irq = IRQ_GEN_RAS_2,
	206	.dev_config = shirq_ras2_config,
	207	.dev_count = ARRAY_SIZE(shirq_ras2_config),
208	.regs = {
209	.enb_reg = -1,
210	.status_reg = INT_STS_MASK_REG,
211	.status_reg_mask = SHIRQ_RAS2_MASK,
212	.clear_reg = -1,
213	},
214	};
215
216	struct shirq_dev_config shirq_ras3_config[] = {
217	{
218	.virq = VIRQ_EMI,
219	.status_mask = EMI_IRQ_MASK,
220	},
221	};
222
223	struct spear_shirq shirq_ras3 = {
224	.irq = IRQ_GEN_RAS_3,
225	.dev_config = shirq_ras3_config,
226	.dev_count = ARRAY_SIZE(shirq_ras3_config),
227	.regs = {
228	.enb_reg = -1,
229	.status_reg = INT_STS_MASK_REG,
230	.status_reg_mask = SHIRQ_RAS3_MASK,
231	.clear_reg = -1,
232	},
233	};
234
235	struct shirq_dev_config shirq_intrcomm_ras_config[] = {
236	{
237	.virq = VIRQ_TDM_HDLC,
238	.status_mask = TDM_HDLC_IRQ_MASK,
239	}, {
240	.virq = VIRQ_RS485_0,
241	.status_mask = RS485_0_IRQ_MASK,
242	}, {
243	.virq = VIRQ_RS485_1,
244	.status_mask = RS485_1_IRQ_MASK,
245	},
246	};
247
248	struct spear_shirq shirq_intrcomm_ras = {
249	.irq = IRQ_INTRCOMM_RAS_ARM,
250	.dev_config = shirq_intrcomm_ras_config,
251	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
252	.regs = {
253	.enb_reg = -1,
254	.status_reg = INT_STS_MASK_REG,
255	.status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
256	.clear_reg = -1,
257	},
258	};
259
70f4c0bf	260	/* spear310 routines */
bc4e814e	261	void __init spear310_init(void)
bc4e814e	262	{
4c18e77f	263	void __iomem *base;
	264	int ret = 0;
	265
bc4e814e	266	/* call spear3xx family common init function */
bc4e814e	267	spear3xx_init();
4c18e77f	268
b595076a	269	/* shared irq registration */
4c18e77f	270	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
	271	if (base) {
	272	/* shirq 1 */
	273	shirq_ras1.regs.base = base;
	274	ret = spear_shirq_register(&shirq_ras1);
	275	if (ret)
	276	printk(KERN_ERR "Error registering Shared IRQ 1\n");
	277
	278	/* shirq 2 */
	279	shirq_ras2.regs.base = base;
	280	ret = spear_shirq_register(&shirq_ras2);
	281	if (ret)
	282	printk(KERN_ERR "Error registering Shared IRQ 2\n");
	283
	284	/* shirq 3 */
	285	shirq_ras3.regs.base = base;
	286	ret = spear_shirq_register(&shirq_ras3);
	287	if (ret)
	288	printk(KERN_ERR "Error registering Shared IRQ 3\n");
	289
	290	/* shirq 4 */
	291	shirq_intrcomm_ras.regs.base = base;
	292	ret = spear_shirq_register(&shirq_intrcomm_ras);
	293	if (ret)
	294	printk(KERN_ERR "Error registering Shared IRQ 4\n");
	295	}
bc4e814e	296	}
70f4c0bf	297
	298	void spear310_pmx_init(void)
	299	{
	300	spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
	301	SPEAR310_SOC_CONFIG_SIZE);
	302	}