[linux-2.6-block.git] / arch / arm / mach-s3c64xx / gpiolib.c

/* arch/arm/plat-s3c64xx/gpiolib.c
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
 * S3C64XX - GPIOlib support 
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>

#include <mach/map.h>
#include <mach/gpio.h>

#include <plat/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <mach/regs-gpio.h>

/* GPIO bank summary:
 *
 * Bank	GPIOs	Style	SlpCon	ExtInt Group
 * A	8	4Bit	Yes	1
 * B	7	4Bit	Yes	1
 * C	8	4Bit	Yes	2
 * D	5	4Bit	Yes	3
 * E	5	4Bit	Yes	None
 * F	16	2Bit	Yes	4 [1]
 * G	7	4Bit	Yes	5
 * H	10	4Bit[2]	Yes	6
 * I	16	2Bit	Yes	None
 * J	12	2Bit	Yes	None
 * K	16	4Bit[2]	No	None
 * L	15	4Bit[2] No	None
 * M	6	4Bit	No	IRQ_EINT
 * N	16	2Bit	No	IRQ_EINT
 * O	16	2Bit	Yes	7
 * P	15	2Bit	Yes	8
 * Q	9	2Bit	Yes	9
 *
 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
 * [2] BANK has two control registers, GPxCON0 and GPxCON1
 */

static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
	.cfg_eint	= 7,
	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
	.cfg_eint	= 3,
	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
{
	return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
}

static struct s3c_gpio_chip gpio_4bit[] = {
	{
		.base	= S3C64XX_GPA_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPA(0),
			.ngpio	= S3C64XX_GPIO_A_NR,
			.label	= "GPA",
		},
	}, {
		.base	= S3C64XX_GPB_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPB(0),
			.ngpio	= S3C64XX_GPIO_B_NR,
			.label	= "GPB",
		},
	}, {
		.base	= S3C64XX_GPC_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPC(0),
			.ngpio	= S3C64XX_GPIO_C_NR,
			.label	= "GPC",
		},
	}, {
		.base	= S3C64XX_GPD_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPD(0),
			.ngpio	= S3C64XX_GPIO_D_NR,
			.label	= "GPD",
		},
	}, {
		.base	= S3C64XX_GPE_BASE,
		.config	= &gpio_4bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPE(0),
			.ngpio	= S3C64XX_GPIO_E_NR,
			.label	= "GPE",
		},
	}, {
		.base	= S3C64XX_GPG_BASE,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPG(0),
			.ngpio	= S3C64XX_GPIO_G_NR,
			.label	= "GPG",
		},
	}, {
		.base	= S3C64XX_GPM_BASE,
		.config	= &gpio_4bit_cfg_eint0011,
		.chip	= {
			.base	= S3C64XX_GPM(0),
			.ngpio	= S3C64XX_GPIO_M_NR,
			.label	= "GPM",
			.to_irq = s3c64xx_gpio2int_gpm,
		},
	},
};

int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
{
	return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
}

static struct s3c_gpio_chip gpio_4bit2[] = {
	{
		.base	= S3C64XX_GPH_BASE + 0x4,
		.config	= &gpio_4bit_cfg_eint0111,
		.chip	= {
			.base	= S3C64XX_GPH(0),
			.ngpio	= S3C64XX_GPIO_H_NR,
			.label	= "GPH",
		},
	}, {
		.base	= S3C64XX_GPK_BASE + 0x4,
		.config	= &gpio_4bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPK(0),
			.ngpio	= S3C64XX_GPIO_K_NR,
			.label	= "GPK",
		},
	}, {
		.base	= S3C64XX_GPL_BASE + 0x4,
		.config	= &gpio_4bit_cfg_eint0011,
		.chip	= {
			.base	= S3C64XX_GPL(0),
			.ngpio	= S3C64XX_GPIO_L_NR,
			.label	= "GPL",
			.to_irq = s3c64xx_gpio2int_gpl,
		},
	},
};

static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
	.cfg_eint	= 2,
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
	.cfg_eint	= 3,
	.set_config	= s3c_gpio_setcfg_s3c24xx,
	.set_pull	= s3c_gpio_setpull_updown,
	.get_pull	= s3c_gpio_getpull_updown,
};

int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
{
	return IRQ_EINT(0) + pin;
}

static struct s3c_gpio_chip gpio_2bit[] = {
	{
		.base	= S3C64XX_GPF_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPF(0),
			.ngpio	= S3C64XX_GPIO_F_NR,
			.label	= "GPF",
		},
	}, {
		.base	= S3C64XX_GPI_BASE,
		.config	= &gpio_2bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPI(0),
			.ngpio	= S3C64XX_GPIO_I_NR,
			.label	= "GPI",
		},
	}, {
		.base	= S3C64XX_GPJ_BASE,
		.config	= &gpio_2bit_cfg_noint,
		.chip	= {
			.base	= S3C64XX_GPJ(0),
			.ngpio	= S3C64XX_GPIO_J_NR,
			.label	= "GPJ",
		},
	}, {
		.base	= S3C64XX_GPN_BASE,
		.config	= &gpio_2bit_cfg_eint10,
		.chip	= {
			.base	= S3C64XX_GPN(0),
			.ngpio	= S3C64XX_GPIO_N_NR,
			.label	= "GPN",
			.to_irq = s3c64xx_gpio2int_gpn,
		},
	}, {
		.base	= S3C64XX_GPO_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPO(0),
			.ngpio	= S3C64XX_GPIO_O_NR,
			.label	= "GPO",
		},
	}, {
		.base	= S3C64XX_GPP_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPP(0),
			.ngpio	= S3C64XX_GPIO_P_NR,
			.label	= "GPP",
		},
	}, {
		.base	= S3C64XX_GPQ_BASE,
		.config	= &gpio_2bit_cfg_eint11,
		.chip	= {
			.base	= S3C64XX_GPQ(0),
			.ngpio	= S3C64XX_GPIO_Q_NR,
			.label	= "GPQ",
		},
	},
};

static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
{
	chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
}

static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
				       int nr_chips,
				       void (*fn)(struct s3c_gpio_chip *))
{
	for (; nr_chips > 0; nr_chips--, chips++) {
		if (fn)
			(fn)(chips);
		s3c_gpiolib_add(chips);
	}
}

static __init int s3c64xx_gpiolib_init(void)
{
	s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
			    samsung_gpiolib_add_4bit);

	s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
			    samsung_gpiolib_add_4bit2);

	s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
			    s3c64xx_gpiolib_add_2bit);

	return 0;
}

core_initcall(s3c64xx_gpiolib_init);
Commit	Line	Data
89d043c3 BD	1	/* arch/arm/plat-s3c64xx/gpiolib.c
	2	*
	3	* Copyright 2008 Openmoko, Inc.
	4	* Copyright 2008 Simtec Electronics
	5	* Ben Dooks <ben@simtec.co.uk>
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* S3C64XX - GPIOlib support
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/irq.h>
	17	#include <linux/io.h>
	18
	19	#include <mach/map.h>
	20	#include <mach/gpio.h>
	21
e856bb1f	22	#include <plat/gpio-core.h>
21b23664 BD	23	#include <plat/gpio-cfg.h>
21b23664 BD	24	#include <plat/gpio-cfg-helpers.h>
3501c9ae	25	#include <mach/regs-gpio.h>
89d043c3 BD	26
	27	/* GPIO bank summary:
	28	*
	29	* Bank GPIOs Style SlpCon ExtInt Group
	30	* A 8 4Bit Yes 1
	31	* B 7 4Bit Yes 1
	32	* C 8 4Bit Yes 2
	33	* D 5 4Bit Yes 3
	34	* E 5 4Bit Yes None
	35	* F 16 2Bit Yes 4 [1]
	36	* G 7 4Bit Yes 5
	37	* H 10 4Bit[2] Yes 6
	38	* I 16 2Bit Yes None
	39	* J 12 2Bit Yes None
	40	* K 16 4Bit[2] No None
	41	* L 15 4Bit[2] No None
	42	* M 6 4Bit No IRQ_EINT
	43	* N 16 2Bit No IRQ_EINT
	44	* O 16 2Bit Yes 7
	45	* P 15 2Bit Yes 8
	46	* Q 9 2Bit Yes 9
	47	*
	48	* [1] BANKF pins 14,15 do not form part of the external interrupt sources
	49	* [2] BANK has two control registers, GPxCON0 and GPxCON1
	50	*/
	51
21b23664 BD	52	static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
	53	.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
	54	.set_pull = s3c_gpio_setpull_updown,
	55	.get_pull = s3c_gpio_getpull_updown,
	56	};
	57
	58	static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
	59	.cfg_eint = 7,
	60	.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
	61	.set_pull = s3c_gpio_setpull_updown,
	62	.get_pull = s3c_gpio_getpull_updown,
	63	};
	64
	65	static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
	66	.cfg_eint = 3,
	67	.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
	68	.set_pull = s3c_gpio_setpull_updown,
	69	.get_pull = s3c_gpio_getpull_updown,
	70	};
	71
6a88e983 MC	72	int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
	73	{
	74	return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
	75	}
	76
89d043c3 BD	77	static struct s3c_gpio_chip gpio_4bit[] = {
	78	{
	79	.base = S3C64XX_GPA_BASE,
21b23664	80	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	81	.chip = {
	82	.base = S3C64XX_GPA(0),
	83	.ngpio = S3C64XX_GPIO_A_NR,
	84	.label = "GPA",
	85	},
	86	}, {
	87	.base = S3C64XX_GPB_BASE,
21b23664	88	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	89	.chip = {
	90	.base = S3C64XX_GPB(0),
	91	.ngpio = S3C64XX_GPIO_B_NR,
	92	.label = "GPB",
	93	},
	94	}, {
	95	.base = S3C64XX_GPC_BASE,
21b23664	96	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	97	.chip = {
	98	.base = S3C64XX_GPC(0),
	99	.ngpio = S3C64XX_GPIO_C_NR,
	100	.label = "GPC",
	101	},
	102	}, {
	103	.base = S3C64XX_GPD_BASE,
21b23664	104	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	105	.chip = {
	106	.base = S3C64XX_GPD(0),
	107	.ngpio = S3C64XX_GPIO_D_NR,
	108	.label = "GPD",
	109	},
	110	}, {
	111	.base = S3C64XX_GPE_BASE,
21b23664	112	.config = &gpio_4bit_cfg_noint,
89d043c3 BD	113	.chip = {
	114	.base = S3C64XX_GPE(0),
	115	.ngpio = S3C64XX_GPIO_E_NR,
	116	.label = "GPE",
	117	},
	118	}, {
	119	.base = S3C64XX_GPG_BASE,
21b23664	120	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	121	.chip = {
	122	.base = S3C64XX_GPG(0),
	123	.ngpio = S3C64XX_GPIO_G_NR,
	124	.label = "GPG",
	125	},
	126	}, {
	127	.base = S3C64XX_GPM_BASE,
21b23664	128	.config = &gpio_4bit_cfg_eint0011,
89d043c3 BD	129	.chip = {
	130	.base = S3C64XX_GPM(0),
	131	.ngpio = S3C64XX_GPIO_M_NR,
	132	.label = "GPM",
6a88e983	133	.to_irq = s3c64xx_gpio2int_gpm,
89d043c3 BD	134	},
	135	},
	136	};
	137
6a88e983 MC	138	int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
	139	{
	140	return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
	141	}
	142
89d043c3 BD	143	static struct s3c_gpio_chip gpio_4bit2[] = {
	144	{
	145	.base = S3C64XX_GPH_BASE + 0x4,
21b23664	146	.config = &gpio_4bit_cfg_eint0111,
89d043c3 BD	147	.chip = {
	148	.base = S3C64XX_GPH(0),
	149	.ngpio = S3C64XX_GPIO_H_NR,
	150	.label = "GPH",
	151	},
	152	}, {
	153	.base = S3C64XX_GPK_BASE + 0x4,
21b23664	154	.config = &gpio_4bit_cfg_noint,
89d043c3 BD	155	.chip = {
	156	.base = S3C64XX_GPK(0),
	157	.ngpio = S3C64XX_GPIO_K_NR,
	158	.label = "GPK",
	159	},
	160	}, {
	161	.base = S3C64XX_GPL_BASE + 0x4,
21b23664	162	.config = &gpio_4bit_cfg_eint0011,
89d043c3 BD	163	.chip = {
	164	.base = S3C64XX_GPL(0),
	165	.ngpio = S3C64XX_GPIO_L_NR,
	166	.label = "GPL",
6a88e983	167	.to_irq = s3c64xx_gpio2int_gpl,
89d043c3 BD	168	},
	169	},
	170	};
	171
21b23664 BD	172	static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
	173	.set_config = s3c_gpio_setcfg_s3c24xx,
	174	.set_pull = s3c_gpio_setpull_updown,
	175	.get_pull = s3c_gpio_getpull_updown,
	176	};
	177
	178	static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
	179	.cfg_eint = 2,
	180	.set_config = s3c_gpio_setcfg_s3c24xx,
	181	.set_pull = s3c_gpio_setpull_updown,
	182	.get_pull = s3c_gpio_getpull_updown,
	183	};
	184
	185	static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
	186	.cfg_eint = 3,
	187	.set_config = s3c_gpio_setcfg_s3c24xx,
	188	.set_pull = s3c_gpio_setpull_updown,
	189	.get_pull = s3c_gpio_getpull_updown,
	190	};
	191
0b495737 MS	192	int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
	193	{
	194	return IRQ_EINT(0) + pin;
	195	}
	196
89d043c3 BD	197	static struct s3c_gpio_chip gpio_2bit[] = {
	198	{
	199	.base = S3C64XX_GPF_BASE,
21b23664	200	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	201	.chip = {
	202	.base = S3C64XX_GPF(0),
	203	.ngpio = S3C64XX_GPIO_F_NR,
	204	.label = "GPF",
	205	},
	206	}, {
	207	.base = S3C64XX_GPI_BASE,
21b23664	208	.config = &gpio_2bit_cfg_noint,
89d043c3 BD	209	.chip = {
	210	.base = S3C64XX_GPI(0),
	211	.ngpio = S3C64XX_GPIO_I_NR,
	212	.label = "GPI",
	213	},
	214	}, {
	215	.base = S3C64XX_GPJ_BASE,
21b23664	216	.config = &gpio_2bit_cfg_noint,
89d043c3 BD	217	.chip = {
	218	.base = S3C64XX_GPJ(0),
	219	.ngpio = S3C64XX_GPIO_J_NR,
	220	.label = "GPJ",
	221	},
	222	}, {
	223	.base = S3C64XX_GPN_BASE,
21b23664	224	.config = &gpio_2bit_cfg_eint10,
89d043c3 BD	225	.chip = {
	226	.base = S3C64XX_GPN(0),
	227	.ngpio = S3C64XX_GPIO_N_NR,
	228	.label = "GPN",
0b495737	229	.to_irq = s3c64xx_gpio2int_gpn,
89d043c3 BD	230	},
	231	}, {
	232	.base = S3C64XX_GPO_BASE,
21b23664	233	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	234	.chip = {
	235	.base = S3C64XX_GPO(0),
	236	.ngpio = S3C64XX_GPIO_O_NR,
	237	.label = "GPO",
	238	},
	239	}, {
	240	.base = S3C64XX_GPP_BASE,
21b23664	241	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	242	.chip = {
	243	.base = S3C64XX_GPP(0),
	244	.ngpio = S3C64XX_GPIO_P_NR,
	245	.label = "GPP",
	246	},
	247	}, {
	248	.base = S3C64XX_GPQ_BASE,
21b23664	249	.config = &gpio_2bit_cfg_eint11,
89d043c3 BD	250	.chip = {
	251	.base = S3C64XX_GPQ(0),
	252	.ngpio = S3C64XX_GPIO_Q_NR,
	253	.label = "GPQ",
	254	},
	255	},
	256	};
	257
d87964c4 BD	258	static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
	259	{
	260	chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
89d043c3 BD	261	}
	262
	263	static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
	264	int nr_chips,
	265	void (fn)(struct s3c_gpio_chip ))
	266	{
	267	for (; nr_chips > 0; nr_chips--, chips++) {
	268	if (fn)
	269	(fn)(chips);
	270	s3c_gpiolib_add(chips);
	271	}
	272	}
	273
	274	static __init int s3c64xx_gpiolib_init(void)
	275	{
	276	s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
1f323cfd	277	samsung_gpiolib_add_4bit);
89d043c3 BD	278
89d043c3 BD	279	s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
1f323cfd	280	samsung_gpiolib_add_4bit2);
89d043c3	281
d87964c4 BD	282	s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
d87964c4 BD	283	s3c64xx_gpiolib_add_2bit);
89d043c3 BD	284
	285	return 0;
	286	}
	287
24d40767	288	core_initcall(s3c64xx_gpiolib_init);