ARM: S3C24XX: fix building without PM_SLEEP
[linux-2.6-block.git] / arch / arm / mach-s3c24xx / s3c2412.c
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fd4e5a5b 1/*
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2 * Copyright (c) 2006 Simtec Electronics
3 * Ben Dooks <ben@simtec.co.uk>
4 *
5 * http://armlinux.simtec.co.uk/.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
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10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
e425382e 18#include <linux/clk.h>
eca8c242 19#include <linux/delay.h>
4a858cfc 20#include <linux/device.h>
bb072c3c 21#include <linux/syscore_ops.h>
b6d1f542 22#include <linux/serial_core.h>
334a1c70 23#include <linux/serial_s3c.h>
68d9ab39 24#include <linux/platform_device.h>
fced80c7 25#include <linux/io.h>
7b6d864b 26#include <linux/reboot.h>
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27
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/irq.h>
31
c84cbb24 32#include <asm/proc-fns.h>
68d9ab39 33#include <asm/irq.h>
9f97da78 34#include <asm/system_misc.h>
68d9ab39 35
fd4e5a5b 36#include <mach/hardware.h>
a09e64fb 37#include <mach/regs-clock.h>
fd4e5a5b 38#include <mach/regs-gpio.h>
68d9ab39 39
a2b7ba9c 40#include <plat/cpu.h>
fd4e5a5b 41#include <plat/cpu-freq.h>
a2b7ba9c 42#include <plat/devs.h>
ef3f2dd4 43#include <plat/nand-core.h>
fd4e5a5b 44#include <plat/pm.h>
fd4e5a5b 45#include <plat/regs-spi.h>
fd4e5a5b 46
d8fdec16 47#include "common.h"
b4353784 48#include "regs-dsc.h"
14cce0e7 49#include "s3c2412-power.h"
b4353784 50
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51#ifndef CONFIG_CPU_S3C2412_ONLY
52void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO;
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53
54static inline void s3c2412_init_gpio2(void)
55{
56 s3c24xx_va_gpio2 = S3C24XX_VA_GPIO + 0x10;
57}
58#else
59#define s3c2412_init_gpio2() do { } while(0)
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60#endif
61
62/* Initial IO mappings */
63
64static struct map_desc s3c2412_iodesc[] __initdata = {
65 IODESC_ENT(CLKPWR),
68d9ab39 66 IODESC_ENT(TIMER),
68d9ab39 67 IODESC_ENT(WATCHDOG),
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68 {
69 .virtual = (unsigned long)S3C2412_VA_SSMC,
70 .pfn = __phys_to_pfn(S3C2412_PA_SSMC),
71 .length = SZ_1M,
72 .type = MT_DEVICE,
73 },
74 {
75 .virtual = (unsigned long)S3C2412_VA_EBI,
76 .pfn = __phys_to_pfn(S3C2412_PA_EBI),
77 .length = SZ_1M,
78 .type = MT_DEVICE,
79 },
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80};
81
82/* uart registration process */
83
84void __init s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no)
85{
86 s3c24xx_init_uartdevs("s3c2412-uart", s3c2410_uart_resources, cfg, no);
87
88 /* rename devices that are s3c2412/s3c2413 specific */
89 s3c_device_sdi.name = "s3c2412-sdi";
72d70d06 90 s3c_device_lcd.name = "s3c2412-lcd";
ef3f2dd4 91 s3c_nand_setname("s3c2412-nand");
e903382c 92
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93 /* alter IRQ of SDI controller */
94
95 s3c_device_sdi.resource[1].start = IRQ_S3C2412_SDI;
96 s3c_device_sdi.resource[1].end = IRQ_S3C2412_SDI;
97
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98 /* spi channel related changes, s3c2412/13 specific */
99 s3c_device_spi0.name = "s3c2412-spi";
100 s3c_device_spi0.resource[0].end = S3C24XX_PA_SPI + 0x24;
101 s3c_device_spi1.name = "s3c2412-spi";
102 s3c_device_spi1.resource[0].start = S3C24XX_PA_SPI + S3C2412_SPI1;
103 s3c_device_spi1.resource[0].end = S3C24XX_PA_SPI + S3C2412_SPI1 + 0x24;
104
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105}
106
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107/* s3c2412_idle
108 *
109 * use the standard idle call by ensuring the idle mode
110 * in power config, then issuing the idle co-processor
111 * instruction
112*/
113
114static void s3c2412_idle(void)
115{
116 unsigned long tmp;
117
118 /* ensure our idle mode is to go to idle */
119
120 tmp = __raw_readl(S3C2412_PWRCFG);
121 tmp &= ~S3C2412_PWRCFG_STANDBYWFI_MASK;
122 tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE;
123 __raw_writel(tmp, S3C2412_PWRCFG);
124
125 cpu_do_idle();
126}
127
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128/* s3c2412_map_io
129 *
130 * register the standard cpu IO areas, and any passed in from the
131 * machine specific initialisation.
132*/
133
74b265d4 134void __init s3c2412_map_io(void)
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135{
136 /* move base of IO */
137
50dedf16 138 s3c2412_init_gpio2();
68d9ab39 139
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140 /* set our idle function */
141
92311272 142 arm_pm_idle = s3c2412_idle;
c84cbb24 143
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144 /* register our io-tables */
145
146 iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
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147}
148
4a858cfc 149/* need to register the subsystem before we actually register the device, and
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150 * we also need to ensure that it has been initialised before any of the
151 * drivers even try to use it (even if not on an s3c2412 based system)
152 * as a driver which may support both 2410 and 2440 may try and use it.
153*/
154
4a858cfc 155struct bus_type s3c2412_subsys = {
af5ca3f4 156 .name = "s3c2412-core",
4a858cfc 157 .dev_name = "s3c2412-core",
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158};
159
160static int __init s3c2412_core_init(void)
161{
4a858cfc 162 return subsys_system_register(&s3c2412_subsys, NULL);
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163}
164
165core_initcall(s3c2412_core_init);
166
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167static struct device s3c2412_dev = {
168 .bus = &s3c2412_subsys,
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169};
170
171int __init s3c2412_init(void)
172{
173 printk("S3C2412: Initialising architecture\n");
174
4f506daf 175#ifdef CONFIG_PM_SLEEP
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176 register_syscore_ops(&s3c2412_pm_syscore_ops);
177 register_syscore_ops(&s3c24xx_irq_syscore_ops);
d8fdec16 178#endif
bb072c3c 179
4a858cfc 180 return device_register(&s3c2412_dev);
68d9ab39 181}