[linux-2.6-block.git] / arch / arm / mach-s3c2412 / mach-jive.c

/* linux/arch/arm/mach-s3c2410/mach-jive.c
 *
 * Copyright 2007 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>

#include <video/ili9320.h>

#include <linux/spi/spi.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/plat-s3c/regs-serial.h>
#include <asm/plat-s3c/nand.h>
#include <asm/plat-s3c/iic.h>

#include <asm/arch/regs-power.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>
#include <asm/arch/spi-gpio.h>
#include <asm/arch/fb.h>

#include <asm/mach-types.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>
#include <asm/plat-s3c24xx/pm.h>
#include <asm/plat-s3c24xx/udc.h>

static struct map_desc jive_iodesc[] __initdata = {
};

#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg jive_uartcfgs[] = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
	}
};

/* Jive flash assignment
 *
 * 0x00000000-0x00028000 : uboot
 * 0x00028000-0x0002c000 : uboot env
 * 0x0002c000-0x00030000 : spare
 * 0x00030000-0x00200000 : zimage A
 * 0x00200000-0x01600000 : cramfs A
 * 0x01600000-0x017d0000 : zimage B
 * 0x017d0000-0x02bd0000 : cramfs B
 * 0x02bd0000-0x03fd0000 : yaffs
 */
static struct mtd_partition jive_imageA_nand_part[] = {

#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
	/* Don't allow access to the bootloader from linux */
	{
		.name           = "uboot",
		.offset         = 0,
		.size           = (160 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	},

	/* spare */
        {
                .name           = "spare",
                .offset         = (176 * SZ_1K),
                .size           = (16 * SZ_1K),
        },
#endif

	/* booted images */
        {
		.name		= "kernel (ro)",
		.offset		= (192 * SZ_1K),
		.size		= (SZ_2M) - (192 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
        }, {
                .name           = "root (ro)",
                .offset         = (SZ_2M),
                .size           = (20 * SZ_1M),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
        },

	/* yaffs */
	{
		.name		= "yaffs",
		.offset		= (44 * SZ_1M),
		.size		= (20 * SZ_1M),
	},

	/* bootloader environment */
	{
                .name		= "env",
		.offset		= (160 * SZ_1K),
		.size		= (16 * SZ_1K),
	},

	/* upgrade images */
        {
		.name		= "zimage",
		.offset		= (22 * SZ_1M),
		.size		= (2 * SZ_1M) - (192 * SZ_1K),
        }, {
		.name		= "cramfs",
		.offset		= (24 * SZ_1M) - (192*SZ_1K),
		.size		= (20 * SZ_1M),
        },
};

static struct mtd_partition jive_imageB_nand_part[] = {

#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
	/* Don't allow access to the bootloader from linux */
	{
		.name           = "uboot",
		.offset         = 0,
		.size           = (160 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	},

	/* spare */
        {
                .name           = "spare",
                .offset         = (176 * SZ_1K),
                .size           = (16 * SZ_1K),
        },
#endif

	/* booted images */
        {
		.name           = "kernel (ro)",
		.offset         = (22 * SZ_1M),
		.size           = (2 * SZ_1M) - (192 * SZ_1K),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
        },
	{
		.name		= "root (ro)",
		.offset		= (24 * SZ_1M) - (192 * SZ_1K),
                .size		= (20 * SZ_1M),
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	},

	/* yaffs */
	{
		.name		= "yaffs",
		.offset		= (44 * SZ_1M),
		.size		= (20 * SZ_1M),
        },

	/* bootloader environment */
	{
		.name		= "env",
		.offset		= (160 * SZ_1K),
		.size		= (16 * SZ_1K),
	},

	/* upgrade images */
	{
		.name		= "zimage",
		.offset		= (192 * SZ_1K),
		.size		= (2 * SZ_1M) - (192 * SZ_1K),
        }, {
		.name		= "cramfs",
		.offset		= (2 * SZ_1M),
		.size		= (20 * SZ_1M),
        },
};

static struct s3c2410_nand_set jive_nand_sets[] = {
	[0] = {
		.name           = "flash",
		.nr_chips       = 1,
		.nr_partitions  = ARRAY_SIZE(jive_imageA_nand_part),
		.partitions     = jive_imageA_nand_part,
	},
};

static struct s3c2410_platform_nand jive_nand_info = {
	/* set taken from osiris nand timings, possibly still conservative */
	.tacls		= 30,
	.twrph0		= 55,
	.twrph1		= 40,
	.sets		= jive_nand_sets,
	.nr_sets	= ARRAY_SIZE(jive_nand_sets),
};

static int __init jive_mtdset(char *options)
{
	struct s3c2410_nand_set *nand = &jive_nand_sets[0];
	unsigned long set;

	if (options == NULL || options[0] == '\0')
		return 0;

	if (strict_strtoul(options, 10, &set)) {
		printk(KERN_ERR "failed to parse mtdset=%s\n", options);
		return 0;
	}

	switch (set) {
	case 1:
		nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
		nand->partitions = jive_imageB_nand_part;
	case 0:
		/* this is already setup in the nand info */
		break;
	default:
		printk(KERN_ERR "Unknown mtd set %ld specified,"
		       "using default.", set);
	}

	return 0;
}

/* parse the mtdset= option given to the kernel command line */
__setup("mtdset=", jive_mtdset);

/* LCD timing and setup */

#define LCD_XRES	 (240)
#define LCD_YRES	 (320)
#define LCD_LEFT_MARGIN  (12)
#define LCD_RIGHT_MARGIN (12)
#define LCD_LOWER_MARGIN (12)
#define LCD_UPPER_MARGIN (12)
#define LCD_VSYNC	 (2)
#define LCD_HSYNC	 (2)

#define LCD_REFRESH	 (60)

#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)

struct s3c2410fb_display jive_vgg2432a4_display[] = {
	[0] = {
		.width		= LCD_XRES,
		.height		= LCD_YRES,
		.xres		= LCD_XRES,
		.yres		= LCD_YRES,
		.left_margin	= LCD_LEFT_MARGIN,
		.right_margin	= LCD_RIGHT_MARGIN,
		.upper_margin	= LCD_UPPER_MARGIN,
		.lower_margin	= LCD_LOWER_MARGIN,
		.hsync_len	= LCD_HSYNC,
		.vsync_len	= LCD_VSYNC,

		.pixclock	= (1000000000000LL /
				   (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),

		.bpp		= 16,
		.type		= (S3C2410_LCDCON1_TFT16BPP |
				   S3C2410_LCDCON1_TFT),

		.lcdcon5	= (S3C2410_LCDCON5_FRM565 |
				   S3C2410_LCDCON5_INVVLINE |
				   S3C2410_LCDCON5_INVVFRAME |
				   S3C2410_LCDCON5_INVVDEN |
				   S3C2410_LCDCON5_PWREN),
	},
};

/* todo - put into gpio header */

#define S3C2410_GPCCON_MASK(x)	(3 << ((x) * 2))
#define S3C2410_GPDCON_MASK(x)	(3 << ((x) * 2))

struct s3c2410fb_mach_info jive_lcd_config = {
	.displays	 = jive_vgg2432a4_display,
	.num_displays	 = ARRAY_SIZE(jive_vgg2432a4_display),
	.default_display = 0,

	/* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
	 * and disable the pull down resistors on pins we are using for LCD
	 * data. */

	.gpcup		= (0xf << 1) | (0x3f << 10),

	.gpccon		= (S3C2410_GPC1_VCLK   | S3C2410_GPC2_VLINE |
			   S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
			   S3C2410_GPC10_VD2   | S3C2410_GPC11_VD3 |
			   S3C2410_GPC12_VD4   | S3C2410_GPC13_VD5 |
			   S3C2410_GPC14_VD6   | S3C2410_GPC15_VD7),

	.gpccon_mask	= (S3C2410_GPCCON_MASK(1)  | S3C2410_GPCCON_MASK(2)  |
			   S3C2410_GPCCON_MASK(3)  | S3C2410_GPCCON_MASK(4)  |
			   S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
			   S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
			   S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),

	.gpdup		= (0x3f << 2) | (0x3f << 10),

	.gpdcon		= (S3C2410_GPD2_VD10  | S3C2410_GPD3_VD11 |
			   S3C2410_GPD4_VD12  | S3C2410_GPD5_VD13 |
			   S3C2410_GPD6_VD14  | S3C2410_GPD7_VD15 |
			   S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
			   S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
			   S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),

	.gpdcon_mask	= (S3C2410_GPDCON_MASK(2)  | S3C2410_GPDCON_MASK(3) |
			   S3C2410_GPDCON_MASK(4)  | S3C2410_GPDCON_MASK(5) |
			   S3C2410_GPDCON_MASK(6)  | S3C2410_GPDCON_MASK(7) |
			   S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
			   S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
			   S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
};

/* ILI9320 support. */

static void jive_lcm_reset(unsigned int set)
{
	printk(KERN_DEBUG "%s(%d)\n", __func__, set);

	s3c2410_gpio_setpin(S3C2410_GPG13, set);
	s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
}

#undef LCD_UPPER_MARGIN
#define LCD_UPPER_MARGIN 2

static struct ili9320_platdata jive_lcm_config = {
	.hsize		= LCD_XRES,
	.vsize		= LCD_YRES,

	.reset		= jive_lcm_reset,
	.suspend	= ILI9320_SUSPEND_DEEP,

	.entry_mode	= ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
	.display2	= (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
			   ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
	.display3	= 0x0,
	.display4	= 0x0,
	.rgb_if1	= (ILI9320_RGBIF1_RIM_RGB18 |
			   ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
	.rgb_if2	= ILI9320_RGBIF2_DPL,
	.interface2	= 0x0,
	.interface3	= 0x3,
	.interface4	= (ILI9320_INTERFACE4_RTNE(16) |
			   ILI9320_INTERFACE4_DIVE(1)),
	.interface5	= 0x0,
	.interface6	= 0x0,
};

/* LCD SPI support */

static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
{
	s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
}

static struct s3c2410_spigpio_info jive_lcd_spi = {
	.bus_num	= 0,
	.pin_clk	= S3C2410_GPG8,
	.pin_mosi	= S3C2410_GPB8,
	.chip_select	= jive_lcd_spi_chipselect,
};

static struct platform_device jive_device_lcdspi = {
	.name		= "s3c24xx-spi-gpio",
	.id		= 1,
	.num_resources  = 0,
	.dev.platform_data = &jive_lcd_spi,
};

/* WM8750 audio code SPI definition */

static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
{
	s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
}

static struct s3c2410_spigpio_info jive_wm8750_spi = {
	.bus_num	= 2,
	.pin_clk	= S3C2410_GPB4,
	.pin_mosi	= S3C2410_GPB9,
	.chip_select	= jive_wm8750_chipselect,
};

static struct platform_device jive_device_wm8750 = {
	.name		= "s3c24xx-spi-gpio",
	.id		= 2,
	.num_resources  = 0,
	.dev.platform_data = &jive_wm8750_spi,
};

/* JIVE SPI devices. */

static struct spi_board_info __initdata jive_spi_devs[] = {
	[0] = {
		.modalias	= "VGG2432A4",
		.bus_num	= 1,
		.chip_select	= 0,
		.mode		= SPI_MODE_3,	/* CPOL=1, CPHA=1 */
		.max_speed_hz	= 100000,
		.platform_data	= &jive_lcm_config,
	}, {
		.modalias	= "WM8750",
		.bus_num	= 2,
		.chip_select	= 0,
		.mode		= SPI_MODE_0,	/* CPOL=0, CPHA=0 */
		.max_speed_hz	= 100000,
	},
};

/* I2C bus and device configuration. */

static struct s3c2410_platform_i2c jive_i2c_cfg = {
	.max_freq	= 80 * 1000,
	.bus_freq	= 50 * 1000,
	.flags		= S3C_IICFLG_FILTER,
	.sda_delay	= 2,
};

static struct i2c_board_info jive_i2c_devs[] = {
	[0] = {
		I2C_BOARD_INFO("lis302dl", 0x1c),
		.irq	= IRQ_EINT14,
	},
};

/* The platform devices being used. */

static struct platform_device *jive_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_rtc,
	&s3c_device_wdt,
	&s3c_device_i2c,
	&s3c_device_lcd,
	&jive_device_lcdspi,
	&jive_device_wm8750,
	&s3c_device_nand,
	&s3c_device_usbgadget,
};

static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
	.vbus_pin	= S3C2410_GPG1,		/* detect is on GPG1 */
};

/* Jive power management device */

#ifdef CONFIG_PM
static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	/* Write the magic value u-boot uses to check for resume into
	 * the INFORM0 register, and ensure INFORM1 is set to the
	 * correct address to resume from. */

	__raw_writel(0x2BED, S3C2412_INFORM0);
	__raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);

	return 0;
}

static int jive_pm_resume(struct sys_device *sd)
{
	__raw_writel(0x0, S3C2412_INFORM0);
	return 0;
}

#else
#define jive_pm_suspend NULL
#define jive_pm_resume NULL
#endif

static struct sysdev_class jive_pm_sysclass = {
	.name		= "jive-pm",
	.suspend	= jive_pm_suspend,
	.resume		= jive_pm_resume,
};

static struct sys_device jive_pm_sysdev = {
	.cls		= &jive_pm_sysclass,
};

static void __init jive_map_io(void)
{
	s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
	s3c24xx_init_clocks(12000000);
	s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
}

static void __init jive_machine_init(void)
{
	/* register system devices for managing low level suspend */

	sysdev_class_register(&jive_pm_sysclass);
	sysdev_register(&jive_pm_sysdev);

	/* write our sleep configurations for the IO. Pull down all unused
	 * IO, ensure that we have turned off all peripherals we do not
	 * need, and configure the ones we do need. */

	/* Port B sleep */

	__raw_writel(S3C2412_SLPCON_IN(0)   |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_HIGH(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_HIGH(7) |
		     S3C2412_SLPCON_PULL(8) |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);

	/* Port C sleep */

	__raw_writel(S3C2412_SLPCON_PULL(0) |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_PULL(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_LOW(6)  |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_PULL(7) |
		     S3C2412_SLPCON_PULL(8) |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_PULL(10) |
		     S3C2412_SLPCON_PULL(11) |
		     S3C2412_SLPCON_PULL(12) |
		     S3C2412_SLPCON_PULL(13) |
		     S3C2412_SLPCON_PULL(14) |
		     S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);

	/* Port D sleep */

	__raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);

	/* Port F sleep */

	__raw_writel(S3C2412_SLPCON_LOW(0)  |
		     S3C2412_SLPCON_LOW(1)  |
		     S3C2412_SLPCON_LOW(2)  |
		     S3C2412_SLPCON_EINT(3) |
		     S3C2412_SLPCON_EINT(4) |
		     S3C2412_SLPCON_EINT(5) |
		     S3C2412_SLPCON_EINT(6) |
		     S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);

	/* Port G sleep */

	__raw_writel(S3C2412_SLPCON_IN(0)    |
		     S3C2412_SLPCON_IN(1)    |
		     S3C2412_SLPCON_IN(2)    |
		     S3C2412_SLPCON_IN(3)    |
		     S3C2412_SLPCON_IN(4)    |
		     S3C2412_SLPCON_IN(5)    |
		     S3C2412_SLPCON_IN(6)    |
		     S3C2412_SLPCON_IN(7)    |
		     S3C2412_SLPCON_PULL(8)  |
		     S3C2412_SLPCON_PULL(9)  |
		     S3C2412_SLPCON_IN(10)   |
		     S3C2412_SLPCON_PULL(11) |
		     S3C2412_SLPCON_PULL(12) |
		     S3C2412_SLPCON_PULL(13) |
		     S3C2412_SLPCON_IN(14)   |
		     S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);

	/* Port H sleep */

	__raw_writel(S3C2412_SLPCON_PULL(0) |
		     S3C2412_SLPCON_PULL(1) |
		     S3C2412_SLPCON_PULL(2) |
		     S3C2412_SLPCON_PULL(3) |
		     S3C2412_SLPCON_PULL(4) |
		     S3C2412_SLPCON_PULL(5) |
		     S3C2412_SLPCON_PULL(6) |
		     S3C2412_SLPCON_IN(7)   |
		     S3C2412_SLPCON_IN(8)   |
		     S3C2412_SLPCON_PULL(9) |
		     S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);

	/* initialise the power management now we've setup everything. */

	s3c2410_pm_init();

	s3c_device_nand.dev.platform_data = &jive_nand_info;

	/* initialise the spi */

	s3c2410_gpio_setpin(S3C2410_GPG13, 0);
	s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);

	s3c2410_gpio_setpin(S3C2410_GPB7, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);

	s3c2410_gpio_setpin(S3C2410_GPB6, 0);
	s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);

	s3c2410_gpio_setpin(S3C2410_GPG8, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);

	/* initialise the WM8750 spi */

	s3c2410_gpio_setpin(S3C2410_GPH10, 1);
	s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);

	/* Turn off suspend on both USB ports, and switch the
	 * selectable USB port to USB device mode. */

	s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
			      S3C2410_MISCCR_USBSUSPND0 |
			      S3C2410_MISCCR_USBSUSPND1, 0x0);

	s3c24xx_udc_set_platdata(&jive_udc_cfg);
	s3c24xx_fb_set_platdata(&jive_lcd_config);

	spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));

	s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
	i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));

	platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
}

MACHINE_START(JIVE, "JIVE")
	/* Maintainer: Ben Dooks <ben@fluff.org> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,

	.init_irq	= s3c24xx_init_irq,
	.map_io		= jive_map_io,
	.init_machine	= jive_machine_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
9db829f4 BD	1	/* linux/arch/arm/mach-s3c2410/mach-jive.c
	2	*
	3	* Copyright 2007 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://armlinux.simtec.co.uk/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
	19	#include <linux/sysdev.h>
c2c1708f	20	#include <linux/delay.h>
9db829f4 BD	21	#include <linux/serial_core.h>
9db829f4 BD	22	#include <linux/platform_device.h>
d10d8a5f	23	#include <linux/i2c.h>
9db829f4	24
c2c1708f BD	25	#include <video/ili9320.h>
c2c1708f BD	26
a2ed4065 BD	27	#include <linux/spi/spi.h>
a2ed4065 BD	28
9db829f4 BD	29	#include <linux/mtd/mtd.h>
	30	#include <linux/mtd/partitions.h>
	31
	32	#include <asm/mach/arch.h>
	33	#include <asm/mach/map.h>
	34	#include <asm/mach/irq.h>
	35
	36	#include <asm/plat-s3c/regs-serial.h>
	37	#include <asm/plat-s3c/nand.h>
d10d8a5f	38	#include <asm/plat-s3c/iic.h>
9db829f4 BD	39
	40	#include <asm/arch/regs-power.h>
	41	#include <asm/arch/regs-gpio.h>
	42	#include <asm/arch/regs-mem.h>
	43	#include <asm/arch/regs-lcd.h>
a2ed4065	44	#include <asm/arch/spi-gpio.h>
0f99263c	45	#include <asm/arch/fb.h>
9db829f4 BD	46
	47	#include <asm/mach-types.h>
	48
	49	#include <linux/mtd/mtd.h>
	50	#include <linux/mtd/nand.h>
	51	#include <linux/mtd/nand_ecc.h>
	52	#include <linux/mtd/partitions.h>
	53
	54	#include <asm/plat-s3c24xx/clock.h>
	55	#include <asm/plat-s3c24xx/devs.h>
	56	#include <asm/plat-s3c24xx/cpu.h>
	57	#include <asm/plat-s3c24xx/pm.h>
	58	#include <asm/plat-s3c24xx/udc.h>
	59
	60	static struct map_desc jive_iodesc[] __initdata = {
	61	};
	62
	63	#define UCON S3C2410_UCON_DEFAULT
	64	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE
	65	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	66
	67	static struct s3c2410_uartcfg jive_uartcfgs[] = {
	68	[0] = {
	69	.hwport = 0,
	70	.flags = 0,
	71	.ucon = UCON,
	72	.ulcon = ULCON,
	73	.ufcon = UFCON,
	74	},
	75	[1] = {
	76	.hwport = 1,
	77	.flags = 0,
	78	.ucon = UCON,
	79	.ulcon = ULCON,
	80	.ufcon = UFCON,
	81	},
	82	[2] = {
	83	.hwport = 2,
	84	.flags = 0,
	85	.ucon = UCON,
	86	.ulcon = ULCON,
	87	.ufcon = UFCON,
	88	}
	89	};
	90
	91	/* Jive flash assignment
	92	*
	93	* 0x00000000-0x00028000 : uboot
	94	* 0x00028000-0x0002c000 : uboot env
	95	* 0x0002c000-0x00030000 : spare
	96	* 0x00030000-0x00200000 : zimage A
	97	* 0x00200000-0x01600000 : cramfs A
	98	* 0x01600000-0x017d0000 : zimage B
	99	* 0x017d0000-0x02bd0000 : cramfs B
	100	* 0x02bd0000-0x03fd0000 : yaffs
	101	*/
	102	static struct mtd_partition jive_imageA_nand_part[] = {
	103
	104	#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
	105	/* Don't allow access to the bootloader from linux */
	106	{
	107	.name = "uboot",
	108	.offset = 0,
	109	.size = (160 * SZ_1K),
110	.mask_flags = MTD_WRITEABLE, /* force read-only */
111	},
112
113	/* spare */
114	{
115	.name = "spare",
116	.offset = (176 * SZ_1K),
117	.size = (16 * SZ_1K),
118	},
119	#endif
120
121	/* booted images */
122	{
123	.name = "kernel (ro)",
124	.offset = (192 * SZ_1K),
125	.size = (SZ_2M) - (192 * SZ_1K),
126	.mask_flags = MTD_WRITEABLE, /* force read-only */
127	}, {
128	.name = "root (ro)",
129	.offset = (SZ_2M),
130	.size = (20 * SZ_1M),
131	.mask_flags = MTD_WRITEABLE, /* force read-only */
132	},
133
134	/* yaffs */
135	{
136	.name = "yaffs",
137	.offset = (44 * SZ_1M),
138	.size = (20 * SZ_1M),
139	},
140
141	/* bootloader environment */
142	{
143	.name = "env",
144	.offset = (160 * SZ_1K),
145	.size = (16 * SZ_1K),
146	},
147
148	/* upgrade images */
149	{
150	.name = "zimage",
151	.offset = (22 * SZ_1M),
152	.size = (2 * SZ_1M) - (192 * SZ_1K),
153	}, {
154	.name = "cramfs",
155	.offset = (24 * SZ_1M) - (192*SZ_1K),
156	.size = (20 * SZ_1M),
157	},
158	};
159
160	static struct mtd_partition jive_imageB_nand_part[] = {
161
162	#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
163	/* Don't allow access to the bootloader from linux */
164	{
165	.name = "uboot",
166	.offset = 0,
167	.size = (160 * SZ_1K),
168	.mask_flags = MTD_WRITEABLE, /* force read-only */
169	},
170
171	/* spare */
172	{
173	.name = "spare",
174	.offset = (176 * SZ_1K),
175	.size = (16 * SZ_1K),
176	},
177	#endif
178
179	/* booted images */
180	{
181	.name = "kernel (ro)",
182	.offset = (22 * SZ_1M),
183	.size = (2 * SZ_1M) - (192 * SZ_1K),
184	.mask_flags = MTD_WRITEABLE, /* force read-only */
185	},
186	{
187	.name = "root (ro)",
188	.offset = (24 * SZ_1M) - (192 * SZ_1K),
189	.size = (20 * SZ_1M),
190	.mask_flags = MTD_WRITEABLE, /* force read-only */
191	},
192
193	/* yaffs */
194	{
195	.name = "yaffs",
196	.offset = (44 * SZ_1M),
197	.size = (20 * SZ_1M),
198	},
199
200	/* bootloader environment */
201	{
202	.name = "env",
203	.offset = (160 * SZ_1K),
204	.size = (16 * SZ_1K),
205	},
206
207	/* upgrade images */
208	{
209	.name = "zimage",
210	.offset = (192 * SZ_1K),
211	.size = (2 * SZ_1M) - (192 * SZ_1K),
212	}, {
213	.name = "cramfs",
214	.offset = (2 * SZ_1M),
215	.size = (20 * SZ_1M),
216	},
217	};
218
219	static struct s3c2410_nand_set jive_nand_sets[] = {
220	[0] = {
221	.name = "flash",
222	.nr_chips = 1,
223	.nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
224	.partitions = jive_imageA_nand_part,
225	},
226	};
227
228	static struct s3c2410_platform_nand jive_nand_info = {
229	/* set taken from osiris nand timings, possibly still conservative */
230	.tacls = 30,
231	.twrph0 = 55,
232	.twrph1 = 40,
233	.sets = jive_nand_sets,
234	.nr_sets = ARRAY_SIZE(jive_nand_sets),
235	};
236
237	static int __init jive_mtdset(char *options)
238	{
239	struct s3c2410_nand_set *nand = &jive_nand_sets[0];
240	unsigned long set;
241
242	if (options == NULL \|\| options[0] == '\0')
243	return 0;
244
245	if (strict_strtoul(options, 10, &set)) {
246	printk(KERN_ERR "failed to parse mtdset=%s\n", options);
247	return 0;
248	}
249
250	switch (set) {
251	case 1:
252	nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
253	nand->partitions = jive_imageB_nand_part;
254	case 0:
255	/* this is already setup in the nand info */
256	break;
257	default:
258	printk(KERN_ERR "Unknown mtd set %ld specified,"
259	"using default.", set);
260	}
261
262	return 0;
263	}
264
265	/* parse the mtdset= option given to the kernel command line */
266	__setup("mtdset=", jive_mtdset);
267
0f99263c BD	268	/* LCD timing and setup */
	269
	270	#define LCD_XRES (240)
	271	#define LCD_YRES (320)
	272	#define LCD_LEFT_MARGIN (12)
	273	#define LCD_RIGHT_MARGIN (12)
	274	#define LCD_LOWER_MARGIN (12)
	275	#define LCD_UPPER_MARGIN (12)
	276	#define LCD_VSYNC (2)
	277	#define LCD_HSYNC (2)
	278
	279	#define LCD_REFRESH (60)
	280
	281	#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
	282	#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
	283
	284	struct s3c2410fb_display jive_vgg2432a4_display[] = {
	285	[0] = {
	286	.width = LCD_XRES,
	287	.height = LCD_YRES,
	288	.xres = LCD_XRES,
	289	.yres = LCD_YRES,
	290	.left_margin = LCD_LEFT_MARGIN,
	291	.right_margin = LCD_RIGHT_MARGIN,
	292	.upper_margin = LCD_UPPER_MARGIN,
	293	.lower_margin = LCD_LOWER_MARGIN,
	294	.hsync_len = LCD_HSYNC,
	295	.vsync_len = LCD_VSYNC,
	296
	297	.pixclock = (1000000000000LL /
	298	(LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
	299
	300	.bpp = 16,
	301	.type = (S3C2410_LCDCON1_TFT16BPP \|
	302	S3C2410_LCDCON1_TFT),
	303
	304	.lcdcon5 = (S3C2410_LCDCON5_FRM565 \|
	305	S3C2410_LCDCON5_INVVLINE \|
	306	S3C2410_LCDCON5_INVVFRAME \|
	307	S3C2410_LCDCON5_INVVDEN \|
	308	S3C2410_LCDCON5_PWREN),
	309	},
	310	};
	311
	312	/* todo - put into gpio header */
	313
	314	#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
	315	#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
	316
	317	struct s3c2410fb_mach_info jive_lcd_config = {
	318	.displays = jive_vgg2432a4_display,
	319	.num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
	320	.default_display = 0,
	321
	322	/* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
	323	* and disable the pull down resistors on pins we are using for LCD
	324	* data. */
	325
	326	.gpcup = (0xf << 1) \| (0x3f << 10),
	327
	328	.gpccon = (S3C2410_GPC1_VCLK \| S3C2410_GPC2_VLINE \|
	329	S3C2410_GPC3_VFRAME \| S3C2410_GPC4_VM \|
	330	S3C2410_GPC10_VD2 \| S3C2410_GPC11_VD3 \|
	331	S3C2410_GPC12_VD4 \| S3C2410_GPC13_VD5 \|
332	S3C2410_GPC14_VD6 \| S3C2410_GPC15_VD7),
333
334	.gpccon_mask = (S3C2410_GPCCON_MASK(1) \| S3C2410_GPCCON_MASK(2) \|
335	S3C2410_GPCCON_MASK(3) \| S3C2410_GPCCON_MASK(4) \|
336	S3C2410_GPCCON_MASK(10) \| S3C2410_GPCCON_MASK(11) \|
337	S3C2410_GPCCON_MASK(12) \| S3C2410_GPCCON_MASK(13) \|
338	S3C2410_GPCCON_MASK(14) \| S3C2410_GPCCON_MASK(15)),
339
340	.gpdup = (0x3f << 2) \| (0x3f << 10),
341
342	.gpdcon = (S3C2410_GPD2_VD10 \| S3C2410_GPD3_VD11 \|
343	S3C2410_GPD4_VD12 \| S3C2410_GPD5_VD13 \|
344	S3C2410_GPD6_VD14 \| S3C2410_GPD7_VD15 \|
345	S3C2410_GPD10_VD18 \| S3C2410_GPD11_VD19 \|
346	S3C2410_GPD12_VD20 \| S3C2410_GPD13_VD21 \|
347	S3C2410_GPD14_VD22 \| S3C2410_GPD15_VD23),
348
349	.gpdcon_mask = (S3C2410_GPDCON_MASK(2) \| S3C2410_GPDCON_MASK(3) \|
350	S3C2410_GPDCON_MASK(4) \| S3C2410_GPDCON_MASK(5) \|
351	S3C2410_GPDCON_MASK(6) \| S3C2410_GPDCON_MASK(7) \|
352	S3C2410_GPDCON_MASK(10) \| S3C2410_GPDCON_MASK(11)\|
353	S3C2410_GPDCON_MASK(12) \| S3C2410_GPDCON_MASK(13)\|
354	S3C2410_GPDCON_MASK(14) \| S3C2410_GPDCON_MASK(15)),
355	};
356
c2c1708f BD	357	/* ILI9320 support. */
	358
	359	static void jive_lcm_reset(unsigned int set)
	360	{
	361	printk(KERN_DEBUG "%s(%d)\n", __func__, set);
	362
	363	s3c2410_gpio_setpin(S3C2410_GPG13, set);
	364	s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
	365	}
	366
	367	#undef LCD_UPPER_MARGIN
	368	#define LCD_UPPER_MARGIN 2
	369
	370	static struct ili9320_platdata jive_lcm_config = {
	371	.hsize = LCD_XRES,
	372	.vsize = LCD_YRES,
	373
	374	.reset = jive_lcm_reset,
	375	.suspend = ILI9320_SUSPEND_DEEP,
	376
	377	.entry_mode = ILI9320_ENTRYMODE_ID(3) \| ILI9320_ENTRYMODE_BGR,
	378	.display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) \|
	379	ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
	380	.display3 = 0x0,
	381	.display4 = 0x0,
	382	.rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 \|
	383	ILI9320_RGBIF1_RM \| ILI9320_RGBIF1_CLK_RGBIF),
	384	.rgb_if2 = ILI9320_RGBIF2_DPL,
	385	.interface2 = 0x0,
	386	.interface3 = 0x3,
	387	.interface4 = (ILI9320_INTERFACE4_RTNE(16) \|
	388	ILI9320_INTERFACE4_DIVE(1)),
	389	.interface5 = 0x0,
	390	.interface6 = 0x0,
	391	};
	392
a2ed4065 BD	393	/* LCD SPI support */
	394
	395	static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
	396	{
	397	s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
	398	}
	399
	400	static struct s3c2410_spigpio_info jive_lcd_spi = {
d10d8a5f	401	.bus_num = 0,
a2ed4065 BD	402	.pin_clk = S3C2410_GPG8,
	403	.pin_mosi = S3C2410_GPB8,
	404	.chip_select = jive_lcd_spi_chipselect,
	405	};
	406
	407	static struct platform_device jive_device_lcdspi = {
	408	.name = "s3c24xx-spi-gpio",
	409	.id = 1,
	410	.num_resources = 0,
	411	.dev.platform_data = &jive_lcd_spi,
	412	};
	413
fd2de272 BD	414	/* WM8750 audio code SPI definition */
	415
	416	static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
	417	{
	418	s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
	419	}
	420
	421	static struct s3c2410_spigpio_info jive_wm8750_spi = {
	422	.bus_num = 2,
	423	.pin_clk = S3C2410_GPB4,
	424	.pin_mosi = S3C2410_GPB9,
	425	.chip_select = jive_wm8750_chipselect,
	426	};
	427
	428	static struct platform_device jive_device_wm8750 = {
	429	.name = "s3c24xx-spi-gpio",
	430	.id = 2,
	431	.num_resources = 0,
	432	.dev.platform_data = &jive_wm8750_spi,
	433	};
a2ed4065	434
fd2de272	435	/* JIVE SPI devices. */
a2ed4065 BD	436
	437	static struct spi_board_info __initdata jive_spi_devs[] = {
	438	[0] = {
	439	.modalias = "VGG2432A4",
	440	.bus_num = 1,
	441	.chip_select = 0,
	442	.mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
	443	.max_speed_hz = 100000,
c2c1708f	444	.platform_data = &jive_lcm_config,
fd2de272 BD	445	}, {
	446	.modalias = "WM8750",
	447	.bus_num = 2,
	448	.chip_select = 0,
	449	.mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
	450	.max_speed_hz = 100000,
a2ed4065 BD	451	},
	452	};
	453
d10d8a5f BD	454	/* I2C bus and device configuration. */
	455
	456	static struct s3c2410_platform_i2c jive_i2c_cfg = {
	457	.max_freq = 80 * 1000,
	458	.bus_freq = 50 * 1000,
	459	.flags = S3C_IICFLG_FILTER,
	460	.sda_delay = 2,
	461	};
	462
	463	static struct i2c_board_info jive_i2c_devs[] = {
	464	[0] = {
	465	I2C_BOARD_INFO("lis302dl", 0x1c),
	466	.irq = IRQ_EINT14,
	467	},
	468	};
	469
	470	/* The platform devices being used. */
	471
9db829f4 BD	472	static struct platform_device *jive_devices[] __initdata = {
	473	&s3c_device_usb,
	474	&s3c_device_rtc,
	475	&s3c_device_wdt,
	476	&s3c_device_i2c,
0f99263c	477	&s3c_device_lcd,
a2ed4065	478	&jive_device_lcdspi,
fd2de272	479	&jive_device_wm8750,
9db829f4 BD	480	&s3c_device_nand,
	481	&s3c_device_usbgadget,
	482	};
	483
	484	static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
	485	.vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */
	486	};
	487
	488	/* Jive power management device */
	489
	490	#ifdef CONFIG_PM
	491	static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
	492	{
	493	/* Write the magic value u-boot uses to check for resume into
	494	* the INFORM0 register, and ensure INFORM1 is set to the
	495	* correct address to resume from. */
	496
	497	__raw_writel(0x2BED, S3C2412_INFORM0);
	498	__raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
	499
	500	return 0;
	501	}
	502
	503	static int jive_pm_resume(struct sys_device *sd)
	504	{
	505	__raw_writel(0x0, S3C2412_INFORM0);
	506	return 0;
	507	}
	508
	509	#else
	510	#define jive_pm_suspend NULL
	511	#define jive_pm_resume NULL
	512	#endif
	513
	514	static struct sysdev_class jive_pm_sysclass = {
	515	.name = "jive-pm",
	516	.suspend = jive_pm_suspend,
	517	.resume = jive_pm_resume,
	518	};
	519
	520	static struct sys_device jive_pm_sysdev = {
	521	.cls = &jive_pm_sysclass,
	522	};
	523
	524	static void __init jive_map_io(void)
	525	{
	526	s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
	527	s3c24xx_init_clocks(12000000);
	528	s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
	529	}
	530
	531	static void __init jive_machine_init(void)
	532	{
	533	/* register system devices for managing low level suspend */
	534
	535	sysdev_class_register(&jive_pm_sysclass);
	536	sysdev_register(&jive_pm_sysdev);
	537
54c272ac BD	538	/* write our sleep configurations for the IO. Pull down all unused
	539	* IO, ensure that we have turned off all peripherals we do not
	540	* need, and configure the ones we do need. */
	541
	542	/* Port B sleep */
	543
	544	__raw_writel(S3C2412_SLPCON_IN(0) \|
	545	S3C2412_SLPCON_PULL(1) \|
	546	S3C2412_SLPCON_HIGH(2) \|
	547	S3C2412_SLPCON_PULL(3) \|
	548	S3C2412_SLPCON_PULL(4) \|
	549	S3C2412_SLPCON_PULL(5) \|
	550	S3C2412_SLPCON_PULL(6) \|
	551	S3C2412_SLPCON_HIGH(7) \|
	552	S3C2412_SLPCON_PULL(8) \|
	553	S3C2412_SLPCON_PULL(9) \|
	554	S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
	555
	556	/* Port C sleep */
	557
	558	__raw_writel(S3C2412_SLPCON_PULL(0) \|
	559	S3C2412_SLPCON_PULL(1) \|
	560	S3C2412_SLPCON_PULL(2) \|
	561	S3C2412_SLPCON_PULL(3) \|
	562	S3C2412_SLPCON_PULL(4) \|
	563	S3C2412_SLPCON_PULL(5) \|
	564	S3C2412_SLPCON_LOW(6) \|
	565	S3C2412_SLPCON_PULL(6) \|
	566	S3C2412_SLPCON_PULL(7) \|
	567	S3C2412_SLPCON_PULL(8) \|
	568	S3C2412_SLPCON_PULL(9) \|
	569	S3C2412_SLPCON_PULL(10) \|
	570	S3C2412_SLPCON_PULL(11) \|
	571	S3C2412_SLPCON_PULL(12) \|
	572	S3C2412_SLPCON_PULL(13) \|
	573	S3C2412_SLPCON_PULL(14) \|
	574	S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
	575
	576	/* Port D sleep */
	577
	578	__raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
	579
	580	/* Port F sleep */
	581
	582	__raw_writel(S3C2412_SLPCON_LOW(0) \|
	583	S3C2412_SLPCON_LOW(1) \|
	584	S3C2412_SLPCON_LOW(2) \|
	585	S3C2412_SLPCON_EINT(3) \|
	586	S3C2412_SLPCON_EINT(4) \|
	587	S3C2412_SLPCON_EINT(5) \|
	588	S3C2412_SLPCON_EINT(6) \|
	589	S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
	590
	591	/* Port G sleep */
	592
	593	__raw_writel(S3C2412_SLPCON_IN(0) \|
	594	S3C2412_SLPCON_IN(1) \|
	595	S3C2412_SLPCON_IN(2) \|
	596	S3C2412_SLPCON_IN(3) \|
	597	S3C2412_SLPCON_IN(4) \|
	598	S3C2412_SLPCON_IN(5) \|
	599	S3C2412_SLPCON_IN(6) \|
	600	S3C2412_SLPCON_IN(7) \|
	601	S3C2412_SLPCON_PULL(8) \|
602	S3C2412_SLPCON_PULL(9) \|
603	S3C2412_SLPCON_IN(10) \|
604	S3C2412_SLPCON_PULL(11) \|
605	S3C2412_SLPCON_PULL(12) \|
606	S3C2412_SLPCON_PULL(13) \|
607	S3C2412_SLPCON_IN(14) \|
608	S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
609
610	/* Port H sleep */
611
612	__raw_writel(S3C2412_SLPCON_PULL(0) \|
613	S3C2412_SLPCON_PULL(1) \|
614	S3C2412_SLPCON_PULL(2) \|
615	S3C2412_SLPCON_PULL(3) \|
616	S3C2412_SLPCON_PULL(4) \|
617	S3C2412_SLPCON_PULL(5) \|
618	S3C2412_SLPCON_PULL(6) \|
619	S3C2412_SLPCON_IN(7) \|
620	S3C2412_SLPCON_IN(8) \|
621	S3C2412_SLPCON_PULL(9) \|
622	S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
623
624	/* initialise the power management now we've setup everything. */
625
9db829f4 BD	626	s3c2410_pm_init();
	627
	628	s3c_device_nand.dev.platform_data = &jive_nand_info;
	629
a2ed4065 BD	630	/* initialise the spi */
	631
	632	s3c2410_gpio_setpin(S3C2410_GPG13, 0);
	633	s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
	634
	635	s3c2410_gpio_setpin(S3C2410_GPB7, 1);
	636	s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
	637
	638	s3c2410_gpio_setpin(S3C2410_GPB6, 0);
	639	s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
	640
	641	s3c2410_gpio_setpin(S3C2410_GPG8, 1);
	642	s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
	643
fd2de272 BD	644	/* initialise the WM8750 spi */
	645
	646	s3c2410_gpio_setpin(S3C2410_GPH10, 1);
	647	s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
	648
9db829f4 BD	649	/* Turn off suspend on both USB ports, and switch the
	650	* selectable USB port to USB device mode. */
	651
	652	s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST \|
	653	S3C2410_MISCCR_USBSUSPND0 \|
	654	S3C2410_MISCCR_USBSUSPND1, 0x0);
	655
	656	s3c24xx_udc_set_platdata(&jive_udc_cfg);
0f99263c	657	s3c24xx_fb_set_platdata(&jive_lcd_config);
9db829f4	658
a2ed4065 BD	659	spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
a2ed4065 BD	660
d10d8a5f BD	661	s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
	662	i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
	663
9db829f4 BD	664	platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
	665	}
	666
	667	MACHINE_START(JIVE, "JIVE")
	668	/* Maintainer: Ben Dooks <ben@fluff.org> */
	669	.phys_io = S3C2410_PA_UART,
	670	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	671	.boot_params = S3C2410_SDRAM_PA + 0x100,
	672
	673	.init_irq = s3c24xx_init_irq,
	674	.map_io = jive_map_io,
	675	.init_machine = jive_machine_init,
	676	.timer = &s3c24xx_timer,
	677	MACHINE_END