[linux-2.6-block.git] / arch / arm / mach-s3c2410 / mach-bast.c

/* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
 * Copyright (c) 2003-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>

#include <net/ax88796.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <asm/arch/bast-map.h>
#include <asm/arch/bast-irq.h>
#include <asm/arch/bast-cpld.h>

#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

//#include <asm/debug-ll.h>
#include <asm/plat-s3c/regs-serial.h>
#include <asm/arch/regs-gpio.h>
#include <asm/arch/regs-mem.h>
#include <asm/arch/regs-lcd.h>

#include <asm/plat-s3c/nand.h>
#include <asm/plat-s3c/iic.h>
#include <asm/arch/fb.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <linux/serial_8250.h>

#include <asm/plat-s3c24xx/clock.h>
#include <asm/plat-s3c24xx/devs.h>
#include <asm/plat-s3c24xx/cpu.h>
#include "usb-simtec.h"

#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"

/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)

/* macros to modify the physical addresses for io space */

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))

static struct map_desc bast_iodesc[] __initdata = {
  /* ISA IO areas */
  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= PA_CS2(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= PA_CS3(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },
  /* bast CPLD control registers, and external interrupt controls */
  {
	  .virtual	= (u32)BAST_VA_CTRL1,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL2,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL3,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL4,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },
  /* PC104 IRQ mux */
  {
	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },

  /* peripheral space... one for each of fast/slow/byte/16bit */
  /* note, ide is only decoded in word space, even though some registers
   * are only 8bit */

  /* slow, byte */
  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C2(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C2(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },

  /* slow, word */
  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C3(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C3(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },

  /* fast, byte */
  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C4(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C4(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },

  /* fast, word */
  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
  { VA_C5(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
  { VA_C5(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
  { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
  { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	/* port 2 is not actually used */
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	}
};

/* NOR Flash on BAST board */

static struct resource bast_nor_resource[] = {
	[0] = {
		.start = S3C2410_CS1 + 0x4000000,
		.end   = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_nor = {
	.name		= "bast-nor",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(bast_nor_resource),
	.resource	= bast_nor_resource,
};

/* NAND Flash on BAST board */


static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };

static struct mtd_partition bast_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user",
		.offset	= SZ_4M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the bast has 4 selectable slots for nand-flash, the three
 * on-board chip areas, as well as the external SmartMedia
 * slot.
 *
 * Note, there is no current hot-plug support for the SmartMedia
 * socket.
*/

static struct s3c2410_nand_set bast_nand_sets[] = {
	[0] = {
		.name		= "SmartMedia",
		.nr_chips	= 1,
		.nr_map		= smartmedia_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[1] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[3] = {
		.name		= "chip2",
		.nr_chips	= 1,
		.nr_map		= chip2_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	}
};

static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(BAST_VA_CTRL2);
	tmp &= BAST_CPLD_CTLR2_IDERST;
	tmp |= slot;
	tmp |= BAST_CPLD_CTRL2_WNAND;

	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);

	__raw_writeb(tmp, BAST_VA_CTRL2);
}

static struct s3c2410_platform_nand bast_nand_info = {
	.tacls		= 30,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
	.sets		= bast_nand_sets,
	.select_chip	= bast_nand_select,
};

/* DM9000 */

static struct resource bast_dm9k_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_DM9000,
		.end   = IRQ_DM9000,
		.flags = IORESOURCE_IRQ,
	}

};

/* for the moment we limit ourselves to 16bit IO until some
 * better IO routines can be written and tested
*/

static struct dm9000_plat_data bast_dm9k_platdata = {
	.flags		= DM9000_PLATF_16BITONLY,
};

static struct platform_device bast_device_dm9k = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_dm9k_resource),
	.resource	= bast_dm9k_resource,
	.dev		= {
		.platform_data = &bast_dm9k_platdata,
	}
};

/* serial devices */

#define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
#define SERIAL_CLK   (1843200)

static struct plat_serial8250_port bast_sio_data[] = {
	[0] = {
		.mapbase	= SERIAL_BASE + 0x2f8,
		.irq		= IRQ_PCSERIAL1,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	[1] = {
		.mapbase	= SERIAL_BASE + 0x3f8,
		.irq		= IRQ_PCSERIAL2,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	{ }
};

static struct platform_device bast_sio = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= &bast_sio_data,
	},
};

/* we have devices on the bus which cannot work much over the
 * standard 100KHz i2c bus frequency
*/

static struct s3c2410_platform_i2c bast_i2c_info = {
	.flags		= 0,
	.slave_addr	= 0x10,
	.bus_freq	= 100*1000,
	.max_freq	= 130*1000,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data bast_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource bast_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET,
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device bast_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asix_resource),
	.resource	= bast_asix_resource,
	.dev		= {
		.platform_data = &bast_asix_platdata
	}
};

/* Asix AX88796 10/100 ethernet controller parallel port */

static struct resource bast_asixpp_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_axpp = {
	.name		= "ax88796-pp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asixpp_resource),
	.resource	= bast_asixpp_resource,
};

/* LCD/VGA controller */

static struct s3c2410fb_display __initdata bast_lcd_info[] = {
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,
		.xres		= 320,
		.yres		= 240,
		.left_margin	= 40,
		.right_margin	= 20,

		.bpp		= 4,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 640,
		.yres		= 480,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 800,
		.yres		= 600,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 320,
		.yres		= 240,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 640,
		.yres		= 480,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 800,
		.yres		= 600,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 320,
		.yres		= 240,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.xres		= 800,
		.yres		= 600,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,

		.lcdcon1	= 0x00000176,
		.lcdcon2	= 0x1d77c7c2,
		.lcdcon4	= 0x00000057,
		.lcdcon5	= 0x00014b02,
	},
};

/* LCD/VGA controller */

static struct s3c2410fb_mach_info __initdata bast_fb_info = {

	.displays = bast_lcd_info,
	.num_displays = ARRAY_SIZE(bast_lcd_info),
	.default_display = 4,
};

/* Standard BAST devices */

static struct platform_device *bast_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c,
	&s3c_device_iis,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&bast_device_nor,
	&bast_device_dm9k,
	&bast_device_asix,
	&bast_device_axpp,
	&bast_sio,
};

static struct clk *bast_clocks[] = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = NULL;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = NULL;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));

	s3c_device_nand.dev.platform_data = &bast_nand_info;
	s3c_device_i2c.dev.platform_data = &bast_i2c_info;

	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));

	usb_simtec_init();
}

static void __init bast_init(void)
{
	s3c24xx_fb_set_platdata(&bast_fb_info);
	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
}

MACHINE_START(BAST, "Simtec-BAST")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= bast_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= bast_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/mach-bast.c
	2	*
	3	* Copyright (c) 2003-2005 Simtec Electronics
	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.simtec.co.uk/products/EB2410ITX/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
b6d1f542	19	#include <linux/serial_core.h>
d052d1be	20	#include <linux/platform_device.h>
d97a666f	21	#include <linux/dm9000.h>
1da177e4	22
5ce4b1fe BD	23	#include <net/ax88796.h>
5ce4b1fe BD	24
1da177e4 LT	25	#include <asm/mach/arch.h>
	26	#include <asm/mach/map.h>
	27	#include <asm/mach/irq.h>
	28
	29	#include <asm/arch/bast-map.h>
	30	#include <asm/arch/bast-irq.h>
	31	#include <asm/arch/bast-cpld.h>
	32
	33	#include <asm/hardware.h>
	34	#include <asm/io.h>
	35	#include <asm/irq.h>
	36	#include <asm/mach-types.h>
	37
	38	//#include <asm/debug-ll.h>
531b617c	39	#include <asm/plat-s3c/regs-serial.h>
1da177e4 LT	40	#include <asm/arch/regs-gpio.h>
1da177e4 LT	41	#include <asm/arch/regs-mem.h>
d97a666f	42	#include <asm/arch/regs-lcd.h>
58c8d570	43
531b617c BD	44	#include <asm/plat-s3c/nand.h>
531b617c BD	45	#include <asm/plat-s3c/iic.h>
58c8d570	46	#include <asm/arch/fb.h>
1da177e4 LT	47
	48	#include <linux/mtd/mtd.h>
	49	#include <linux/mtd/nand.h>
	50	#include <linux/mtd/nand_ecc.h>
	51	#include <linux/mtd/partitions.h>
	52
65cc3370 BD	53	#include <linux/serial_8250.h>
65cc3370 BD	54
a21765a7 BD	55	#include <asm/plat-s3c24xx/clock.h>
	56	#include <asm/plat-s3c24xx/devs.h>
	57	#include <asm/plat-s3c24xx/cpu.h>
1da177e4	58	#include "usb-simtec.h"
1da177e4 LT	59
	60	#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
	61
	62	/* macros for virtual address mods for the io space entries */
	63	#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
	64	#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
	65	#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
	66	#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
	67
	68	/* macros to modify the physical addresses for io space */
	69
1d23b65d BD	70	#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
	71	#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
	72	#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
	73	#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
1da177e4 LT	74
	75	static struct map_desc bast_iodesc[] __initdata = {
	76	/* ISA IO areas */
1d23b65d BD	77	{
	78	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	79	.pfn = PA_CS2(BAST_PA_ISAIO),
	80	.length = SZ_16M,
	81	.type = MT_DEVICE,
	82	}, {
	83	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	84	.pfn = PA_CS3(BAST_PA_ISAIO),
	85	.length = SZ_16M,
	86	.type = MT_DEVICE,
	87	},
1da177e4	88	/* bast CPLD control registers, and external interrupt controls */
1d23b65d BD	89	{
	90	.virtual = (u32)BAST_VA_CTRL1,
	91	.pfn = __phys_to_pfn(BAST_PA_CTRL1),
	92	.length = SZ_1M,
	93	.type = MT_DEVICE,
	94	}, {
	95	.virtual = (u32)BAST_VA_CTRL2,
	96	.pfn = __phys_to_pfn(BAST_PA_CTRL2),
	97	.length = SZ_1M,
	98	.type = MT_DEVICE,
	99	}, {
	100	.virtual = (u32)BAST_VA_CTRL3,
	101	.pfn = __phys_to_pfn(BAST_PA_CTRL3),
	102	.length = SZ_1M,
	103	.type = MT_DEVICE,
	104	}, {
	105	.virtual = (u32)BAST_VA_CTRL4,
	106	.pfn = __phys_to_pfn(BAST_PA_CTRL4),
	107	.length = SZ_1M,
	108	.type = MT_DEVICE,
	109	},
1da177e4	110	/* PC104 IRQ mux */
1d23b65d BD	111	{
	112	.virtual = (u32)BAST_VA_PC104_IRQREQ,
	113	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	114	.length = SZ_1M,
	115	.type = MT_DEVICE,
	116	}, {
	117	.virtual = (u32)BAST_VA_PC104_IRQRAW,
	118	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	119	.length = SZ_1M,
	120	.type = MT_DEVICE,
	121	}, {
	122	.virtual = (u32)BAST_VA_PC104_IRQMASK,
	123	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	124	.length = SZ_1M,
	125	.type = MT_DEVICE,
	126	},
1da177e4 LT	127
	128	/* peripheral space... one for each of fast/slow/byte/16bit */
	129	/* note, ide is only decoded in word space, even though some registers
	130	* are only 8bit */
	131
	132	/* slow, byte */
	133	{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	134	{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	135	{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	136	{ VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	137	{ VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	138	{ VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	139	{ VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	140
	141	/* slow, word */
	142	{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	143	{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	144	{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	145	{ VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	146	{ VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	147	{ VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	148	{ VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	149
	150	/* fast, byte */
	151	{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	152	{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	153	{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	154	{ VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	155	{ VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	156	{ VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	157	{ VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	158
	159	/* fast, word */
	160	{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	161	{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	162	{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	163	{ VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
	164	{ VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
	165	{ VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
	166	{ VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
	167	};
	168
	169	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	170	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	171	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	172
	173	static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	174	[0] = {
	175	.name = "uclk",
	176	.divisor = 1,
	177	.min_baud = 0,
	178	.max_baud = 0,
	179	},
	180	[1] = {
	181	.name = "pclk",
	182	.divisor = 1,
	183	.min_baud = 0,
b526bf23	184	.max_baud = 0,
1da177e4 LT	185	}
	186	};
	187
	188
66a9b49a	189	static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
1da177e4 LT	190	[0] = {
	191	.hwport = 0,
	192	.flags = 0,
	193	.ucon = UCON,
	194	.ulcon = ULCON,
	195	.ufcon = UFCON,
	196	.clocks = bast_serial_clocks,
b526bf23	197	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	198	},
	199	[1] = {
	200	.hwport = 1,
	201	.flags = 0,
	202	.ucon = UCON,
	203	.ulcon = ULCON,
	204	.ufcon = UFCON,
	205	.clocks = bast_serial_clocks,
b526bf23	206	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	207	},
	208	/* port 2 is not actually used */
	209	[2] = {
	210	.hwport = 2,
	211	.flags = 0,
	212	.ucon = UCON,
	213	.ulcon = ULCON,
	214	.ufcon = UFCON,
	215	.clocks = bast_serial_clocks,
b526bf23	216	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	217	}
	218	};
	219
	220	/* NOR Flash on BAST board */
	221
	222	static struct resource bast_nor_resource[] = {
	223	[0] = {
	224	.start = S3C2410_CS1 + 0x4000000,
	225	.end = S3C2410_CS1 + 0x4000000 + (3210241024) - 1,
	226	.flags = IORESOURCE_MEM,
	227	}
	228	};
	229
	230	static struct platform_device bast_device_nor = {
	231	.name = "bast-nor",
	232	.id = -1,
	233	.num_resources = ARRAY_SIZE(bast_nor_resource),
	234	.resource = bast_nor_resource,
	235	};
	236
	237	/* NAND Flash on BAST board */
	238
	239
	240	static int smartmedia_map[] = { 0 };
	241	static int chip0_map[] = { 1 };
	242	static int chip1_map[] = { 2 };
	243	static int chip2_map[] = { 3 };
	244
9f693d7b	245	static struct mtd_partition bast_default_nand_part[] = {
1da177e4 LT	246	[0] = {
	247	.name = "Boot Agent",
	248	.size = SZ_16K,
b526bf23	249	.offset = 0,
1da177e4 LT	250	},
	251	[1] = {
	252	.name = "/boot",
	253	.size = SZ_4M - SZ_16K,
	254	.offset = SZ_16K,
	255	},
	256	[2] = {
	257	.name = "user",
	258	.offset = SZ_4M,
	259	.size = MTDPART_SIZ_FULL,
	260	}
	261	};
	262
	263	/* the bast has 4 selectable slots for nand-flash, the three
	264	* on-board chip areas, as well as the external SmartMedia
	265	* slot.
	266	*
	267	* Note, there is no current hot-plug support for the SmartMedia
	268	* socket.
	269	*/
	270
	271	static struct s3c2410_nand_set bast_nand_sets[] = {
	272	[0] = {
	273	.name = "SmartMedia",
	274	.nr_chips = 1,
	275	.nr_map = smartmedia_map,
	276	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	277	.partitions = bast_default_nand_part,
1da177e4 LT	278	},
	279	[1] = {
	280	.name = "chip0",
	281	.nr_chips = 1,
	282	.nr_map = chip0_map,
	283	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	284	.partitions = bast_default_nand_part,
1da177e4 LT	285	},
	286	[2] = {
	287	.name = "chip1",
	288	.nr_chips = 1,
	289	.nr_map = chip1_map,
	290	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	291	.partitions = bast_default_nand_part,
1da177e4 LT	292	},
	293	[3] = {
	294	.name = "chip2",
	295	.nr_chips = 1,
	296	.nr_map = chip2_map,
	297	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	298	.partitions = bast_default_nand_part,
1da177e4 LT	299	}
	300	};
	301
	302	static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
	303	{
	304	unsigned int tmp;
	305
	306	slot = set->nr_map[slot] & 3;
	307
	308	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
	309	slot, set, set->nr_map);
	310
	311	tmp = __raw_readb(BAST_VA_CTRL2);
	312	tmp &= BAST_CPLD_CTLR2_IDERST;
	313	tmp \|= slot;
	314	tmp \|= BAST_CPLD_CTRL2_WNAND;
	315
	316	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
	317
	318	__raw_writeb(tmp, BAST_VA_CTRL2);
	319	}
	320
	321	static struct s3c2410_platform_nand bast_nand_info = {
b048dbf4 BD	322	.tacls = 30,
	323	.twrph0 = 60,
	324	.twrph1 = 60,
1da177e4 LT	325	.nr_sets = ARRAY_SIZE(bast_nand_sets),
	326	.sets = bast_nand_sets,
	327	.select_chip = bast_nand_select,
	328	};
	329
d97a666f BD	330	/* DM9000 */
	331
	332	static struct resource bast_dm9k_resource[] = {
	333	[0] = {
	334	.start = S3C2410_CS5 + BAST_PA_DM9000,
	335	.end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
b526bf23	336	.flags = IORESOURCE_MEM,
d97a666f BD	337	},
	338	[1] = {
	339	.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
	340	.end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
b526bf23	341	.flags = IORESOURCE_MEM,
d97a666f BD	342	},
	343	[2] = {
	344	.start = IRQ_DM9000,
	345	.end = IRQ_DM9000,
b526bf23	346	.flags = IORESOURCE_IRQ,
d97a666f BD	347	}
	348
	349	};
	350
	351	/* for the moment we limit ourselves to 16bit IO until some
	352	* better IO routines can be written and tested
	353	*/
	354
9f693d7b	355	static struct dm9000_plat_data bast_dm9k_platdata = {
b526bf23	356	.flags = DM9000_PLATF_16BITONLY,
d97a666f BD	357	};
	358
	359	static struct platform_device bast_device_dm9k = {
	360	.name = "dm9000",
	361	.id = 0,
	362	.num_resources = ARRAY_SIZE(bast_dm9k_resource),
	363	.resource = bast_dm9k_resource,
	364	.dev = {
	365	.platform_data = &bast_dm9k_platdata,
	366	}
	367	};
	368
65cc3370 BD	369	/* serial devices */
	370
	371	#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
	372	#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SHARE_IRQ)
	373	#define SERIAL_CLK (1843200)
	374
	375	static struct plat_serial8250_port bast_sio_data[] = {
	376	[0] = {
	377	.mapbase = SERIAL_BASE + 0x2f8,
	378	.irq = IRQ_PCSERIAL1,
	379	.flags = SERIAL_FLAGS,
	380	.iotype = UPIO_MEM,
	381	.regshift = 0,
	382	.uartclk = SERIAL_CLK,
	383	},
	384	[1] = {
	385	.mapbase = SERIAL_BASE + 0x3f8,
	386	.irq = IRQ_PCSERIAL2,
	387	.flags = SERIAL_FLAGS,
	388	.iotype = UPIO_MEM,
	389	.regshift = 0,
	390	.uartclk = SERIAL_CLK,
	391	},
	392	{ }
	393	};
	394
	395	static struct platform_device bast_sio = {
	396	.name = "serial8250",
6df29deb	397	.id = PLAT8250_DEV_PLATFORM,
65cc3370 BD	398	.dev = {
	399	.platform_data = &bast_sio_data,
	400	},
	401	};
1da177e4	402
1fcf8448 BD	403	/* we have devices on the bus which cannot work much over the
	404	* standard 100KHz i2c bus frequency
	405	*/
	406
	407	static struct s3c2410_platform_i2c bast_i2c_info = {
	408	.flags = 0,
	409	.slave_addr = 0x10,
	410	.bus_freq = 100*1000,
	411	.max_freq = 130*1000,
	412	};
	413
5ce4b1fe BD	414	/* Asix AX88796 10/100 ethernet controller */
	415
	416	static struct ax_plat_data bast_asix_platdata = {
	417	.flags = AXFLG_MAC_FROMDEV,
	418	.wordlength = 2,
	419	.dcr_val = 0x48,
	420	.rcr_val = 0x40,
	421	};
	422
	423	static struct resource bast_asix_resource[] = {
	424	[0] = {
	425	.start = S3C2410_CS5 + BAST_PA_ASIXNET,
	426	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
	427	.flags = IORESOURCE_MEM,
	428	},
	429	[1] = {
	430	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	431	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	432	.flags = IORESOURCE_MEM,
	433	},
	434	[2] = {
	435	.start = IRQ_ASIX,
	436	.end = IRQ_ASIX,
	437	.flags = IORESOURCE_IRQ
	438	}
	439	};
	440
	441	static struct platform_device bast_device_asix = {
	442	.name = "ax88796",
	443	.id = 0,
	444	.num_resources = ARRAY_SIZE(bast_asix_resource),
	445	.resource = bast_asix_resource,
	446	.dev = {
	447	.platform_data = &bast_asix_platdata
	448	}
	449	};
	450
	451	/* Asix AX88796 10/100 ethernet controller parallel port */
	452
	453	static struct resource bast_asixpp_resource[] = {
	454	[0] = {
	455	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
	456	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
	457	.flags = IORESOURCE_MEM,
	458	}
	459	};
	460
	461	static struct platform_device bast_device_axpp = {
	462	.name = "ax88796-pp",
	463	.id = 0,
	464	.num_resources = ARRAY_SIZE(bast_asixpp_resource),
	465	.resource = bast_asixpp_resource,
	466	};
	467
	468	/* LCD/VGA controller */
58c8d570	469
09fe75f6 KH	470	static struct s3c2410fb_display __initdata bast_lcd_info[] = {
09fe75f6 KH	471	{
1f411537	472	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	473	.width = 640,
	474	.height = 480,
	475	.xres = 320,
	476	.yres = 240,
1f411537 KH	477	.left_margin = 40,
1f411537 KH	478	.right_margin = 20,
09fe75f6 KH	479
	480	.bpp = 4,
	481
f28ef573 KH	482	.lcdcon1 = 0x00000176,
	483	.lcdcon2 = 0x1d77c7c2,
	484	.lcdcon4 = 0x00000057,
	485	.lcdcon5 = 0x00014b02,
58c8d570	486	},
09fe75f6	487	{
1f411537	488	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	489	.width = 640,
	490	.height = 480,
	491
	492	.xres = 640,
	493	.yres = 480,
	494	.bpp = 4,
1f411537 KH	495	.left_margin = 40,
1f411537 KH	496	.right_margin = 20,
09fe75f6	497
f28ef573 KH	498	.lcdcon1 = 0x00000176,
	499	.lcdcon2 = 0x1d77c7c2,
	500	.lcdcon4 = 0x00000057,
	501	.lcdcon5 = 0x00014b02,
58c8d570	502	},
09fe75f6	503	{
1f411537	504	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	505	.width = 640,
	506	.height = 480,
	507
	508	.xres = 800,
	509	.yres = 600,
	510	.bpp = 4,
1f411537 KH	511	.left_margin = 40,
1f411537 KH	512	.right_margin = 20,
09fe75f6	513
f28ef573 KH	514	.lcdcon1 = 0x00000176,
	515	.lcdcon2 = 0x1d77c7c2,
	516	.lcdcon4 = 0x00000057,
	517	.lcdcon5 = 0x00014b02,
09fe75f6 KH	518	},
09fe75f6 KH	519	{
1f411537	520	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	521	.width = 640,
	522	.height = 480,
	523
	524	.xres = 320,
	525	.yres = 240,
	526	.bpp = 8,
1f411537 KH	527	.left_margin = 40,
1f411537 KH	528	.right_margin = 20,
09fe75f6	529
f28ef573 KH	530	.lcdcon1 = 0x00000176,
	531	.lcdcon2 = 0x1d77c7c2,
	532	.lcdcon4 = 0x00000057,
	533	.lcdcon5 = 0x00014b02,
09fe75f6 KH	534	},
09fe75f6 KH	535	{
1f411537	536	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	537	.width = 640,
	538	.height = 480,
	539
	540	.xres = 640,
	541	.yres = 480,
	542	.bpp = 8,
1f411537 KH	543	.left_margin = 40,
1f411537 KH	544	.right_margin = 20,
09fe75f6	545
f28ef573 KH	546	.lcdcon1 = 0x00000176,
	547	.lcdcon2 = 0x1d77c7c2,
	548	.lcdcon4 = 0x00000057,
	549	.lcdcon5 = 0x00014b02,
09fe75f6 KH	550	},
09fe75f6 KH	551	{
1f411537	552	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	553	.width = 640,
	554	.height = 480,
	555
	556	.xres = 800,
	557	.yres = 600,
	558	.bpp = 8,
1f411537 KH	559	.left_margin = 40,
1f411537 KH	560	.right_margin = 20,
09fe75f6	561
f28ef573 KH	562	.lcdcon1 = 0x00000176,
	563	.lcdcon2 = 0x1d77c7c2,
	564	.lcdcon4 = 0x00000057,
	565	.lcdcon5 = 0x00014b02,
09fe75f6 KH	566	},
09fe75f6 KH	567	{
1f411537	568	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	569	.width = 640,
	570	.height = 480,
	571
	572	.xres = 320,
	573	.yres = 240,
	574	.bpp = 16,
1f411537 KH	575	.left_margin = 40,
1f411537 KH	576	.right_margin = 20,
09fe75f6	577
f28ef573 KH	578	.lcdcon1 = 0x00000176,
	579	.lcdcon2 = 0x1d77c7c2,
	580	.lcdcon4 = 0x00000057,
	581	.lcdcon5 = 0x00014b02,
09fe75f6 KH	582	},
09fe75f6 KH	583	{
1f411537	584	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	585	.width = 640,
	586	.height = 480,
	587
	588	.xres = 640,
	589	.yres = 480,
	590	.bpp = 16,
1f411537 KH	591	.left_margin = 40,
1f411537 KH	592	.right_margin = 20,
09fe75f6	593
f28ef573 KH	594	.lcdcon1 = 0x00000176,
	595	.lcdcon2 = 0x1d77c7c2,
	596	.lcdcon4 = 0x00000057,
	597	.lcdcon5 = 0x00014b02,
58c8d570	598	},
09fe75f6	599	{
1f411537	600	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	601	.width = 640,
	602	.height = 480,
	603
	604	.xres = 800,
	605	.yres = 600,
	606	.bpp = 16,
1f411537 KH	607	.left_margin = 40,
1f411537 KH	608	.right_margin = 20,
09fe75f6	609
f28ef573 KH	610	.lcdcon1 = 0x00000176,
	611	.lcdcon2 = 0x1d77c7c2,
	612	.lcdcon4 = 0x00000057,
	613	.lcdcon5 = 0x00014b02,
09fe75f6 KH	614	},
09fe75f6 KH	615	};
58c8d570	616
09fe75f6 KH	617	/* LCD/VGA controller */
	618
	619	static struct s3c2410fb_mach_info __initdata bast_fb_info = {
	620
	621	.displays = bast_lcd_info,
	622	.num_displays = ARRAY_SIZE(bast_lcd_info),
	623	.default_display = 4,
58c8d570 BD	624	};
58c8d570 BD	625
1da177e4 LT	626	/* Standard BAST devices */
	627
	628	static struct platform_device *bast_devices[] __initdata = {
	629	&s3c_device_usb,
	630	&s3c_device_lcd,
	631	&s3c_device_wdt,
	632	&s3c_device_i2c,
	633	&s3c_device_iis,
	634	&s3c_device_rtc,
	635	&s3c_device_nand,
d97a666f BD	636	&bast_device_nor,
d97a666f BD	637	&bast_device_dm9k,
5ce4b1fe BD	638	&bast_device_asix,
5ce4b1fe BD	639	&bast_device_axpp,
65cc3370	640	&bast_sio,
1da177e4 LT	641	};
	642
	643	static struct clk *bast_clocks[] = {
	644	&s3c24xx_dclk0,
	645	&s3c24xx_dclk1,
	646	&s3c24xx_clkout0,
	647	&s3c24xx_clkout1,
	648	&s3c24xx_uclk,
	649	};
	650
5fe10ab1	651	static void __init bast_map_io(void)
1da177e4 LT	652	{
	653	/* initialise the clocks */
	654
	655	s3c24xx_dclk0.parent = NULL;
	656	s3c24xx_dclk0.rate = 1210001000;
	657
	658	s3c24xx_dclk1.parent = NULL;
	659	s3c24xx_dclk1.rate = 2410001000;
	660
	661	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	662	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	663
	664	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	665
ce89c206 BD	666	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
ce89c206 BD	667
1da177e4	668	s3c_device_nand.dev.platform_data = &bast_nand_info;
1fcf8448	669	s3c_device_i2c.dev.platform_data = &bast_i2c_info;
1da177e4 LT	670
	671	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	672	s3c24xx_init_clocks(0);
	673	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
57e5171c	674
1da177e4 LT	675	usb_simtec_init();
	676	}
	677
58c8d570 BD	678	static void __init bast_init(void)
58c8d570 BD	679	{
09fe75f6	680	s3c24xx_fb_set_platdata(&bast_fb_info);
57e5171c	681	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
58c8d570	682	}
1da177e4 LT	683
1da177e4 LT	684	MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6	685	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
e9dea0c6 RK	686	.phys_io = S3C2410_PA_UART,
	687	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	688	.boot_params = S3C2410_SDRAM_PA + 0x100,
f705b1ae BD	689	.map_io = bast_map_io,
f705b1ae BD	690	.init_irq = s3c24xx_init_irq,
58c8d570	691	.init_machine = bast_init,
1da177e4 LT	692	.timer = &s3c24xx_timer,
1da177e4 LT	693	MACHINE_END