[linux-2.6-block.git] / arch / arm / mach-s3c2410 / mach-bast.c

/* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
 * Copyright (c) 2003-2005,2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <net/ax88796.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/bast-map.h>
#include <mach/bast-irq.h>
#include <mach/bast-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

//#include <asm/debug-ll.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>

#include <plat/nand.h>
#include <plat/iic.h>
#include <mach/fb.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <linux/serial_8250.h>

#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

#include "usb-simtec.h"
#include "nor-simtec.h"

#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"

/* macros for virtual address mods for the io space entries */
#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)

/* macros to modify the physical addresses for io space */

#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))

static struct map_desc bast_iodesc[] __initdata = {
  /* ISA IO areas */
  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= PA_CS2(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= PA_CS3(BAST_PA_ISAIO),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },
  /* bast CPLD control registers, and external interrupt controls */
  {
	  .virtual	= (u32)BAST_VA_CTRL1,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL1),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL2,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL2),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL3,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL3),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_CTRL4,
	  .pfn		= __phys_to_pfn(BAST_PA_CTRL4),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },
  /* PC104 IRQ mux */
  {
	  .virtual	= (u32)BAST_VA_PC104_IRQREQ,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQRAW,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)BAST_VA_PC104_IRQMASK,
	  .pfn		= __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	  .length	= SZ_1M,
	  .type		= MT_DEVICE,
  },

  /* peripheral space... one for each of fast/slow/byte/16bit */
  /* note, ide is only decoded in word space, even though some registers
   * are only 8bit */

  /* slow, byte */
  { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* slow, word */
  { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, byte */
  { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },

  /* fast, word */
  { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
  { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	[0] = {
		.name		= "uclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	},
	[1] = {
		.name		= "pclk",
		.divisor	= 1,
		.min_baud	= 0,
		.max_baud	= 0,
	}
};


static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	},
	/* port 2 is not actually used */
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clocks	     = bast_serial_clocks,
		.clocks_size = ARRAY_SIZE(bast_serial_clocks),
	}
};

/* NAND Flash on BAST board */

#ifdef CONFIG_PM
static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
{
	/* ensure that an nRESET is not generated on resume. */
	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);

	return 0;
}

static int bast_pm_resume(struct sys_device *sd)
{
	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
	return 0;
}

#else
#define bast_pm_suspend NULL
#define bast_pm_resume NULL
#endif

static struct sysdev_class bast_pm_sysclass = {
	.name		= "mach-bast",
	.suspend	= bast_pm_suspend,
	.resume		= bast_pm_resume,
};

static struct sys_device bast_pm_sysdev = {
	.cls		= &bast_pm_sysclass,
};

static int smartmedia_map[] = { 0 };
static int chip0_map[] = { 1 };
static int chip1_map[] = { 2 };
static int chip2_map[] = { 3 };

static struct mtd_partition bast_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user",
		.offset	= SZ_4M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the bast has 4 selectable slots for nand-flash, the three
 * on-board chip areas, as well as the external SmartMedia
 * slot.
 *
 * Note, there is no current hot-plug support for the SmartMedia
 * socket.
*/

static struct s3c2410_nand_set bast_nand_sets[] = {
	[0] = {
		.name		= "SmartMedia",
		.nr_chips	= 1,
		.nr_map		= smartmedia_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[1] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	},
	[3] = {
		.name		= "chip2",
		.nr_chips	= 1,
		.nr_map		= chip2_map,
		.nr_partitions	= ARRAY_SIZE(bast_default_nand_part),
		.partitions	= bast_default_nand_part,
	}
};

static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(BAST_VA_CTRL2);
	tmp &= BAST_CPLD_CTLR2_IDERST;
	tmp |= slot;
	tmp |= BAST_CPLD_CTRL2_WNAND;

	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);

	__raw_writeb(tmp, BAST_VA_CTRL2);
}

static struct s3c2410_platform_nand bast_nand_info = {
	.tacls		= 30,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(bast_nand_sets),
	.sets		= bast_nand_sets,
	.select_chip	= bast_nand_select,
};

/* DM9000 */

static struct resource bast_dm9k_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
		.end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_DM9000,
		.end   = IRQ_DM9000,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
	}

};

/* for the moment we limit ourselves to 16bit IO until some
 * better IO routines can be written and tested
*/

static struct dm9000_plat_data bast_dm9k_platdata = {
	.flags		= DM9000_PLATF_16BITONLY,
};

static struct platform_device bast_device_dm9k = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_dm9k_resource),
	.resource	= bast_dm9k_resource,
	.dev		= {
		.platform_data = &bast_dm9k_platdata,
	}
};

/* serial devices */

#define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
#define SERIAL_CLK   (1843200)

static struct plat_serial8250_port bast_sio_data[] = {
	[0] = {
		.mapbase	= SERIAL_BASE + 0x2f8,
		.irq		= IRQ_PCSERIAL1,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	[1] = {
		.mapbase	= SERIAL_BASE + 0x3f8,
		.irq		= IRQ_PCSERIAL2,
		.flags		= SERIAL_FLAGS,
		.iotype		= UPIO_MEM,
		.regshift	= 0,
		.uartclk	= SERIAL_CLK,
	},
	{ }
};

static struct platform_device bast_sio = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= &bast_sio_data,
	},
};

/* we have devices on the bus which cannot work much over the
 * standard 100KHz i2c bus frequency
*/

static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
	.flags		= 0,
	.slave_addr	= 0x10,
	.frequency	= 100*1000,
};

/* Asix AX88796 10/100 ethernet controller */

static struct ax_plat_data bast_asix_platdata = {
	.flags		= AXFLG_MAC_FROMDEV,
	.wordlength	= 2,
	.dcr_val	= 0x48,
	.rcr_val	= 0x40,
};

static struct resource bast_asix_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET,
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = IRQ_ASIX,
		.end   = IRQ_ASIX,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device bast_device_asix = {
	.name		= "ax88796",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asix_resource),
	.resource	= bast_asix_resource,
	.dev		= {
		.platform_data = &bast_asix_platdata
	}
};

/* Asix AX88796 10/100 ethernet controller parallel port */

static struct resource bast_asixpp_resource[] = {
	[0] = {
		.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
		.end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
		.flags = IORESOURCE_MEM,
	}
};

static struct platform_device bast_device_axpp = {
	.name		= "ax88796-pp",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(bast_asixpp_resource),
	.resource	= bast_asixpp_resource,
};

/* LCD/VGA controller */

static struct s3c2410fb_display __initdata bast_lcd_info[] = {
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 4,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 8,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
	{
		.type		= S3C2410_LCDCON1_TFT,
		.width		= 640,
		.height		= 480,

		.pixclock	= 33333,
		.xres		= 640,
		.yres		= 480,
		.bpp		= 16,
		.left_margin	= 40,
		.right_margin	= 20,
		.hsync_len	= 88,
		.upper_margin	= 30,
		.lower_margin	= 32,
		.vsync_len	= 3,

		.lcdcon5	= 0x00014b02,
	},
};

/* LCD/VGA controller */

static struct s3c2410fb_mach_info __initdata bast_fb_info = {

	.displays = bast_lcd_info,
	.num_displays = ARRAY_SIZE(bast_lcd_info),
	.default_display = 1,
};

/* I2C devices fitted. */

static struct i2c_board_info bast_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tlv320aic23", 0x1a),
	}, {
		I2C_BOARD_INFO("simtec-pmu", 0x6b),
	}, {
		I2C_BOARD_INFO("ch7013", 0x75),
	},
};

/* Standard BAST devices */

static struct platform_device *bast_devices[] __initdata = {
	&s3c_device_usb,
	&s3c_device_lcd,
	&s3c_device_wdt,
	&s3c_device_i2c0,
 	&s3c_device_rtc,
	&s3c_device_nand,
	&bast_device_dm9k,
	&bast_device_asix,
	&bast_device_axpp,
	&bast_sio,
};

static struct clk *bast_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static void __init bast_map_io(void)
{
	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));

	s3c_device_nand.dev.platform_data = &bast_nand_info;

	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
}

static void __init bast_init(void)
{
	sysdev_class_register(&bast_pm_sysclass);
	sysdev_register(&bast_pm_sysdev);

	s3c_i2c0_set_platdata(&bast_i2c_info);
	s3c24xx_fb_set_platdata(&bast_fb_info);
	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));

	i2c_register_board_info(0, bast_i2c_devs,
				ARRAY_SIZE(bast_i2c_devs));

	usb_simtec_init();
	nor_simtec_init();
}

MACHINE_START(BAST, "Simtec-BAST")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.phys_io	= S3C2410_PA_UART,
	.io_pg_offst	= (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	.boot_params	= S3C2410_SDRAM_PA + 0x100,
	.map_io		= bast_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= bast_init,
	.timer		= &s3c24xx_timer,
MACHINE_END
Commit	Line	Data
1da177e4 LT	1	/* linux/arch/arm/mach-s3c2410/mach-bast.c
1da177e4 LT	2	*
042cf0f2	3	* Copyright (c) 2003-2005,2008 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
	5	*
	6	* http://www.simtec.co.uk/products/EB2410ITX/
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/list.h>
	17	#include <linux/timer.h>
	18	#include <linux/init.h>
ec976d6e	19	#include <linux/gpio.h>
6ddc4b07	20	#include <linux/sysdev.h>
b6d1f542	21	#include <linux/serial_core.h>
d052d1be	22	#include <linux/platform_device.h>
d97a666f	23	#include <linux/dm9000.h>
b7a12d19	24	#include <linux/ata_platform.h>
042cf0f2	25	#include <linux/i2c.h>
fced80c7	26	#include <linux/io.h>
1da177e4	27
5ce4b1fe BD	28	#include <net/ax88796.h>
5ce4b1fe BD	29
1da177e4 LT	30	#include <asm/mach/arch.h>
	31	#include <asm/mach/map.h>
	32	#include <asm/mach/irq.h>
	33
a09e64fb RK	34	#include <mach/bast-map.h>
	35	#include <mach/bast-irq.h>
	36	#include <mach/bast-cpld.h>
1da177e4	37
a09e64fb	38	#include <mach/hardware.h>
1da177e4 LT	39	#include <asm/irq.h>
	40	#include <asm/mach-types.h>
	41
	42	//#include <asm/debug-ll.h>
a2b7ba9c	43	#include <plat/regs-serial.h>
a09e64fb RK	44	#include <mach/regs-gpio.h>
	45	#include <mach/regs-mem.h>
	46	#include <mach/regs-lcd.h>
58c8d570	47
7926b5a3	48	#include <plat/nand.h>
9498cb79	49	#include <plat/iic.h>
a09e64fb	50	#include <mach/fb.h>
1da177e4 LT	51
	52	#include <linux/mtd/mtd.h>
	53	#include <linux/mtd/nand.h>
	54	#include <linux/mtd/nand_ecc.h>
	55	#include <linux/mtd/partitions.h>
	56
65cc3370 BD	57	#include <linux/serial_8250.h>
65cc3370 BD	58
d5120ae7	59	#include <plat/clock.h>
a2b7ba9c BD	60	#include <plat/devs.h>
a2b7ba9c BD	61	#include <plat/cpu.h>
9d529c6e	62
1da177e4	63	#include "usb-simtec.h"
9d529c6e	64	#include "nor-simtec.h"
1da177e4 LT	65
	66	#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
	67
	68	/* macros for virtual address mods for the io space entries */
	69	#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
	70	#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
	71	#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
	72	#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
	73
	74	/* macros to modify the physical addresses for io space */
	75
1d23b65d BD	76	#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
	77	#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
	78	#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
	79	#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
1da177e4 LT	80
	81	static struct map_desc bast_iodesc[] __initdata = {
	82	/* ISA IO areas */
1d23b65d BD	83	{
	84	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	85	.pfn = PA_CS2(BAST_PA_ISAIO),
	86	.length = SZ_16M,
	87	.type = MT_DEVICE,
	88	}, {
	89	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	90	.pfn = PA_CS3(BAST_PA_ISAIO),
	91	.length = SZ_16M,
	92	.type = MT_DEVICE,
	93	},
1da177e4	94	/* bast CPLD control registers, and external interrupt controls */
1d23b65d BD	95	{
	96	.virtual = (u32)BAST_VA_CTRL1,
	97	.pfn = __phys_to_pfn(BAST_PA_CTRL1),
	98	.length = SZ_1M,
	99	.type = MT_DEVICE,
	100	}, {
	101	.virtual = (u32)BAST_VA_CTRL2,
	102	.pfn = __phys_to_pfn(BAST_PA_CTRL2),
	103	.length = SZ_1M,
	104	.type = MT_DEVICE,
	105	}, {
	106	.virtual = (u32)BAST_VA_CTRL3,
	107	.pfn = __phys_to_pfn(BAST_PA_CTRL3),
	108	.length = SZ_1M,
	109	.type = MT_DEVICE,
	110	}, {
	111	.virtual = (u32)BAST_VA_CTRL4,
	112	.pfn = __phys_to_pfn(BAST_PA_CTRL4),
	113	.length = SZ_1M,
	114	.type = MT_DEVICE,
	115	},
1da177e4	116	/* PC104 IRQ mux */
1d23b65d BD	117	{
	118	.virtual = (u32)BAST_VA_PC104_IRQREQ,
	119	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
	120	.length = SZ_1M,
	121	.type = MT_DEVICE,
	122	}, {
	123	.virtual = (u32)BAST_VA_PC104_IRQRAW,
	124	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
	125	.length = SZ_1M,
	126	.type = MT_DEVICE,
	127	}, {
	128	.virtual = (u32)BAST_VA_PC104_IRQMASK,
	129	.pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
	130	.length = SZ_1M,
	131	.type = MT_DEVICE,
	132	},
1da177e4 LT	133
	134	/* peripheral space... one for each of fast/slow/byte/16bit */
	135	/* note, ide is only decoded in word space, even though some registers
	136	* are only 8bit */
	137
	138	/* slow, byte */
	139	{ VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	140	{ VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	141	{ VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	142
	143	/* slow, word */
	144	{ VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	145	{ VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	146	{ VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	147
	148	/* fast, byte */
	149	{ VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	150	{ VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	151	{ VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	152
	153	/* fast, word */
	154	{ VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
	155	{ VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4	156	{ VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4 LT	157	};
	158
	159	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	160	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	161	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	162
	163	static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
	164	[0] = {
	165	.name = "uclk",
	166	.divisor = 1,
	167	.min_baud = 0,
	168	.max_baud = 0,
	169	},
	170	[1] = {
	171	.name = "pclk",
	172	.divisor = 1,
	173	.min_baud = 0,
b526bf23	174	.max_baud = 0,
1da177e4 LT	175	}
	176	};
	177
	178
66a9b49a	179	static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
1da177e4 LT	180	[0] = {
	181	.hwport = 0,
	182	.flags = 0,
	183	.ucon = UCON,
	184	.ulcon = ULCON,
	185	.ufcon = UFCON,
	186	.clocks = bast_serial_clocks,
b526bf23	187	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	188	},
	189	[1] = {
	190	.hwport = 1,
	191	.flags = 0,
	192	.ucon = UCON,
	193	.ulcon = ULCON,
	194	.ufcon = UFCON,
	195	.clocks = bast_serial_clocks,
b526bf23	196	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	197	},
	198	/* port 2 is not actually used */
	199	[2] = {
	200	.hwport = 2,
	201	.flags = 0,
	202	.ucon = UCON,
	203	.ulcon = ULCON,
	204	.ufcon = UFCON,
	205	.clocks = bast_serial_clocks,
b526bf23	206	.clocks_size = ARRAY_SIZE(bast_serial_clocks),
1da177e4 LT	207	}
	208	};
	209
1da177e4 LT	210	/* NAND Flash on BAST board */
1da177e4 LT	211
6ddc4b07 BD	212	#ifdef CONFIG_PM
	213	static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
	214	{
	215	/* ensure that an nRESET is not generated on resume. */
070276d5 BD	216	s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
070276d5 BD	217	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
6ddc4b07 BD	218
	219	return 0;
	220	}
	221
	222	static int bast_pm_resume(struct sys_device *sd)
	223	{
070276d5	224	s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
6ddc4b07 BD	225	return 0;
	226	}
	227
	228	#else
	229	#define bast_pm_suspend NULL
	230	#define bast_pm_resume NULL
	231	#endif
	232
	233	static struct sysdev_class bast_pm_sysclass = {
140749e2	234	.name = "mach-bast",
6ddc4b07 BD	235	.suspend = bast_pm_suspend,
	236	.resume = bast_pm_resume,
	237	};
	238
	239	static struct sys_device bast_pm_sysdev = {
	240	.cls = &bast_pm_sysclass,
	241	};
1da177e4 LT	242
	243	static int smartmedia_map[] = { 0 };
	244	static int chip0_map[] = { 1 };
	245	static int chip1_map[] = { 2 };
	246	static int chip2_map[] = { 3 };
	247
9f693d7b	248	static struct mtd_partition bast_default_nand_part[] = {
1da177e4 LT	249	[0] = {
	250	.name = "Boot Agent",
	251	.size = SZ_16K,
b526bf23	252	.offset = 0,
1da177e4 LT	253	},
	254	[1] = {
	255	.name = "/boot",
	256	.size = SZ_4M - SZ_16K,
	257	.offset = SZ_16K,
	258	},
	259	[2] = {
	260	.name = "user",
	261	.offset = SZ_4M,
	262	.size = MTDPART_SIZ_FULL,
	263	}
	264	};
	265
	266	/* the bast has 4 selectable slots for nand-flash, the three
	267	* on-board chip areas, as well as the external SmartMedia
	268	* slot.
	269	*
	270	* Note, there is no current hot-plug support for the SmartMedia
	271	* socket.
	272	*/
	273
	274	static struct s3c2410_nand_set bast_nand_sets[] = {
	275	[0] = {
	276	.name = "SmartMedia",
	277	.nr_chips = 1,
	278	.nr_map = smartmedia_map,
	279	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	280	.partitions = bast_default_nand_part,
1da177e4 LT	281	},
	282	[1] = {
	283	.name = "chip0",
	284	.nr_chips = 1,
	285	.nr_map = chip0_map,
	286	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	287	.partitions = bast_default_nand_part,
1da177e4 LT	288	},
	289	[2] = {
	290	.name = "chip1",
	291	.nr_chips = 1,
	292	.nr_map = chip1_map,
	293	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	294	.partitions = bast_default_nand_part,
1da177e4 LT	295	},
	296	[3] = {
	297	.name = "chip2",
	298	.nr_chips = 1,
	299	.nr_map = chip2_map,
	300	.nr_partitions = ARRAY_SIZE(bast_default_nand_part),
b526bf23	301	.partitions = bast_default_nand_part,
1da177e4 LT	302	}
	303	};
	304
	305	static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
	306	{
	307	unsigned int tmp;
	308
	309	slot = set->nr_map[slot] & 3;
	310
	311	pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
	312	slot, set, set->nr_map);
	313
	314	tmp = __raw_readb(BAST_VA_CTRL2);
	315	tmp &= BAST_CPLD_CTLR2_IDERST;
	316	tmp \|= slot;
	317	tmp \|= BAST_CPLD_CTRL2_WNAND;
	318
	319	pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
	320
	321	__raw_writeb(tmp, BAST_VA_CTRL2);
	322	}
	323
	324	static struct s3c2410_platform_nand bast_nand_info = {
b048dbf4 BD	325	.tacls = 30,
	326	.twrph0 = 60,
	327	.twrph1 = 60,
1da177e4 LT	328	.nr_sets = ARRAY_SIZE(bast_nand_sets),
	329	.sets = bast_nand_sets,
	330	.select_chip = bast_nand_select,
	331	};
	332
d97a666f BD	333	/* DM9000 */
	334
	335	static struct resource bast_dm9k_resource[] = {
	336	[0] = {
	337	.start = S3C2410_CS5 + BAST_PA_DM9000,
	338	.end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
b526bf23	339	.flags = IORESOURCE_MEM,
d97a666f BD	340	},
	341	[1] = {
	342	.start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
	343	.end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
b526bf23	344	.flags = IORESOURCE_MEM,
d97a666f BD	345	},
	346	[2] = {
	347	.start = IRQ_DM9000,
	348	.end = IRQ_DM9000,
9cf345e3	349	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHLEVEL,
d97a666f BD	350	}
	351
	352	};
	353
	354	/* for the moment we limit ourselves to 16bit IO until some
	355	* better IO routines can be written and tested
	356	*/
	357
9f693d7b	358	static struct dm9000_plat_data bast_dm9k_platdata = {
b526bf23	359	.flags = DM9000_PLATF_16BITONLY,
d97a666f BD	360	};
	361
	362	static struct platform_device bast_device_dm9k = {
	363	.name = "dm9000",
	364	.id = 0,
	365	.num_resources = ARRAY_SIZE(bast_dm9k_resource),
	366	.resource = bast_dm9k_resource,
	367	.dev = {
	368	.platform_data = &bast_dm9k_platdata,
	369	}
	370	};
	371
65cc3370 BD	372	/* serial devices */
	373
	374	#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
	375	#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF \| UPF_IOREMAP \| UPF_SHARE_IRQ)
	376	#define SERIAL_CLK (1843200)
	377
	378	static struct plat_serial8250_port bast_sio_data[] = {
	379	[0] = {
	380	.mapbase = SERIAL_BASE + 0x2f8,
	381	.irq = IRQ_PCSERIAL1,
	382	.flags = SERIAL_FLAGS,
	383	.iotype = UPIO_MEM,
	384	.regshift = 0,
	385	.uartclk = SERIAL_CLK,
	386	},
	387	[1] = {
	388	.mapbase = SERIAL_BASE + 0x3f8,
	389	.irq = IRQ_PCSERIAL2,
	390	.flags = SERIAL_FLAGS,
	391	.iotype = UPIO_MEM,
	392	.regshift = 0,
	393	.uartclk = SERIAL_CLK,
	394	},
	395	{ }
	396	};
	397
	398	static struct platform_device bast_sio = {
	399	.name = "serial8250",
6df29deb	400	.id = PLAT8250_DEV_PLATFORM,
65cc3370 BD	401	.dev = {
	402	.platform_data = &bast_sio_data,
	403	},
	404	};
1da177e4	405
1fcf8448 BD	406	/* we have devices on the bus which cannot work much over the
	407	* standard 100KHz i2c bus frequency
	408	*/
	409
3e1b776c	410	static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
1fcf8448 BD	411	.flags = 0,
1fcf8448 BD	412	.slave_addr = 0x10,
c564e6ae	413	.frequency = 100*1000,
1fcf8448 BD	414	};
1fcf8448 BD	415
5ce4b1fe BD	416	/* Asix AX88796 10/100 ethernet controller */
	417
	418	static struct ax_plat_data bast_asix_platdata = {
	419	.flags = AXFLG_MAC_FROMDEV,
	420	.wordlength = 2,
	421	.dcr_val = 0x48,
	422	.rcr_val = 0x40,
	423	};
	424
	425	static struct resource bast_asix_resource[] = {
	426	[0] = {
	427	.start = S3C2410_CS5 + BAST_PA_ASIXNET,
	428	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
	429	.flags = IORESOURCE_MEM,
	430	},
	431	[1] = {
	432	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	433	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
	434	.flags = IORESOURCE_MEM,
	435	},
	436	[2] = {
	437	.start = IRQ_ASIX,
	438	.end = IRQ_ASIX,
	439	.flags = IORESOURCE_IRQ
	440	}
	441	};
	442
	443	static struct platform_device bast_device_asix = {
	444	.name = "ax88796",
	445	.id = 0,
	446	.num_resources = ARRAY_SIZE(bast_asix_resource),
	447	.resource = bast_asix_resource,
	448	.dev = {
	449	.platform_data = &bast_asix_platdata
	450	}
	451	};
	452
	453	/* Asix AX88796 10/100 ethernet controller parallel port */
	454
	455	static struct resource bast_asixpp_resource[] = {
	456	[0] = {
	457	.start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
	458	.end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
	459	.flags = IORESOURCE_MEM,
	460	}
	461	};
	462
	463	static struct platform_device bast_device_axpp = {
	464	.name = "ax88796-pp",
	465	.id = 0,
	466	.num_resources = ARRAY_SIZE(bast_asixpp_resource),
	467	.resource = bast_asixpp_resource,
	468	};
	469
	470	/* LCD/VGA controller */
58c8d570	471
09fe75f6 KH	472	static struct s3c2410fb_display __initdata bast_lcd_info[] = {
09fe75f6 KH	473	{
1f411537	474	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	475	.width = 640,
09fe75f6 KH	476	.height = 480,
5f20f69b	477
69816699	478	.pixclock = 33333,
09fe75f6 KH	479	.xres = 640,
	480	.yres = 480,
	481	.bpp = 4,
1f411537 KH	482	.left_margin = 40,
1f411537 KH	483	.right_margin = 20,
93d11f5a	484	.hsync_len = 88,
5f20f69b KH	485	.upper_margin = 30,
5f20f69b KH	486	.lower_margin = 32,
93d11f5a	487	.vsync_len = 3,
09fe75f6	488
f28ef573	489	.lcdcon5 = 0x00014b02,
58c8d570	490	},
09fe75f6	491	{
1f411537	492	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	493	.width = 640,
	494	.height = 480,
	495
69816699	496	.pixclock = 33333,
09fe75f6 KH	497	.xres = 640,
	498	.yres = 480,
	499	.bpp = 8,
1f411537 KH	500	.left_margin = 40,
1f411537 KH	501	.right_margin = 20,
93d11f5a	502	.hsync_len = 88,
5f20f69b KH	503	.upper_margin = 30,
5f20f69b KH	504	.lower_margin = 32,
93d11f5a	505	.vsync_len = 3,
09fe75f6	506
f28ef573	507	.lcdcon5 = 0x00014b02,
09fe75f6 KH	508	},
09fe75f6 KH	509	{
1f411537	510	.type = S3C2410_LCDCON1_TFT,
09fe75f6 KH	511	.width = 640,
	512	.height = 480,
	513
69816699	514	.pixclock = 33333,
09fe75f6 KH	515	.xres = 640,
	516	.yres = 480,
	517	.bpp = 16,
1f411537 KH	518	.left_margin = 40,
1f411537 KH	519	.right_margin = 20,
93d11f5a	520	.hsync_len = 88,
5f20f69b KH	521	.upper_margin = 30,
5f20f69b KH	522	.lower_margin = 32,
93d11f5a	523	.vsync_len = 3,
09fe75f6	524
f28ef573	525	.lcdcon5 = 0x00014b02,
09fe75f6 KH	526	},
09fe75f6 KH	527	};
58c8d570	528
09fe75f6 KH	529	/* LCD/VGA controller */
	530
	531	static struct s3c2410fb_mach_info __initdata bast_fb_info = {
	532
	533	.displays = bast_lcd_info,
	534	.num_displays = ARRAY_SIZE(bast_lcd_info),
9cbae12c	535	.default_display = 1,
58c8d570 BD	536	};
58c8d570 BD	537
042cf0f2 BD	538	/* I2C devices fitted. */
	539
	540	static struct i2c_board_info bast_i2c_devs[] __initdata = {
	541	{
	542	I2C_BOARD_INFO("tlv320aic23", 0x1a),
	543	}, {
	544	I2C_BOARD_INFO("simtec-pmu", 0x6b),
	545	}, {
	546	I2C_BOARD_INFO("ch7013", 0x75),
	547	},
	548	};
b7a12d19	549
1da177e4 LT	550	/* Standard BAST devices */
	551
	552	static struct platform_device *bast_devices[] __initdata = {
	553	&s3c_device_usb,
	554	&s3c_device_lcd,
	555	&s3c_device_wdt,
3e1b776c	556	&s3c_device_i2c0,
1da177e4 LT	557	&s3c_device_rtc,
1da177e4 LT	558	&s3c_device_nand,
d97a666f	559	&bast_device_dm9k,
5ce4b1fe BD	560	&bast_device_asix,
5ce4b1fe BD	561	&bast_device_axpp,
65cc3370	562	&bast_sio,
1da177e4 LT	563	};
1da177e4 LT	564
2bc7509f	565	static struct clk *bast_clocks[] __initdata = {
1da177e4 LT	566	&s3c24xx_dclk0,
	567	&s3c24xx_dclk1,
	568	&s3c24xx_clkout0,
	569	&s3c24xx_clkout1,
	570	&s3c24xx_uclk,
	571	};
	572
5fe10ab1	573	static void __init bast_map_io(void)
1da177e4 LT	574	{
	575	/* initialise the clocks */
	576
d96a9804	577	s3c24xx_dclk0.parent = &clk_upll;
1da177e4 LT	578	s3c24xx_dclk0.rate = 1210001000;
1da177e4 LT	579
d96a9804	580	s3c24xx_dclk1.parent = &clk_upll;
1da177e4 LT	581	s3c24xx_dclk1.rate = 2410001000;
	582
	583	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	584	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	585
	586	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	587
ce89c206 BD	588	s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
ce89c206 BD	589
1da177e4	590	s3c_device_nand.dev.platform_data = &bast_nand_info;
3e1b776c	591
1da177e4 LT	592	s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
	593	s3c24xx_init_clocks(0);
	594	s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
1da177e4 LT	595	}
1da177e4 LT	596
58c8d570 BD	597	static void __init bast_init(void)
58c8d570 BD	598	{
6ddc4b07 BD	599	sysdev_class_register(&bast_pm_sysclass);
	600	sysdev_register(&bast_pm_sysdev);
	601
a8af6de0	602	s3c_i2c0_set_platdata(&bast_i2c_info);
09fe75f6	603	s3c24xx_fb_set_platdata(&bast_fb_info);
57e5171c	604	platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
9d529c6e	605
042cf0f2 BD	606	i2c_register_board_info(0, bast_i2c_devs,
	607	ARRAY_SIZE(bast_i2c_devs));
	608
7a05a2cb	609	usb_simtec_init();
9d529c6e	610	nor_simtec_init();
58c8d570	611	}
1da177e4 LT	612
1da177e4 LT	613	MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6	614	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
e9dea0c6 RK	615	.phys_io = S3C2410_PA_UART,
	616	.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
	617	.boot_params = S3C2410_SDRAM_PA + 0x100,
f705b1ae BD	618	.map_io = bast_map_io,
f705b1ae BD	619	.init_irq = s3c24xx_init_irq,
58c8d570	620	.init_machine = bast_init,
1da177e4 LT	621	.timer = &s3c24xx_timer,
1da177e4 LT	622	MACHINE_END