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[PATCH] Xmon bug fix for soft-reset
[linux-2.6-block.git] / arch / arm / mach-s3c2410 / mach-bast.c
CommitLineData
1da177e4
LT		 1/* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 14-Sep-2004 BJD USB power control
14 * 20-Aug-2004 BJD Added s3c2410_board struct
15 * 18-Aug-2004 BJD Added platform devices from default set
16 * 16-May-2003 BJD Created initial version
17 * 16-Aug-2003 BJD Fixed header files and copyright, added URL
18 * 05-Sep-2003 BJD Moved to v2.6 kernel
19 * 06-Jan-2003 BJD Updates for <arch/map.h>
20 * 18-Jan-2003 BJD Added serial port configuration
21 * 05-Oct-2004 BJD Power management code
22 * 04-Nov-2004 BJD Updated serial port clocks
23 * 04-Jan-2005 BJD New uart init call
24 * 10-Jan-2005 BJD Removed include of s3c2410.h
25 * 14-Jan-2005 BJD Add support for muitlple NAND devices
26 * 03-Mar-2005 BJD Ensured that bast-cpld.h is included
27 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
5730b7d6
BD		 28 * 14-Mar-2005 BJD Updated for __iomem changes
29 * 22-Jun-2005 BJD Added DM9000 platform information
30 * 28-Jun-2005 BJD Moved pm functionality out to common code
31 * 17-Jul-2005 BJD Changed to platform device for SuperIO 16550s
32 * 25-Jul-2005 BJD Removed ASIX static mappings
1da177e4
LT		 33*/
34
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/interrupt.h>
38#include <linux/list.h>
39#include <linux/timer.h>
40#include <linux/init.h>
41#include <linux/device.h>
d97a666f 42#include <linux/dm9000.h>
1da177e4
LT		 43
44#include <asm/mach/arch.h>
45#include <asm/mach/map.h>
46#include <asm/mach/irq.h>
47
48#include <asm/arch/bast-map.h>
49#include <asm/arch/bast-irq.h>
50#include <asm/arch/bast-cpld.h>
51
52#include <asm/hardware.h>
53#include <asm/io.h>
54#include <asm/irq.h>
55#include <asm/mach-types.h>
56
57//#include <asm/debug-ll.h>
58#include <asm/arch/regs-serial.h>
59#include <asm/arch/regs-gpio.h>
60#include <asm/arch/regs-mem.h>
d97a666f 61#include <asm/arch/regs-lcd.h>
1da177e4
LT		 62#include <asm/arch/nand.h>
63
64#include <linux/mtd/mtd.h>
65#include <linux/mtd/nand.h>
66#include <linux/mtd/nand_ecc.h>
67#include <linux/mtd/partitions.h>
68
65cc3370
BD		 69#include <linux/serial_8250.h>
70
1da177e4
LT		 71#include "clock.h"
72#include "devs.h"
73#include "cpu.h"
74#include "usb-simtec.h"
1da177e4
LT		 75
76#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
77
78/* macros for virtual address mods for the io space entries */
79#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
80#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
81#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
82#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
83
84/* macros to modify the physical addresses for io space */
85
86#define PA_CS2(item) ((item) + S3C2410_CS2)
87#define PA_CS3(item) ((item) + S3C2410_CS3)
88#define PA_CS4(item) ((item) + S3C2410_CS4)
89#define PA_CS5(item) ((item) + S3C2410_CS5)
90
91static struct map_desc bast_iodesc[] __initdata = {
92 /* ISA IO areas */
93
94 { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
95 { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
96
97 /* we could possibly compress the next set down into a set of smaller tables
98 * pagetables, but that would mean using an L2 section, and it still means
99 * we cannot actually feed the same register to an LDR due to 16K spacing
100 */
101
102 /* bast CPLD control registers, and external interrupt controls */
103 { (u32)BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE },
104 { (u32)BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE },
105 { (u32)BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE },
106 { (u32)BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE },
107
108 /* PC104 IRQ mux */
109 { (u32)BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE },
110 { (u32)BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE },
111 { (u32)BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE },
112
113 /* peripheral space... one for each of fast/slow/byte/16bit */
114 /* note, ide is only decoded in word space, even though some registers
115 * are only 8bit */
116
117 /* slow, byte */
118 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
119 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4 120 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4
LT		 121 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
122 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
123 { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
124 { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
125
126 /* slow, word */
127 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
128 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4 129 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4
LT		 130 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
131 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
132 { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
133 { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
134
135 /* fast, byte */
136 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
137 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4 138 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4
LT		 139 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
140 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
141 { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
142 { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
143
144 /* fast, word */
145 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
146 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
1da177e4 147 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
1da177e4
LT		 148 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
149 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
150 { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
151 { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
152};
153
154#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
155#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
156#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
157
158static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
159 [0] = {
160 .name = "uclk",
161 .divisor = 1,
162 .min_baud = 0,
163 .max_baud = 0,
164 },
165 [1] = {
166 .name = "pclk",
167 .divisor = 1,
168 .min_baud = 0,
169 .max_baud = 0.
170 }
171};
172
173
174static struct s3c2410_uartcfg bast_uartcfgs[] = {
175 [0] = {
176 .hwport = 0,
177 .flags = 0,
178 .ucon = UCON,
179 .ulcon = ULCON,
180 .ufcon = UFCON,
181 .clocks = bast_serial_clocks,
182 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
183 },
184 [1] = {
185 .hwport = 1,
186 .flags = 0,
187 .ucon = UCON,
188 .ulcon = ULCON,
189 .ufcon = UFCON,
190 .clocks = bast_serial_clocks,
191 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
192 },
193 /* port 2 is not actually used */
194 [2] = {
195 .hwport = 2,
196 .flags = 0,
197 .ucon = UCON,
198 .ulcon = ULCON,
199 .ufcon = UFCON,
200 .clocks = bast_serial_clocks,
201 .clocks_size = ARRAY_SIZE(bast_serial_clocks)
202 }
203};
204
205/* NOR Flash on BAST board */
206
207static struct resource bast_nor_resource[] = {
208 [0] = {
209 .start = S3C2410_CS1 + 0x4000000,
210 .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
211 .flags = IORESOURCE_MEM,
212 }
213};
214
215static struct platform_device bast_device_nor = {
216 .name = "bast-nor",
217 .id = -1,
218 .num_resources = ARRAY_SIZE(bast_nor_resource),
219 .resource = bast_nor_resource,
220};
221
222/* NAND Flash on BAST board */
223
224
225static int smartmedia_map[] = { 0 };
226static int chip0_map[] = { 1 };
227static int chip1_map[] = { 2 };
228static int chip2_map[] = { 3 };
229
230struct mtd_partition bast_default_nand_part[] = {
231 [0] = {
232 .name = "Boot Agent",
233 .size = SZ_16K,
234 .offset = 0
235 },
236 [1] = {
237 .name = "/boot",
238 .size = SZ_4M - SZ_16K,
239 .offset = SZ_16K,
240 },
241 [2] = {
242 .name = "user",
243 .offset = SZ_4M,
244 .size = MTDPART_SIZ_FULL,
245 }
246};
247
248/* the bast has 4 selectable slots for nand-flash, the three
249 * on-board chip areas, as well as the external SmartMedia
250 * slot.
251 *
252 * Note, there is no current hot-plug support for the SmartMedia
253 * socket.
254*/
255
256static struct s3c2410_nand_set bast_nand_sets[] = {
257 [0] = {
258 .name = "SmartMedia",
259 .nr_chips = 1,
260 .nr_map = smartmedia_map,
261 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
262 .partitions = bast_default_nand_part
263 },
264 [1] = {
265 .name = "chip0",
266 .nr_chips = 1,
267 .nr_map = chip0_map,
268 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
269 .partitions = bast_default_nand_part
270 },
271 [2] = {
272 .name = "chip1",
273 .nr_chips = 1,
274 .nr_map = chip1_map,
275 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
276 .partitions = bast_default_nand_part
277 },
278 [3] = {
279 .name = "chip2",
280 .nr_chips = 1,
281 .nr_map = chip2_map,
282 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
283 .partitions = bast_default_nand_part
284 }
285};
286
287static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
288{
289 unsigned int tmp;
290
291 slot = set->nr_map[slot] & 3;
292
293 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
294 slot, set, set->nr_map);
295
296 tmp = __raw_readb(BAST_VA_CTRL2);
297 tmp &= BAST_CPLD_CTLR2_IDERST;
298 tmp |= slot;
299 tmp |= BAST_CPLD_CTRL2_WNAND;
300
301 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
302
303 __raw_writeb(tmp, BAST_VA_CTRL2);
304}
305
306static struct s3c2410_platform_nand bast_nand_info = {
307 .tacls = 80,
308 .twrph0 = 80,
309 .twrph1 = 80,
310 .nr_sets = ARRAY_SIZE(bast_nand_sets),
311 .sets = bast_nand_sets,
312 .select_chip = bast_nand_select,
313};
314
d97a666f
BD		 315/* DM9000 */
316
317static struct resource bast_dm9k_resource[] = {
318 [0] = {
319 .start = S3C2410_CS5 + BAST_PA_DM9000,
320 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
321 .flags = IORESOURCE_MEM
322 },
323 [1] = {
324 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
325 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
326 .flags = IORESOURCE_MEM
327 },
328 [2] = {
329 .start = IRQ_DM9000,
330 .end = IRQ_DM9000,
331 .flags = IORESOURCE_IRQ
332 }
333
334};
335
336/* for the moment we limit ourselves to 16bit IO until some
337 * better IO routines can be written and tested
338*/
339
340struct dm9000_plat_data bast_dm9k_platdata = {
341 .flags = DM9000_PLATF_16BITONLY
342};
343
344static struct platform_device bast_device_dm9k = {
345 .name = "dm9000",
346 .id = 0,
347 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
348 .resource = bast_dm9k_resource,
349 .dev = {
350 .platform_data = &bast_dm9k_platdata,
351 }
352};
353
65cc3370
BD		 354/* serial devices */
355
356#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
357#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
358#define SERIAL_CLK (1843200)
359
360static struct plat_serial8250_port bast_sio_data[] = {
361 [0] = {
362 .mapbase = SERIAL_BASE + 0x2f8,
363 .irq = IRQ_PCSERIAL1,
364 .flags = SERIAL_FLAGS,
365 .iotype = UPIO_MEM,
366 .regshift = 0,
367 .uartclk = SERIAL_CLK,
368 },
369 [1] = {
370 .mapbase = SERIAL_BASE + 0x3f8,
371 .irq = IRQ_PCSERIAL2,
372 .flags = SERIAL_FLAGS,
373 .iotype = UPIO_MEM,
374 .regshift = 0,
375 .uartclk = SERIAL_CLK,
376 },
377 { }
378};
379
380static struct platform_device bast_sio = {
381 .name = "serial8250",
382 .id = 0,
383 .dev = {
384 .platform_data = &bast_sio_data,
385 },
386};
1da177e4
LT		 387
388/* Standard BAST devices */
389
390static struct platform_device *bast_devices[] __initdata = {
391 &s3c_device_usb,
392 &s3c_device_lcd,
393 &s3c_device_wdt,
394 &s3c_device_i2c,
395 &s3c_device_iis,
396 &s3c_device_rtc,
397 &s3c_device_nand,
d97a666f
BD		 398 &bast_device_nor,
399 &bast_device_dm9k,
65cc3370 400 &bast_sio,
1da177e4
LT		 401};
402
403static struct clk *bast_clocks[] = {
404 &s3c24xx_dclk0,
405 &s3c24xx_dclk1,
406 &s3c24xx_clkout0,
407 &s3c24xx_clkout1,
408 &s3c24xx_uclk,
409};
410
411static struct s3c24xx_board bast_board __initdata = {
412 .devices = bast_devices,
413 .devices_count = ARRAY_SIZE(bast_devices),
414 .clocks = bast_clocks,
415 .clocks_count = ARRAY_SIZE(bast_clocks)
416};
417
418void __init bast_map_io(void)
419{
420 /* initialise the clocks */
421
422 s3c24xx_dclk0.parent = NULL;
423 s3c24xx_dclk0.rate = 12*1000*1000;
424
425 s3c24xx_dclk1.parent = NULL;
426 s3c24xx_dclk1.rate = 24*1000*1000;
427
428 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
429 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
430
431 s3c24xx_uclk.parent = &s3c24xx_clkout1;
432
433 s3c_device_nand.dev.platform_data = &bast_nand_info;
434
435 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
436 s3c24xx_init_clocks(0);
437 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
438 s3c24xx_set_board(&bast_board);
439 usb_simtec_init();
440}
441
1da177e4
LT		 442
443MACHINE_START(BAST, "Simtec-BAST")
e9dea0c6
RK		 444 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
445 .phys_ram = S3C2410_SDRAM_PA,
446 .phys_io = S3C2410_PA_UART,
447 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
448 .boot_params = S3C2410_SDRAM_PA + 0x100,
f705b1ae
BD		 449 .map_io = bast_map_io,
450 .init_irq = s3c24xx_init_irq,
1da177e4
LT		 451 .timer = &s3c24xx_timer,
452MACHINE_END
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