[linux-2.6-block.git] / arch / arm / mach-s3c2410 / include / mach / map.h

/* arch/arm/mach-s3c2410/include/mach/map.h
 *
 * Copyright (c) 2003 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 - Memory map definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H

#include <plat/map-base.h>
#include <plat/map.h>

#define S3C2410_ADDR(x)		S3C_ADDR(x)

/* USB host controller */
#define S3C2410_PA_USBHOST (0x49000000)

/* DMA controller */
#define S3C2410_PA_DMA	   (0x4B000000)
#define S3C24XX_SZ_DMA	   SZ_1M

/* Clock and Power management */
#define S3C2410_PA_CLKPWR  (0x4C000000)

/* LCD controller */
#define S3C2410_PA_LCD	   (0x4D000000)
#define S3C24XX_SZ_LCD	   SZ_1M

/* NAND flash controller */
#define S3C2410_PA_NAND	   (0x4E000000)

/* IIC hardware controller */
#define S3C2410_PA_IIC	   (0x54000000)

/* IIS controller */
#define S3C2410_PA_IIS	   (0x55000000)

/* RTC */
#define S3C2410_PA_RTC	   (0x57000000)
#define S3C24XX_SZ_RTC	   SZ_1M

/* ADC */
#define S3C2410_PA_ADC	   (0x58000000)

/* SPI */
#define S3C2410_PA_SPI	   (0x59000000)

/* SDI */
#define S3C2410_PA_SDI	   (0x5A000000)

/* CAMIF */
#define S3C2440_PA_CAMIF   (0x4F000000)
#define S3C2440_SZ_CAMIF   SZ_1M

/* AC97 */

#define S3C2440_PA_AC97	   (0x5B000000)
#define S3C2440_SZ_AC97	   SZ_1M

/* S3C2443 High-speed SD/MMC */
#define S3C2443_PA_HSMMC   (0x4A800000)
#define S3C2443_SZ_HSMMC   (256)

/* physical addresses of all the chip-select areas */

#define S3C2410_CS0 (0x00000000)
#define S3C2410_CS1 (0x08000000)
#define S3C2410_CS2 (0x10000000)
#define S3C2410_CS3 (0x18000000)
#define S3C2410_CS4 (0x20000000)
#define S3C2410_CS5 (0x28000000)
#define S3C2410_CS6 (0x30000000)
#define S3C2410_CS7 (0x38000000)

#define S3C2410_SDRAM_PA    (S3C2410_CS6)

/* Use a single interface for common resources between S3C24XX cpus */

#define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
#define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
#define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
#define S3C24XX_PA_DMA      S3C2410_PA_DMA
#define S3C24XX_PA_CLKPWR   S3C2410_PA_CLKPWR
#define S3C24XX_PA_LCD      S3C2410_PA_LCD
#define S3C24XX_PA_UART     S3C2410_PA_UART
#define S3C24XX_PA_TIMER    S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV   S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIS      S3C2410_PA_IIS
#define S3C24XX_PA_GPIO     S3C2410_PA_GPIO
#define S3C24XX_PA_RTC      S3C2410_PA_RTC
#define S3C24XX_PA_ADC      S3C2410_PA_ADC
#define S3C24XX_PA_SPI      S3C2410_PA_SPI
#define S3C24XX_PA_SDI      S3C2410_PA_SDI
#define S3C24XX_PA_NAND	    S3C2410_PA_NAND

#define S3C_PA_IIC          S3C2410_PA_IIC
#define S3C_PA_UART	    S3C24XX_PA_UART
#define S3C_PA_HSMMC0	    S3C2443_PA_HSMMC

#endif /* __ASM_ARCH_MAP_H */
Commit	Line	Data
a09e64fb	1	/* arch/arm/mach-s3c2410/include/mach/map.h
1da177e4	2	*
f056076e BD	3	* Copyright (c) 2003 Simtec Electronics
f056076e BD	4	* Ben Dooks <ben@simtec.co.uk>
1da177e4 LT	5	*
	6	* S3C2410 - Memory map definitions
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
1da177e4 LT	11	*/
	12
	13	#ifndef __ASM_ARCH_MAP_H
	14	#define __ASM_ARCH_MAP_H
	15
ce46a9c4	16	#include <plat/map-base.h>
d5120ae7	17	#include <plat/map.h>
1da177e4	18
530ef3c2	19	#define S3C2410_ADDR(x) S3C_ADDR(x)
1da177e4	20
1da177e4	21	/* USB host controller */
1da177e4	22	#define S3C2410_PA_USBHOST (0x49000000)
1da177e4 LT	23
1da177e4 LT	24	/* DMA controller */
1da177e4 LT	25	#define S3C2410_PA_DMA (0x4B000000)
	26	#define S3C24XX_SZ_DMA SZ_1M
	27
	28	/* Clock and Power management */
1da177e4	29	#define S3C2410_PA_CLKPWR (0x4C000000)
1da177e4 LT	30
1da177e4 LT	31	/* LCD controller */
1da177e4 LT	32	#define S3C2410_PA_LCD (0x4D000000)
	33	#define S3C24XX_SZ_LCD SZ_1M
	34
	35	/* NAND flash controller */
1da177e4	36	#define S3C2410_PA_NAND (0x4E000000)
1da177e4 LT	37
1da177e4 LT	38	/* IIC hardware controller */
1da177e4	39	#define S3C2410_PA_IIC (0x54000000)
1da177e4	40
1da177e4	41	/* IIS controller */
1da177e4	42	#define S3C2410_PA_IIS (0x55000000)
1da177e4 LT	43
1da177e4 LT	44	/* RTC */
1da177e4 LT	45	#define S3C2410_PA_RTC (0x57000000)
	46	#define S3C24XX_SZ_RTC SZ_1M
	47
	48	/* ADC */
1da177e4	49	#define S3C2410_PA_ADC (0x58000000)
1da177e4 LT	50
1da177e4 LT	51	/* SPI */
1da177e4	52	#define S3C2410_PA_SPI (0x59000000)
1da177e4 LT	53
1da177e4 LT	54	/* SDI */
1da177e4	55	#define S3C2410_PA_SDI (0x5A000000)
1da177e4 LT	56
	57	/* CAMIF */
	58	#define S3C2440_PA_CAMIF (0x4F000000)
	59	#define S3C2440_SZ_CAMIF SZ_1M
	60
fd88edd2 BD	61	/* AC97 */
	62
	63	#define S3C2440_PA_AC97 (0x5B000000)
	64	#define S3C2440_SZ_AC97 SZ_1M
	65
ece97941 BD	66	/* S3C2443 High-speed SD/MMC */
	67	#define S3C2443_PA_HSMMC (0x4A800000)
	68	#define S3C2443_SZ_HSMMC (256)
	69
1da177e4 LT	70	/* physical addresses of all the chip-select areas */
	71
	72	#define S3C2410_CS0 (0x00000000)
	73	#define S3C2410_CS1 (0x08000000)
	74	#define S3C2410_CS2 (0x10000000)
	75	#define S3C2410_CS3 (0x18000000)
	76	#define S3C2410_CS4 (0x20000000)
	77	#define S3C2410_CS5 (0x28000000)
	78	#define S3C2410_CS6 (0x30000000)
	79	#define S3C2410_CS7 (0x38000000)
	80
	81	#define S3C2410_SDRAM_PA (S3C2410_CS6)
	82
0367a8d3 LCVR	83	/* Use a single interface for common resources between S3C24XX cpus */
0367a8d3 LCVR	84
0367a8d3 LCVR	85	#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
	86	#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
	87	#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
	88	#define S3C24XX_PA_DMA S3C2410_PA_DMA
	89	#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
	90	#define S3C24XX_PA_LCD S3C2410_PA_LCD
	91	#define S3C24XX_PA_UART S3C2410_PA_UART
	92	#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
	93	#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
	94	#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
0367a8d3 LCVR	95	#define S3C24XX_PA_IIS S3C2410_PA_IIS
	96	#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
	97	#define S3C24XX_PA_RTC S3C2410_PA_RTC
	98	#define S3C24XX_PA_ADC S3C2410_PA_ADC
	99	#define S3C24XX_PA_SPI S3C2410_PA_SPI
ce46a9c4 BD	100	#define S3C24XX_PA_SDI S3C2410_PA_SDI
ce46a9c4 BD	101	#define S3C24XX_PA_NAND S3C2410_PA_NAND
68d9ab39	102
3e1b776c	103	#define S3C_PA_IIC S3C2410_PA_IIC
b690ace5	104	#define S3C_PA_UART S3C24XX_PA_UART
5b323c7b	105	#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
b690ace5	106
1da177e4	107	#endif /* __ASM_ARCH_MAP_H */