[linux-2.6-block.git] / arch / arm / mach-s3c2410 / dma.c

/* linux/arch/arm/mach-s3c2410/dma.c
 *
 * Copyright (c) 2006 Simtec Electronics
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 DMA selection
 *
 * http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/serial_core.h>

#include <mach/map.h>
#include <mach/dma.h>

#include <plat/cpu.h>
#include <plat/dma-s3c24xx.h>

#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <plat/regs-ac97.h>
#include <plat/regs-dma.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <mach/regs-sdi.h>
#include <plat/regs-iis.h>
#include <plat/regs-spi.h>

static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
	[DMACH_XD0] = {
		.name		= "xdreq0",
		.channels[0]	= S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
	},
	[DMACH_XD1] = {
		.name		= "xdreq1",
		.channels[1]	= S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
	},
	[DMACH_SDI] = {
		.name		= "sdi",
		.channels[0]	= S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_IIS + S3C2410_IISFIFO,
		.hw_addr.from	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	},
	[DMACH_SPI0] = {
		.name		= "spi0",
		.channels[1]	= S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_SPI + S3C2410_SPTDAT,
		.hw_addr.from	= S3C2410_PA_SPI + S3C2410_SPRDAT,
	},
	[DMACH_SPI1] = {
		.name		= "spi1",
		.channels[3]	= S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
		.hw_addr.from	= S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
	},
	[DMACH_UART0] = {
		.name		= "uart0",
		.channels[0]	= S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_UART0 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART0 + S3C2410_URXH,
	},
	[DMACH_UART1] = {
		.name		= "uart1",
		.channels[1]	= S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_UART1 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART1 + S3C2410_URXH,
	},
      	[DMACH_UART2] = {
		.name		= "uart2",
		.channels[3]	= S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_UART2 + S3C2410_UTXH,
		.hw_addr.from	= S3C2410_PA_UART2 + S3C2410_URXH,
	},
	[DMACH_TIMER] = {
		.name		= "timer",
		.channels[0]	= S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
		.channels[3]	= S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
	},
	[DMACH_I2S_IN] = {
		.name		= "i2s-sdi",
		.channels[1]	= S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
		.channels[2]	= S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
		.hw_addr.from	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	},
	[DMACH_I2S_OUT] = {
		.name		= "i2s-sdo",
		.channels[2]	= S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
		.hw_addr.to	= S3C2410_PA_IIS + S3C2410_IISFIFO,
	},
	[DMACH_USB_EP1] = {
		.name		= "usb-ep1",
		.channels[0]	= S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
	},
	[DMACH_USB_EP2] = {
		.name		= "usb-ep2",
		.channels[1]	= S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
	},
	[DMACH_USB_EP3] = {
		.name		= "usb-ep3",
		.channels[2]	= S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
	},
	[DMACH_USB_EP4] = {
		.name		= "usb-ep4",
		.channels[3]	=S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
	},
};

static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
			       struct s3c24xx_dma_map *map)
{
	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
}

static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
	.select		= s3c2410_dma_select,
	.dcon_mask	= 7 << 24,
	.map		= s3c2410_dma_mappings,
	.map_size	= ARRAY_SIZE(s3c2410_dma_mappings),
};

static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
	.channels	= {
		[DMACH_SDI]	= {
			.list	= {
				[0]	= 3 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
				[2]	= 0 | DMA_CH_VALID,
			},
		},
		[DMACH_I2S_IN]	= {
			.list	= {
				[0]	= 1 | DMA_CH_VALID,
				[1]	= 2 | DMA_CH_VALID,
			},
		},
	},
};

static int __init s3c2410_dma_add(struct sys_device *sysdev)
{
	s3c2410_dma_init();
	s3c24xx_dma_order_set(&s3c2410_dma_order);
	return s3c24xx_dma_init_map(&s3c2410_dma_sel);
}

#if defined(CONFIG_CPU_S3C2410)
static struct sysdev_driver s3c2410_dma_driver = {
	.add	= s3c2410_dma_add,
};

static int __init s3c2410_dma_drvinit(void)
{
	return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
}

arch_initcall(s3c2410_dma_drvinit);

static struct sysdev_driver s3c2410a_dma_driver = {
	.add	= s3c2410_dma_add,
};

static int __init s3c2410a_dma_drvinit(void)
{
	return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
}

arch_initcall(s3c2410a_dma_drvinit);
#endif

#if defined(CONFIG_CPU_S3C2442)
/* S3C2442 DMA contains the same selection table as the S3C2410 */
static struct sysdev_driver s3c2442_dma_driver = {
	.add	= s3c2410_dma_add,
};

static int __init s3c2442_dma_drvinit(void)
{
	return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
}

arch_initcall(s3c2442_dma_drvinit);
#endif
Commit	Line	Data
505788cc	1	/* linux/arch/arm/mach-s3c2410/dma.c
1da177e4	2	*
a21765a7	3	* Copyright (c) 2006 Simtec Electronics
1da177e4 LT	4	* Ben Dooks <ben@simtec.co.uk>
1da177e4 LT	5	*
a21765a7	6	* S3C2410 DMA selection
1da177e4	7	*
505788cc	8	* http://armlinux.simtec.co.uk/
1da177e4 LT	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
505788cc	13	*/
1da177e4	14
a21765a7	15	#include <linux/kernel.h>
1da177e4	16	#include <linux/init.h>
1da177e4	17	#include <linux/sysdev.h>
a21765a7	18	#include <linux/serial_core.h>
1da177e4	19
20934cdb	20	#include <mach/map.h>
a09e64fb	21	#include <mach/dma.h>
a21765a7	22
a2b7ba9c	23	#include <plat/cpu.h>
992426bf	24	#include <plat/dma-s3c24xx.h>
a21765a7	25
a2b7ba9c	26	#include <plat/regs-serial.h>
a09e64fb	27	#include <mach/regs-gpio.h>
f74c95c2	28	#include <plat/regs-ac97.h>
44dc9404	29	#include <plat/regs-dma.h>
a09e64fb RK	30	#include <mach/regs-mem.h>
	31	#include <mach/regs-lcd.h>
	32	#include <mach/regs-sdi.h>
8150bc88	33	#include <plat/regs-iis.h>
13622708	34	#include <plat/regs-spi.h>
a21765a7 BD	35
	36	static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
	37	[DMACH_XD0] = {
	38	.name = "xdreq0",
	39	.channels[0] = S3C2410_DCON_CH0_XDREQ0 \| DMA_CH_VALID,
	40	},
	41	[DMACH_XD1] = {
	42	.name = "xdreq1",
	43	.channels[1] = S3C2410_DCON_CH1_XDREQ1 \| DMA_CH_VALID,
	44	},
	45	[DMACH_SDI] = {
	46	.name = "sdi",
	47	.channels[0] = S3C2410_DCON_CH0_SDI \| DMA_CH_VALID,
	48	.channels[2] = S3C2410_DCON_CH2_SDI \| DMA_CH_VALID,
	49	.channels[3] = S3C2410_DCON_CH3_SDI \| DMA_CH_VALID,
	50	.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
	51	.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
	52	},
	53	[DMACH_SPI0] = {
	54	.name = "spi0",
	55	.channels[1] = S3C2410_DCON_CH1_SPI \| DMA_CH_VALID,
	56	.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
	57	.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
	58	},
	59	[DMACH_SPI1] = {
	60	.name = "spi1",
	61	.channels[3] = S3C2410_DCON_CH3_SPI \| DMA_CH_VALID,
	62	.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
	63	.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
	64	},
	65	[DMACH_UART0] = {
	66	.name = "uart0",
	67	.channels[0] = S3C2410_DCON_CH0_UART0 \| DMA_CH_VALID,
	68	.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
	69	.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
	70	},
	71	[DMACH_UART1] = {
	72	.name = "uart1",
	73	.channels[1] = S3C2410_DCON_CH1_UART1 \| DMA_CH_VALID,
	74	.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
	75	.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
	76	},
	77	[DMACH_UART2] = {
	78	.name = "uart2",
	79	.channels[3] = S3C2410_DCON_CH3_UART2 \| DMA_CH_VALID,
	80	.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
	81	.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
	82	},
	83	[DMACH_TIMER] = {
	84	.name = "timer",
	85	.channels[0] = S3C2410_DCON_CH0_TIMER \| DMA_CH_VALID,
	86	.channels[2] = S3C2410_DCON_CH2_TIMER \| DMA_CH_VALID,
	87	.channels[3] = S3C2410_DCON_CH3_TIMER \| DMA_CH_VALID,
	88	},
	89	[DMACH_I2S_IN] = {
	90	.name = "i2s-sdi",
	91	.channels[1] = S3C2410_DCON_CH1_I2SSDI \| DMA_CH_VALID,
	92	.channels[2] = S3C2410_DCON_CH2_I2SSDI \| DMA_CH_VALID,
	93	.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
	94	},
	95	[DMACH_I2S_OUT] = {
	96	.name = "i2s-sdo",
	97	.channels[2] = S3C2410_DCON_CH2_I2SSDO \| DMA_CH_VALID,
	98	.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
99	},
100	[DMACH_USB_EP1] = {
101	.name = "usb-ep1",
102	.channels[0] = S3C2410_DCON_CH0_USBEP1 \| DMA_CH_VALID,
103	},
104	[DMACH_USB_EP2] = {
105	.name = "usb-ep2",
106	.channels[1] = S3C2410_DCON_CH1_USBEP2 \| DMA_CH_VALID,
107	},
108	[DMACH_USB_EP3] = {
109	.name = "usb-ep3",
110	.channels[2] = S3C2410_DCON_CH2_USBEP3 \| DMA_CH_VALID,
111	},
112	[DMACH_USB_EP4] = {
113	.name = "usb-ep4",
114	.channels[3] =S3C2410_DCON_CH3_USBEP4 \| DMA_CH_VALID,
115	},
1da177e4 LT	116	};
1da177e4 LT	117
a21765a7 BD	118	static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
a21765a7 BD	119	struct s3c24xx_dma_map *map)
1da177e4	120	{
a21765a7	121	chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
1da177e4 LT	122	}
1da177e4 LT	123
a21765a7 BD	124	static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
	125	.select = s3c2410_dma_select,
	126	.dcon_mask = 7 << 24,
	127	.map = s3c2410_dma_mappings,
	128	.map_size = ARRAY_SIZE(s3c2410_dma_mappings),
	129	};
1da177e4	130
dad8d6c5 BD	131	static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
	132	.channels = {
	133	[DMACH_SDI] = {
	134	.list = {
	135	[0] = 3 \| DMA_CH_VALID,
	136	[1] = 2 \| DMA_CH_VALID,
	137	[2] = 0 \| DMA_CH_VALID,
	138	},
	139	},
	140	[DMACH_I2S_IN] = {
	141	.list = {
	142	[0] = 1 \| DMA_CH_VALID,
	143	[1] = 2 \| DMA_CH_VALID,
	144	},
	145	},
	146	},
	147	};
	148
f2c10d6c	149	static int __init s3c2410_dma_add(struct sys_device *sysdev)
1da177e4	150	{
48adbcf3	151	s3c2410_dma_init();
dad8d6c5	152	s3c24xx_dma_order_set(&s3c2410_dma_order);
a21765a7	153	return s3c24xx_dma_init_map(&s3c2410_dma_sel);
1da177e4 LT	154	}
1da177e4 LT	155
a21765a7 BD	156	#if defined(CONFIG_CPU_S3C2410)
	157	static struct sysdev_driver s3c2410_dma_driver = {
	158	.add = s3c2410_dma_add,
	159	};
1da177e4	160
48adbcf3	161	static int __init s3c2410_dma_drvinit(void)
f57e1abd	162	{
a21765a7	163	return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
f57e1abd BD	164	}
f57e1abd BD	165
48adbcf3	166	arch_initcall(s3c2410_dma_drvinit);
f0176794 BD	167
	168	static struct sysdev_driver s3c2410a_dma_driver = {
	169	.add = s3c2410_dma_add,
	170	};
	171
	172	static int __init s3c2410a_dma_drvinit(void)
	173	{
	174	return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
	175	}
	176
	177	arch_initcall(s3c2410a_dma_drvinit);
f57e1abd BD	178	#endif
f57e1abd BD	179
a21765a7 BD	180	#if defined(CONFIG_CPU_S3C2442)
	181	/* S3C2442 DMA contains the same selection table as the S3C2410 */
	182	static struct sysdev_driver s3c2442_dma_driver = {
	183	.add = s3c2410_dma_add,
1da177e4 LT	184	};
1da177e4 LT	185
48adbcf3	186	static int __init s3c2442_dma_drvinit(void)
505788cc	187	{
a21765a7	188	return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
505788cc BD	189	}
505788cc BD	190
48adbcf3	191	arch_initcall(s3c2442_dma_drvinit);
a21765a7	192	#endif
505788cc	193