[linux-2.6-block.git] / arch / arm / mach-realview / core.c

/*
 *  linux/arch/arm/mach-realview/core.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
#include <linux/amba/clcd.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/smc911x.h>

#include <asm/clkdev.h>
#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst307.h>

#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/mmc.h>

#include <asm/hardware/gic.h>

#include "core.h"
#include "clock.h"

#define REALVIEW_REFCOUNTER	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)

/* used by entry-macro.S and platsmp.c */
void __iomem *gic_cpu_base_addr;

/*
 * This is the RealView sched_clock implementation.  This has
 * a resolution of 41.7ns, and a maximum value of about 179s.
 */
unsigned long long sched_clock(void)
{
	unsigned long long v;

	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	do_div(v, 3);

	return v;
}


#define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)

static int realview_flash_init(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);

	return 0;
}

static void realview_flash_exit(void)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static void realview_flash_set_vpp(int on)
{
	u32 val;

	val = __raw_readl(REALVIEW_FLASHCTRL);
	if (on)
		val |= REALVIEW_FLASHPROG_FLVPPEN;
	else
		val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	__raw_writel(val, REALVIEW_FLASHCTRL);
}

static struct flash_platform_data realview_flash_data = {
	.map_name		= "cfi_probe",
	.width			= 4,
	.init			= realview_flash_init,
	.exit			= realview_flash_exit,
	.set_vpp		= realview_flash_set_vpp,
};

struct platform_device realview_flash_device = {
	.name			= "armflash",
	.id			= 0,
	.dev			= {
		.platform_data	= &realview_flash_data,
	},
};

int realview_flash_register(struct resource *res, u32 num)
{
	realview_flash_device.resource = res;
	realview_flash_device.num_resources = num;
	return platform_device_register(&realview_flash_device);
}

static struct smc911x_platdata realview_smc911x_platdata = {
	.flags		= SMC911X_USE_32BIT,
	.irq_flags	= IRQF_SHARED,
	.irq_polarity	= 1,
};

static struct platform_device realview_eth_device = {
	.name		= "smc911x",
	.id		= 0,
	.num_resources	= 2,
};

int realview_eth_register(const char *name, struct resource *res)
{
	if (name)
		realview_eth_device.name = name;
	realview_eth_device.resource = res;
	if (strcmp(realview_eth_device.name, "smc911x") == 0)
		realview_eth_device.dev.platform_data = &realview_smc911x_platdata;

	return platform_device_register(&realview_eth_device);
}

static struct resource realview_i2c_resource = {
	.start		= REALVIEW_I2C_BASE,
	.end		= REALVIEW_I2C_BASE + SZ_4K - 1,
	.flags		= IORESOURCE_MEM,
};

struct platform_device realview_i2c_device = {
	.name		= "versatile-i2c",
	.id		= -1,
	.num_resources	= 1,
	.resource	= &realview_i2c_resource,
};

#define REALVIEW_SYSMCI	(__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)

static unsigned int realview_mmc_status(struct device *dev)
{
	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	u32 mask;

	if (adev->res.start == REALVIEW_MMCI0_BASE)
		mask = 1;
	else
		mask = 2;

	return readl(REALVIEW_SYSMCI) & mask;
}

struct mmc_platform_data realview_mmc0_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

struct mmc_platform_data realview_mmc1_plat_data = {
	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
	.status		= realview_mmc_status,
};

/*
 * Clock handling
 */
static const struct icst307_params realview_oscvco_params = {
	.ref		= 24000,
	.vco_max	= 200000,
	.vd_min		= 4 + 8,
	.vd_max		= 511 + 8,
	.rd_min		= 1 + 2,
	.rd_max		= 127 + 2,
};

static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
{
	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
	void __iomem *sys_osc;
	u32 val;

	if (machine_is_realview_pb1176())
		sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	else
		sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;

	val = readl(sys_osc) & ~0x7ffff;
	val |= vco.v | (vco.r << 9) | (vco.s << 16);

	writel(0xa05f, sys_lock);
	writel(val, sys_osc);
	writel(0, sys_lock);
}

static struct clk oscvco_clk = {
	.params	= &realview_oscvco_params,
	.setvco = realview_oscvco_set,
};

/*
 * These are fixed clocks.
 */
static struct clk ref24_clk = {
	.rate	= 24000000,
};

static struct clk_lookup lookups[] = {
	{	/* UART0 */
		.dev_id		= "dev:f1",
		.clk		= &ref24_clk,
	}, {	/* UART1 */
		.dev_id		= "dev:f2",
		.clk		= &ref24_clk,
	}, {	/* UART2 */
		.dev_id		= "dev:f3",
		.clk		= &ref24_clk,
	}, {	/* UART3 */
		.dev_id		= "fpga:09",
		.clk		= &ref24_clk,
	}, {	/* KMI0 */
		.dev_id		= "fpga:06",
		.clk		= &ref24_clk,
	}, {	/* KMI1 */
		.dev_id		= "fpga:07",
		.clk		= &ref24_clk,
	}, {	/* MMC0 */
		.dev_id		= "fpga:05",
		.clk		= &ref24_clk,
	}, {	/* EB:CLCD */
		.dev_id		= "dev:20",
		.clk		= &oscvco_clk,
	}, {	/* PB:CLCD */
		.dev_id		= "issp:20",
		.clk		= &oscvco_clk,
	}
};

static int __init clk_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(lookups); i++)
		clkdev_add(&lookups[i]);
	return 0;
}
arch_initcall(clk_init);

/*
 * CLCD support.
 */
#define SYS_CLCD_NLCDIOON	(1 << 2)
#define SYS_CLCD_VDDPOSSWITCH	(1 << 3)
#define SYS_CLCD_PWR3V5SWITCH	(1 << 4)
#define SYS_CLCD_ID_MASK	(0x1f << 8)
#define SYS_CLCD_ID_SANYO_3_8	(0x00 << 8)
#define SYS_CLCD_ID_UNKNOWN_8_4	(0x01 << 8)
#define SYS_CLCD_ID_EPSON_2_2	(0x02 << 8)
#define SYS_CLCD_ID_SANYO_2_5	(0x07 << 8)
#define SYS_CLCD_ID_VGA		(0x1f << 8)

static struct clcd_panel vga = {
	.mode		= {
		.name		= "VGA",
		.refresh	= 60,
		.xres		= 640,
		.yres		= 480,
		.pixclock	= 39721,
		.left_margin	= 40,
		.right_margin	= 24,
		.upper_margin	= 32,
		.lower_margin	= 11,
		.hsync_len	= 96,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel xvga = {
	.mode		= {
		.name		= "XVGA",
		.refresh	= 60,
		.xres		= 1024,
		.yres		= 768,
		.pixclock	= 15748,
		.left_margin	= 152,
		.right_margin	= 48,
		.upper_margin	= 23,
		.lower_margin	= 3,
		.hsync_len	= 104,
		.vsync_len	= 4,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_3_8_in = {
	.mode		= {
		.name		= "Sanyo QVGA",
		.refresh	= 116,
		.xres		= 320,
		.yres		= 240,
		.pixclock	= 100000,
		.left_margin	= 6,
		.right_margin	= 6,
		.upper_margin	= 5,
		.lower_margin	= 5,
		.hsync_len	= 6,
		.vsync_len	= 6,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel sanyo_2_5_in = {
	.mode		= {
		.name		= "Sanyo QVGA Portrait",
		.refresh	= 116,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 100000,
		.left_margin	= 20,
		.right_margin	= 10,
		.upper_margin	= 2,
		.lower_margin	= 2,
		.hsync_len	= 10,
		.vsync_len	= 2,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_IVS | TIM2_IHS | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

static struct clcd_panel epson_2_2_in = {
	.mode		= {
		.name		= "Epson QCIF",
		.refresh	= 390,
		.xres		= 176,
		.yres		= 220,
		.pixclock	= 62500,
		.left_margin	= 3,
		.right_margin	= 2,
		.upper_margin	= 1,
		.lower_margin	= 0,
		.hsync_len	= 3,
		.vsync_len	= 2,
		.sync		= 0,
		.vmode		= FB_VMODE_NONINTERLACED,
	},
	.width		= -1,
	.height		= -1,
	.tim2		= TIM2_BCD | TIM2_IPC,
	.cntl		= CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
	.bpp		= 16,
};

/*
 * Detect which LCD panel is connected, and return the appropriate
 * clcd_panel structure.  Note: we do not have any information on
 * the required timings for the 8.4in panel, so we presently assume
 * VGA timings.
 */
static struct clcd_panel *realview_clcd_panel(void)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	struct clcd_panel *vga_panel;
	struct clcd_panel *panel;
	u32 val;

	if (machine_is_realview_eb())
		vga_panel = &vga;
	else
		vga_panel = &xvga;

	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	if (val == SYS_CLCD_ID_SANYO_3_8)
		panel = &sanyo_3_8_in;
	else if (val == SYS_CLCD_ID_SANYO_2_5)
		panel = &sanyo_2_5_in;
	else if (val == SYS_CLCD_ID_EPSON_2_2)
		panel = &epson_2_2_in;
	else if (val == SYS_CLCD_ID_VGA)
		panel = vga_panel;
	else {
		printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
			val);
		panel = vga_panel;
	}

	return panel;
}

/*
 * Disable all display connectors on the interface module.
 */
static void realview_clcd_disable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	val = readl(sys_clcd);
	val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

/*
 * Enable the relevant connector on the interface module.
 */
static void realview_clcd_enable(struct clcd_fb *fb)
{
	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	u32 val;

	/*
	 * Enable the PSUs
	 */
	val = readl(sys_clcd);
	val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
	writel(val, sys_clcd);
}

static int realview_clcd_setup(struct clcd_fb *fb)
{
	unsigned long framesize;
	dma_addr_t dma;

	if (machine_is_realview_eb())
		/* VGA, 16bpp */
		framesize = 640 * 480 * 2;
	else
		/* XVGA, 16bpp */
		framesize = 1024 * 768 * 2;

	fb->panel		= realview_clcd_panel();

	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
						    &dma, GFP_KERNEL);
	if (!fb->fb.screen_base) {
		printk(KERN_ERR "CLCD: unable to map framebuffer\n");
		return -ENOMEM;
	}

	fb->fb.fix.smem_start	= dma;
	fb->fb.fix.smem_len	= framesize;

	return 0;
}

static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
{
	return dma_mmap_writecombine(&fb->dev->dev, vma,
				     fb->fb.screen_base,
				     fb->fb.fix.smem_start,
				     fb->fb.fix.smem_len);
}

static void realview_clcd_remove(struct clcd_fb *fb)
{
	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
			      fb->fb.screen_base, fb->fb.fix.smem_start);
}

struct clcd_board clcd_plat_data = {
	.name		= "RealView",
	.check		= clcdfb_check,
	.decode		= clcdfb_decode,
	.disable	= realview_clcd_disable,
	.enable		= realview_clcd_enable,
	.setup		= realview_clcd_setup,
	.mmap		= realview_clcd_mmap,
	.remove		= realview_clcd_remove,
};

#ifdef CONFIG_LEDS
#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)

void realview_leds_event(led_event_t ledevt)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);
	val = readl(VA_LEDS_BASE);

	switch (ledevt) {
	case led_idle_start:
		val = val & ~REALVIEW_SYS_LED0;
		break;

	case led_idle_end:
		val = val | REALVIEW_SYS_LED0;
		break;

	case led_timer:
		val = val ^ REALVIEW_SYS_LED1;
		break;

	case led_halted:
		val = 0;
		break;

	default:
		break;
	}

	writel(val, VA_LEDS_BASE);
	local_irq_restore(flags);
}
#endif	/* CONFIG_LEDS */

/*
 * Where is the timer (VA)?
 */
void __iomem *timer0_va_base;
void __iomem *timer1_va_base;
void __iomem *timer2_va_base;
void __iomem *timer3_va_base;

/*
 * How long is the timer interval?
 */
#define TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_10)
#if TIMER_INTERVAL >= 0x100000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 8)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV256)
#define TICKS2USECS(x)	(256 * (x) / TICKS_PER_uSEC)
#elif TIMER_INTERVAL >= 0x10000
#define TIMER_RELOAD	(TIMER_INTERVAL >> 4)		/* Divide by 16 */
#define TIMER_DIVISOR	(TIMER_CTRL_DIV16)
#define TICKS2USECS(x)	(16 * (x) / TICKS_PER_uSEC)
#else
#define TIMER_RELOAD	(TIMER_INTERVAL)
#define TIMER_DIVISOR	(TIMER_CTRL_DIV1)
#define TICKS2USECS(x)	((x) / TICKS_PER_uSEC)
#endif

static void timer_set_mode(enum clock_event_mode mode,
			   struct clock_event_device *clk)
{
	unsigned long ctrl;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);

		ctrl = TIMER_CTRL_PERIODIC;
		ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE | TIMER_CTRL_ENABLE;
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* period set, and timer enabled in 'next_event' hook */
		ctrl = TIMER_CTRL_ONESHOT;
		ctrl |= TIMER_CTRL_32BIT | TIMER_CTRL_IE;
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		ctrl = 0;
	}

	writel(ctrl, timer0_va_base + TIMER_CTRL);
}

static int timer_set_next_event(unsigned long evt,
				struct clock_event_device *unused)
{
	unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);

	writel(evt, timer0_va_base + TIMER_LOAD);
	writel(ctrl | TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device timer0_clockevent =	 {
	.name		= "timer0",
	.shift		= 32,
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= timer_set_mode,
	.set_next_event	= timer_set_next_event,
	.rating		= 300,
	.cpumask	= CPU_MASK_ALL,
};

static void __init realview_clockevents_init(unsigned int timer_irq)
{
	timer0_clockevent.irq = timer_irq;
	timer0_clockevent.mult =
		div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
	timer0_clockevent.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &timer0_clockevent);
	timer0_clockevent.min_delta_ns =
		clockevent_delta2ns(0xf, &timer0_clockevent);

	clockevents_register_device(&timer0_clockevent);
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &timer0_clockevent;

	/* clear the interrupt */
	writel(1, timer0_va_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction realview_timer_irq = {
	.name		= "RealView Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= realview_timer_interrupt,
};

static cycle_t realview_get_cycles(void)
{
	return ~readl(timer3_va_base + TIMER_VALUE);
}

static struct clocksource clocksource_realview = {
	.name	= "timer3",
	.rating	= 200,
	.read	= realview_get_cycles,
	.mask	= CLOCKSOURCE_MASK(32),
	.shift	= 20,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static void __init realview_clocksource_init(void)
{
	/* setup timer 0 as free-running clocksource */
	writel(0, timer3_va_base + TIMER_CTRL);
	writel(0xffffffff, timer3_va_base + TIMER_LOAD);
	writel(0xffffffff, timer3_va_base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		timer3_va_base + TIMER_CTRL);

	clocksource_realview.mult =
		clocksource_khz2mult(1000, clocksource_realview.shift);
	clocksource_register(&clocksource_realview);
}

/*
 * Set up the clock source and clock events devices
 */
void __init realview_timer_init(unsigned int timer_irq)
{
	u32 val;

#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	/*
	 * The dummy clock device has to be registered before the main device
	 * so that the latter will broadcast the clock events
	 */
	local_timer_setup();
#endif

	/* 
	 * set clock frequency: 
	 *	REALVIEW_REFCLK is 32KHz
	 *	REALVIEW_TIMCLK is 1MHz
	 */
	val = readl(__io_address(REALVIEW_SCTL_BASE));
	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) | 
	       (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
	       (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
	       __io_address(REALVIEW_SCTL_BASE));

	/*
	 * Initialise to a known state (all timers off)
	 */
	writel(0, timer0_va_base + TIMER_CTRL);
	writel(0, timer1_va_base + TIMER_CTRL);
	writel(0, timer2_va_base + TIMER_CTRL);
	writel(0, timer3_va_base + TIMER_CTRL);

	/* 
	 * Make irqs happen for the system timer
	 */
	setup_irq(timer_irq, &realview_timer_irq);

	realview_clocksource_init();
	realview_clockevents_init(timer_irq);
}
Commit	Line	Data
8ad68bbf CM	1	/*
	2	* linux/arch/arm/mach-realview/core.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
8ad68bbf	21	#include <linux/init.h>
1be7228d	22	#include <linux/platform_device.h>
8ad68bbf CM	23	#include <linux/dma-mapping.h>
	24	#include <linux/sysdev.h>
	25	#include <linux/interrupt.h>
a62c80e5 RK	26	#include <linux/amba/bus.h>
a62c80e5 RK	27	#include <linux/amba/clcd.h>
85802afe	28	#include <linux/clocksource.h>
ae30ceac	29	#include <linux/clockchips.h>
fced80c7	30	#include <linux/io.h>
0a5b2f6b	31	#include <linux/smc911x.h>
8ad68bbf	32
cf30fb4a	33	#include <asm/clkdev.h>
8ad68bbf	34	#include <asm/system.h>
a09e64fb	35	#include <mach/hardware.h>
8ad68bbf CM	36	#include <asm/irq.h>
8ad68bbf CM	37	#include <asm/leds.h>
68c3d935	38	#include <asm/mach-types.h>
8ad68bbf CM	39	#include <asm/hardware/arm_timer.h>
	40	#include <asm/hardware/icst307.h>
	41
	42	#include <asm/mach/arch.h>
	43	#include <asm/mach/flash.h>
	44	#include <asm/mach/irq.h>
8ad68bbf CM	45	#include <asm/mach/map.h>
	46	#include <asm/mach/mmc.h>
	47
	48	#include <asm/hardware/gic.h>
	49
	50	#include "core.h"
	51	#include "clock.h"
	52
	53	#define REALVIEW_REFCOUNTER (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
	54
1bbdf637	55	/* used by entry-macro.S and platsmp.c */
c4057f52 CM	56	void __iomem *gic_cpu_base_addr;
c4057f52 CM	57
8ad68bbf CM	58	/*
	59	* This is the RealView sched_clock implementation. This has
	60	* a resolution of 41.7ns, and a maximum value of about 179s.
	61	*/
	62	unsigned long long sched_clock(void)
	63	{
	64	unsigned long long v;
	65
	66	v = (unsigned long long)readl(REALVIEW_REFCOUNTER) * 125;
	67	do_div(v, 3);
	68
	69	return v;
	70	}
	71
	72
	73	#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
	74
	75	static int realview_flash_init(void)
	76	{
	77	u32 val;
	78
	79	val = __raw_readl(REALVIEW_FLASHCTRL);
	80	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	81	__raw_writel(val, REALVIEW_FLASHCTRL);
	82
	83	return 0;
	84	}
	85
	86	static void realview_flash_exit(void)
	87	{
	88	u32 val;
	89
	90	val = __raw_readl(REALVIEW_FLASHCTRL);
	91	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	92	__raw_writel(val, REALVIEW_FLASHCTRL);
	93	}
	94
	95	static void realview_flash_set_vpp(int on)
	96	{
	97	u32 val;
	98
	99	val = __raw_readl(REALVIEW_FLASHCTRL);
	100	if (on)
	101	val \|= REALVIEW_FLASHPROG_FLVPPEN;
	102	else
	103	val &= ~REALVIEW_FLASHPROG_FLVPPEN;
	104	__raw_writel(val, REALVIEW_FLASHCTRL);
	105	}
	106
	107	static struct flash_platform_data realview_flash_data = {
	108	.map_name = "cfi_probe",
	109	.width = 4,
	110	.init = realview_flash_init,
	111	.exit = realview_flash_exit,
	112	.set_vpp = realview_flash_set_vpp,
	113	};
	114
8ad68bbf CM	115	struct platform_device realview_flash_device = {
	116	.name = "armflash",
	117	.id = 0,
	118	.dev = {
	119	.platform_data = &realview_flash_data,
	120	},
8ad68bbf CM	121	};
8ad68bbf CM	122
a44ddfd5 CM	123	int realview_flash_register(struct resource *res, u32 num)
	124	{
	125	realview_flash_device.resource = res;
	126	realview_flash_device.num_resources = num;
	127	return platform_device_register(&realview_flash_device);
	128	}
	129
0a5b2f6b CM	130	static struct smc911x_platdata realview_smc911x_platdata = {
	131	.flags = SMC911X_USE_32BIT,
	132	.irq_flags = IRQF_SHARED,
	133	.irq_polarity = 1,
	134	};
	135
0a381330 CM	136	static struct platform_device realview_eth_device = {
	137	.name = "smc911x",
	138	.id = 0,
	139	.num_resources = 2,
	140	};
	141
	142	int realview_eth_register(const char name, struct resource res)
	143	{
	144	if (name)
	145	realview_eth_device.name = name;
	146	realview_eth_device.resource = res;
0a5b2f6b CM	147	if (strcmp(realview_eth_device.name, "smc911x") == 0)
0a5b2f6b CM	148	realview_eth_device.dev.platform_data = &realview_smc911x_platdata;
0a381330 CM	149
	150	return platform_device_register(&realview_eth_device);
	151	}
	152
6b65cd74 RK	153	static struct resource realview_i2c_resource = {
	154	.start = REALVIEW_I2C_BASE,
	155	.end = REALVIEW_I2C_BASE + SZ_4K - 1,
	156	.flags = IORESOURCE_MEM,
	157	};
	158
	159	struct platform_device realview_i2c_device = {
	160	.name = "versatile-i2c",
	161	.id = -1,
	162	.num_resources = 1,
	163	.resource = &realview_i2c_resource,
	164	};
	165
8ad68bbf CM	166	#define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
	167
	168	static unsigned int realview_mmc_status(struct device *dev)
	169	{
	170	struct amba_device *adev = container_of(dev, struct amba_device, dev);
	171	u32 mask;
	172
	173	if (adev->res.start == REALVIEW_MMCI0_BASE)
	174	mask = 1;
	175	else
	176	mask = 2;
	177
	178	return readl(REALVIEW_SYSMCI) & mask;
	179	}
	180
	181	struct mmc_platform_data realview_mmc0_plat_data = {
	182	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	183	.status = realview_mmc_status,
	184	};
	185
	186	struct mmc_platform_data realview_mmc1_plat_data = {
	187	.ocr_mask = MMC_VDD_32_33\|MMC_VDD_33_34,
	188	.status = realview_mmc_status,
	189	};
	190
	191	/*
	192	* Clock handling
	193	*/
	194	static const struct icst307_params realview_oscvco_params = {
	195	.ref = 24000,
	196	.vco_max = 200000,
	197	.vd_min = 4 + 8,
	198	.vd_max = 511 + 8,
	199	.rd_min = 1 + 2,
	200	.rd_max = 127 + 2,
	201	};
	202
	203	static void realview_oscvco_set(struct clk *clk, struct icst307_vco vco)
	204	{
	205	void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
68c3d935	206	void __iomem *sys_osc;
8ad68bbf CM	207	u32 val;
8ad68bbf CM	208
68c3d935 CT	209	if (machine_is_realview_pb1176())
	210	sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
	211	else
	212	sys_osc = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
	213
8ad68bbf CM	214	val = readl(sys_osc) & ~0x7ffff;
	215	val \|= vco.v \| (vco.r << 9) \| (vco.s << 16);
	216
	217	writel(0xa05f, sys_lock);
	218	writel(val, sys_osc);
	219	writel(0, sys_lock);
	220	}
	221
cf30fb4a	222	static struct clk oscvco_clk = {
8ad68bbf CM	223	.params = &realview_oscvco_params,
	224	.setvco = realview_oscvco_set,
	225	};
	226
cf30fb4a RK	227	/*
	228	* These are fixed clocks.
	229	*/
	230	static struct clk ref24_clk = {
	231	.rate = 24000000,
	232	};
	233
	234	static struct clk_lookup lookups[] = {
	235	{ /* UART0 */
	236	.dev_id = "dev:f1",
	237	.clk = &ref24_clk,
	238	}, { /* UART1 */
	239	.dev_id = "dev:f2",
	240	.clk = &ref24_clk,
	241	}, { /* UART2 */
	242	.dev_id = "dev:f3",
	243	.clk = &ref24_clk,
	244	}, { /* UART3 */
	245	.dev_id = "fpga:09",
	246	.clk = &ref24_clk,
	247	}, { /* KMI0 */
	248	.dev_id = "fpga:06",
	249	.clk = &ref24_clk,
	250	}, { /* KMI1 */
	251	.dev_id = "fpga:07",
	252	.clk = &ref24_clk,
	253	}, { /* MMC0 */
	254	.dev_id = "fpga:05",
	255	.clk = &ref24_clk,
	256	}, { /* EB:CLCD */
	257	.dev_id = "dev:20",
	258	.clk = &oscvco_clk,
	259	}, { /* PB:CLCD */
	260	.dev_id = "issp:20",
	261	.clk = &oscvco_clk,
	262	}
	263	};
	264
	265	static int __init clk_init(void)
	266	{
	267	int i;
	268
	269	for (i = 0; i < ARRAY_SIZE(lookups); i++)
	270	clkdev_add(&lookups[i]);
	271	return 0;
	272	}
	273	arch_initcall(clk_init);
	274
8ad68bbf CM	275	/*
	276	* CLCD support.
	277	*/
8ad68bbf CM	278	#define SYS_CLCD_NLCDIOON (1 << 2)
	279	#define SYS_CLCD_VDDPOSSWITCH (1 << 3)
	280	#define SYS_CLCD_PWR3V5SWITCH (1 << 4)
	281	#define SYS_CLCD_ID_MASK (0x1f << 8)
	282	#define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
	283	#define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
	284	#define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
	285	#define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
	286	#define SYS_CLCD_ID_VGA (0x1f << 8)
	287
	288	static struct clcd_panel vga = {
	289	.mode = {
	290	.name = "VGA",
	291	.refresh = 60,
	292	.xres = 640,
	293	.yres = 480,
	294	.pixclock = 39721,
	295	.left_margin = 40,
	296	.right_margin = 24,
	297	.upper_margin = 32,
	298	.lower_margin = 11,
	299	.hsync_len = 96,
	300	.vsync_len = 2,
	301	.sync = 0,
	302	.vmode = FB_VMODE_NONINTERLACED,
	303	},
	304	.width = -1,
	305	.height = -1,
	306	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	307	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	308	.bpp = 16,
	309	};
	310
c34a1025 CT	311	static struct clcd_panel xvga = {
	312	.mode = {
	313	.name = "XVGA",
	314	.refresh = 60,
	315	.xres = 1024,
	316	.yres = 768,
	317	.pixclock = 15748,
	318	.left_margin = 152,
	319	.right_margin = 48,
	320	.upper_margin = 23,
	321	.lower_margin = 3,
	322	.hsync_len = 104,
	323	.vsync_len = 4,
	324	.sync = 0,
	325	.vmode = FB_VMODE_NONINTERLACED,
	326	},
	327	.width = -1,
	328	.height = -1,
	329	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	330	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	331	.bpp = 16,
	332	};
	333
	334	static struct clcd_panel sanyo_3_8_in = {
	335	.mode = {
	336	.name = "Sanyo QVGA",
	337	.refresh = 116,
	338	.xres = 320,
	339	.yres = 240,
	340	.pixclock = 100000,
	341	.left_margin = 6,
	342	.right_margin = 6,
	343	.upper_margin = 5,
	344	.lower_margin = 5,
	345	.hsync_len = 6,
	346	.vsync_len = 6,
	347	.sync = 0,
	348	.vmode = FB_VMODE_NONINTERLACED,
	349	},
	350	.width = -1,
	351	.height = -1,
	352	.tim2 = TIM2_BCD,
4eccca20	353	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	354	.bpp = 16,
	355	};
	356
	357	static struct clcd_panel sanyo_2_5_in = {
	358	.mode = {
	359	.name = "Sanyo QVGA Portrait",
	360	.refresh = 116,
	361	.xres = 240,
	362	.yres = 320,
	363	.pixclock = 100000,
	364	.left_margin = 20,
	365	.right_margin = 10,
	366	.upper_margin = 2,
	367	.lower_margin = 2,
	368	.hsync_len = 10,
	369	.vsync_len = 2,
	370	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_VERT_HIGH_ACT,
	371	.vmode = FB_VMODE_NONINTERLACED,
	372	},
	373	.width = -1,
	374	.height = -1,
	375	.tim2 = TIM2_IVS \| TIM2_IHS \| TIM2_IPC,
4eccca20	376	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	377	.bpp = 16,
	378	};
	379
	380	static struct clcd_panel epson_2_2_in = {
	381	.mode = {
	382	.name = "Epson QCIF",
	383	.refresh = 390,
	384	.xres = 176,
	385	.yres = 220,
	386	.pixclock = 62500,
	387	.left_margin = 3,
	388	.right_margin = 2,
	389	.upper_margin = 1,
	390	.lower_margin = 0,
	391	.hsync_len = 3,
	392	.vsync_len = 2,
	393	.sync = 0,
	394	.vmode = FB_VMODE_NONINTERLACED,
	395	},
	396	.width = -1,
	397	.height = -1,
	398	.tim2 = TIM2_BCD \| TIM2_IPC,
4eccca20	399	.cntl = CNTL_LCDTFT \| CNTL_BGR \| CNTL_LCDVCOMP(1),
8ad68bbf CM	400	.bpp = 16,
	401	};
	402
	403	/*
	404	* Detect which LCD panel is connected, and return the appropriate
	405	* clcd_panel structure. Note: we do not have any information on
	406	* the required timings for the 8.4in panel, so we presently assume
	407	* VGA timings.
	408	*/
	409	static struct clcd_panel *realview_clcd_panel(void)
	410	{
	411	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
c34a1025 CT	412	struct clcd_panel *vga_panel;
c34a1025 CT	413	struct clcd_panel *panel;
8ad68bbf CM	414	u32 val;
8ad68bbf CM	415
c34a1025 CT	416	if (machine_is_realview_eb())
	417	vga_panel = &vga;
	418	else
	419	vga_panel = &xvga;
	420
8ad68bbf CM	421	val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
	422	if (val == SYS_CLCD_ID_SANYO_3_8)
	423	panel = &sanyo_3_8_in;
	424	else if (val == SYS_CLCD_ID_SANYO_2_5)
	425	panel = &sanyo_2_5_in;
	426	else if (val == SYS_CLCD_ID_EPSON_2_2)
	427	panel = &epson_2_2_in;
	428	else if (val == SYS_CLCD_ID_VGA)
c34a1025	429	panel = vga_panel;
8ad68bbf CM	430	else {
	431	printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
	432	val);
c34a1025	433	panel = vga_panel;
8ad68bbf CM	434	}
	435
	436	return panel;
	437	}
	438
	439	/*
	440	* Disable all display connectors on the interface module.
	441	*/
	442	static void realview_clcd_disable(struct clcd_fb *fb)
	443	{
	444	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	445	u32 val;
	446
	447	val = readl(sys_clcd);
	448	val &= ~SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	449	writel(val, sys_clcd);
	450	}
	451
	452	/*
	453	* Enable the relevant connector on the interface module.
	454	*/
	455	static void realview_clcd_enable(struct clcd_fb *fb)
	456	{
	457	void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
	458	u32 val;
	459
8ad68bbf	460	/*
9e7714d0	461	* Enable the PSUs
8ad68bbf	462	*/
9e7714d0	463	val = readl(sys_clcd);
8ad68bbf CM	464	val \|= SYS_CLCD_NLCDIOON \| SYS_CLCD_PWR3V5SWITCH;
	465	writel(val, sys_clcd);
	466	}
	467
8ad68bbf CM	468	static int realview_clcd_setup(struct clcd_fb *fb)
8ad68bbf CM	469	{
c34a1025	470	unsigned long framesize;
8ad68bbf CM	471	dma_addr_t dma;
8ad68bbf CM	472
c34a1025 CT	473	if (machine_is_realview_eb())
	474	/* VGA, 16bpp */
	475	framesize = 640 * 480 * 2;
	476	else
	477	/* XVGA, 16bpp */
	478	framesize = 1024 * 768 * 2;
	479
8ad68bbf CM	480	fb->panel = realview_clcd_panel();
	481
	482	fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
	483	&dma, GFP_KERNEL);
	484	if (!fb->fb.screen_base) {
	485	printk(KERN_ERR "CLCD: unable to map framebuffer\n");
	486	return -ENOMEM;
	487	}
	488
	489	fb->fb.fix.smem_start = dma;
	490	fb->fb.fix.smem_len = framesize;
	491
	492	return 0;
	493	}
	494
	495	static int realview_clcd_mmap(struct clcd_fb fb, struct vm_area_struct vma)
	496	{
	497	return dma_mmap_writecombine(&fb->dev->dev, vma,
	498	fb->fb.screen_base,
	499	fb->fb.fix.smem_start,
	500	fb->fb.fix.smem_len);
	501	}
	502
	503	static void realview_clcd_remove(struct clcd_fb *fb)
	504	{
	505	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
	506	fb->fb.screen_base, fb->fb.fix.smem_start);
	507	}
	508
	509	struct clcd_board clcd_plat_data = {
	510	.name = "RealView",
	511	.check = clcdfb_check,
	512	.decode = clcdfb_decode,
	513	.disable = realview_clcd_disable,
	514	.enable = realview_clcd_enable,
	515	.setup = realview_clcd_setup,
	516	.mmap = realview_clcd_mmap,
	517	.remove = realview_clcd_remove,
	518	};
	519
	520	#ifdef CONFIG_LEDS
	521	#define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
	522
	523	void realview_leds_event(led_event_t ledevt)
	524	{
	525	unsigned long flags;
	526	u32 val;
	527
	528	local_irq_save(flags);
	529	val = readl(VA_LEDS_BASE);
	530
	531	switch (ledevt) {
	532	case led_idle_start:
	533	val = val & ~REALVIEW_SYS_LED0;
	534	break;
	535
	536	case led_idle_end:
	537	val = val \| REALVIEW_SYS_LED0;
	538	break;
	539
	540	case led_timer:
	541	val = val ^ REALVIEW_SYS_LED1;
	542	break;
	543
544	case led_halted:
545	val = 0;
546	break;
547
548	default:
549	break;
550	}
551
552	writel(val, VA_LEDS_BASE);
553	local_irq_restore(flags);
554	}
555	#endif /* CONFIG_LEDS */
556
557	/*
558	* Where is the timer (VA)?
559	*/
80192735 CM	560	void __iomem *timer0_va_base;
	561	void __iomem *timer1_va_base;
	562	void __iomem *timer2_va_base;
	563	void __iomem *timer3_va_base;
8ad68bbf CM	564
	565	/*
	566	* How long is the timer interval?
	567	*/
	568	#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
	569	#if TIMER_INTERVAL >= 0x100000
	570	#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
	571	#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
	572	#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
	573	#elif TIMER_INTERVAL >= 0x10000
	574	#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
	575	#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
	576	#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
	577	#else
	578	#define TIMER_RELOAD (TIMER_INTERVAL)
	579	#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
	580	#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
	581	#endif
	582
ae30ceac CM	583	static void timer_set_mode(enum clock_event_mode mode,
	584	struct clock_event_device *clk)
	585	{
	586	unsigned long ctrl;
	587
	588	switch(mode) {
	589	case CLOCK_EVT_MODE_PERIODIC:
80192735	590	writel(TIMER_RELOAD, timer0_va_base + TIMER_LOAD);
ae30ceac CM	591
	592	ctrl = TIMER_CTRL_PERIODIC;
	593	ctrl \|= TIMER_CTRL_32BIT \| TIMER_CTRL_IE \| TIMER_CTRL_ENABLE;
	594	break;
	595	case CLOCK_EVT_MODE_ONESHOT:
	596	/* period set, and timer enabled in 'next_event' hook */
	597	ctrl = TIMER_CTRL_ONESHOT;
	598	ctrl \|= TIMER_CTRL_32BIT \| TIMER_CTRL_IE;
	599	break;
	600	case CLOCK_EVT_MODE_UNUSED:
	601	case CLOCK_EVT_MODE_SHUTDOWN:
	602	default:
	603	ctrl = 0;
	604	}
	605
80192735	606	writel(ctrl, timer0_va_base + TIMER_CTRL);
ae30ceac CM	607	}
	608
	609	static int timer_set_next_event(unsigned long evt,
	610	struct clock_event_device *unused)
	611	{
80192735	612	unsigned long ctrl = readl(timer0_va_base + TIMER_CTRL);
ae30ceac	613
80192735 CM	614	writel(evt, timer0_va_base + TIMER_LOAD);
80192735 CM	615	writel(ctrl \| TIMER_CTRL_ENABLE, timer0_va_base + TIMER_CTRL);
ae30ceac CM	616
	617	return 0;
	618	}
	619
	620	static struct clock_event_device timer0_clockevent = {
	621	.name = "timer0",
	622	.shift = 32,
	623	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	624	.set_mode = timer_set_mode,
	625	.set_next_event = timer_set_next_event,
	626	.rating = 300,
ae30ceac CM	627	.cpumask = CPU_MASK_ALL,
	628	};
	629
8cc4c548	630	static void __init realview_clockevents_init(unsigned int timer_irq)
ae30ceac	631	{
8cc4c548	632	timer0_clockevent.irq = timer_irq;
ae30ceac CM	633	timer0_clockevent.mult =
	634	div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
	635	timer0_clockevent.max_delta_ns =
	636	clockevent_delta2ns(0xffffffff, &timer0_clockevent);
	637	timer0_clockevent.min_delta_ns =
	638	clockevent_delta2ns(0xf, &timer0_clockevent);
	639
	640	clockevents_register_device(&timer0_clockevent);
	641	}
	642
8ad68bbf CM	643	/*
	644	* IRQ handler for the timer
	645	*/
0cd61b68	646	static irqreturn_t realview_timer_interrupt(int irq, void *dev_id)
8ad68bbf	647	{
ae30ceac	648	struct clock_event_device *evt = &timer0_clockevent;
8ad68bbf	649
ae30ceac	650	/* clear the interrupt */
80192735	651	writel(1, timer0_va_base + TIMER_INTCLR);
8ad68bbf	652
ae30ceac	653	evt->event_handler(evt);
dbebb4cb	654
8ad68bbf CM	655	return IRQ_HANDLED;
	656	}
	657
	658	static struct irqaction realview_timer_irq = {
	659	.name = "RealView Timer Tick",
b30fabad	660	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
8ad68bbf CM	661	.handler = realview_timer_interrupt,
	662	};
	663
85802afe CM	664	static cycle_t realview_get_cycles(void)
85802afe CM	665	{
80192735	666	return ~readl(timer3_va_base + TIMER_VALUE);
85802afe CM	667	}
	668
	669	static struct clocksource clocksource_realview = {
	670	.name = "timer3",
	671	.rating = 200,
	672	.read = realview_get_cycles,
	673	.mask = CLOCKSOURCE_MASK(32),
	674	.shift = 20,
	675	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	676	};
	677
	678	static void __init realview_clocksource_init(void)
	679	{
	680	/* setup timer 0 as free-running clocksource */
80192735 CM	681	writel(0, timer3_va_base + TIMER_CTRL);
	682	writel(0xffffffff, timer3_va_base + TIMER_LOAD);
	683	writel(0xffffffff, timer3_va_base + TIMER_VALUE);
85802afe	684	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
80192735	685	timer3_va_base + TIMER_CTRL);
85802afe CM	686
	687	clocksource_realview.mult =
	688	clocksource_khz2mult(1000, clocksource_realview.shift);
	689	clocksource_register(&clocksource_realview);
	690	}
	691
8ad68bbf	692	/*
a8655e83	693	* Set up the clock source and clock events devices
8ad68bbf	694	*/
8cc4c548	695	void __init realview_timer_init(unsigned int timer_irq)
8ad68bbf CM	696	{
	697	u32 val;
	698
a8655e83 CM	699	#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
	700	/*
	701	* The dummy clock device has to be registered before the main device
	702	* so that the latter will broadcast the clock events
	703	*/
ebac6546	704	local_timer_setup();
a8655e83 CM	705	#endif
a8655e83 CM	706
8ad68bbf CM	707	/*
	708	* set clock frequency:
	709	* REALVIEW_REFCLK is 32KHz
	710	* REALVIEW_TIMCLK is 1MHz
	711	*/
	712	val = readl(__io_address(REALVIEW_SCTL_BASE));
	713	writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) \|
	714	(REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) \|
	715	(REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) \|
	716	(REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) \| val,
	717	__io_address(REALVIEW_SCTL_BASE));
	718
	719	/*
	720	* Initialise to a known state (all timers off)
	721	*/
80192735 CM	722	writel(0, timer0_va_base + TIMER_CTRL);
	723	writel(0, timer1_va_base + TIMER_CTRL);
	724	writel(0, timer2_va_base + TIMER_CTRL);
	725	writel(0, timer3_va_base + TIMER_CTRL);
8ad68bbf	726
8ad68bbf CM	727	/*
	728	* Make irqs happen for the system timer
	729	*/
8cc4c548	730	setup_irq(timer_irq, &realview_timer_irq);
85802afe CM	731
85802afe CM	732	realview_clocksource_init();
8cc4c548	733	realview_clockevents_init(timer_irq);
8ad68bbf	734	}