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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / arch / arm / mach-pxa / devices.c
CommitLineData
8f58de7c 1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/platform_device.h>
5#include <linux/dma-mapping.h>
8348c259 6#include <linux/spi/pxa2xx_spi.h>
b459396e 7#include <linux/i2c/pxa-i2c.h>
8f58de7c 8
a09e64fb 9#include <mach/udc.h>
293b2da1
AB		 10#include <linux/platform_data/usb-pxa3xx-ulpi.h>
11#include <linux/platform_data/video-pxafb.h>
12#include <linux/platform_data/mmc-pxamci.h>
13#include <linux/platform_data/irda-pxaficp.h>
4e611091 14#include <mach/irqs.h>
293b2da1
AB		 15#include <linux/platform_data/usb-ohci-pxa27x.h>
16#include <linux/platform_data/keypad-pxa27x.h>
17#include <linux/platform_data/camera-pxa.h>
a09e64fb 18#include <mach/audio.h>
75e874c6 19#include <mach/hardware.h>
4be0856f 20#include <linux/platform_data/mmp_dma.h>
293b2da1 21#include <linux/platform_data/mtd-nand-pxa3xx.h>
8f58de7c 22
23#include "devices.h"
bc3a5959 24#include "generic.h"
8f58de7c 25
26void __init pxa_register_device(struct platform_device *dev, void *data)
27{
28 int ret;
29
30 dev->dev.platform_data = data;
31
32 ret = platform_device_register(dev);
33 if (ret)
34 dev_err(&dev->dev, "unable to register device: %d\n", ret);
35}
36
09a5358d
EM		 37static struct resource pxa_resource_pmu = {
38 .start = IRQ_PMU,
39 .end = IRQ_PMU,
40 .flags = IORESOURCE_IRQ,
41};
42
43struct platform_device pxa_device_pmu = {
f9eff219 44 .name = "xscale-pmu",
df3d17e0 45 .id = -1,
09a5358d
EM		 46 .resource = &pxa_resource_pmu,
47 .num_resources = 1,
48};
49
8f58de7c 50static struct resource pxamci_resources[] = {
51 [0] = {
52 .start = 0x41100000,
53 .end = 0x41100fff,
54 .flags = IORESOURCE_MEM,
55 },
56 [1] = {
57 .start = IRQ_MMC,
58 .end = IRQ_MMC,
59 .flags = IORESOURCE_IRQ,
60 },
61 [2] = {
62 .start = 21,
63 .end = 21,
64 .flags = IORESOURCE_DMA,
65 },
66 [3] = {
67 .start = 22,
68 .end = 22,
69 .flags = IORESOURCE_DMA,
70 },
71};
72
73static u64 pxamci_dmamask = 0xffffffffUL;
74
75struct platform_device pxa_device_mci = {
76 .name = "pxa2xx-mci",
fafc9d3f 77 .id = 0,
8f58de7c 78 .dev = {
79 .dma_mask = &pxamci_dmamask,
80 .coherent_dma_mask = 0xffffffff,
81 },
82 .num_resources = ARRAY_SIZE(pxamci_resources),
83 .resource = pxamci_resources,
84};
85
86void __init pxa_set_mci_info(struct pxamci_platform_data *info)
87{
88 pxa_register_device(&pxa_device_mci, info);
89}
90
91
1257629b
PZ		 92static struct pxa2xx_udc_mach_info pxa_udc_info = {
93 .gpio_pullup = -1,
1257629b 94};
8f58de7c 95
96void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
97{
98 memcpy(&pxa_udc_info, info, sizeof *info);
99}
100
101static struct resource pxa2xx_udc_resources[] = {
102 [0] = {
103 .start = 0x40600000,
104 .end = 0x4060ffff,
105 .flags = IORESOURCE_MEM,
106 },
107 [1] = {
108 .start = IRQ_USB,
109 .end = IRQ_USB,
110 .flags = IORESOURCE_IRQ,
111 },
112};
113
114static u64 udc_dma_mask = ~(u32)0;
115
7a857620
PZ		 116struct platform_device pxa25x_device_udc = {
117 .name = "pxa25x-udc",
118 .id = -1,
119 .resource = pxa2xx_udc_resources,
120 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
121 .dev = {
122 .platform_data = &pxa_udc_info,
123 .dma_mask = &udc_dma_mask,
124 }
125};
126
127struct platform_device pxa27x_device_udc = {
128 .name = "pxa27x-udc",
8f58de7c 129 .id = -1,
130 .resource = pxa2xx_udc_resources,
131 .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
132 .dev = {
133 .platform_data = &pxa_udc_info,
134 .dma_mask = &udc_dma_mask,
135 }
136};
137
69f22be7
IG		 138#ifdef CONFIG_PXA3xx
139static struct resource pxa3xx_u2d_resources[] = {
140 [0] = {
141 .start = 0x54100000,
142 .end = 0x54100fff,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = IRQ_USB2,
147 .end = IRQ_USB2,
148 .flags = IORESOURCE_IRQ,
149 },
150};
151
152struct platform_device pxa3xx_device_u2d = {
153 .name = "pxa3xx-u2d",
154 .id = -1,
155 .resource = pxa3xx_u2d_resources,
156 .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
157};
158
159void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
160{
161 pxa_register_device(&pxa3xx_device_u2d, info);
162}
163#endif /* CONFIG_PXA3xx */
164
8f58de7c 165static struct resource pxafb_resources[] = {
166 [0] = {
167 .start = 0x44000000,
168 .end = 0x4400ffff,
169 .flags = IORESOURCE_MEM,
170 },
171 [1] = {
172 .start = IRQ_LCD,
173 .end = IRQ_LCD,
174 .flags = IORESOURCE_IRQ,
175 },
176};
177
178static u64 fb_dma_mask = ~(u64)0;
179
180struct platform_device pxa_device_fb = {
181 .name = "pxa2xx-fb",
182 .id = -1,
183 .dev = {
184 .dma_mask = &fb_dma_mask,
185 .coherent_dma_mask = 0xffffffff,
186 },
187 .num_resources = ARRAY_SIZE(pxafb_resources),
188 .resource = pxafb_resources,
189};
190
4321e1a1 191void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
8f58de7c 192{
4321e1a1 193 pxa_device_fb.dev.parent = parent;
8f58de7c 194 pxa_register_device(&pxa_device_fb, info);
195}
196
8f58de7c 197static struct resource pxa_resource_ffuart[] = {
198 {
02f65262
EM		 199 .start = 0x40100000,
200 .end = 0x40100023,
8f58de7c 201 .flags = IORESOURCE_MEM,
202 }, {
203 .start = IRQ_FFUART,
204 .end = IRQ_FFUART,
205 .flags = IORESOURCE_IRQ,
206 }
207};
208
cc155c6f 209struct platform_device pxa_device_ffuart = {
8f58de7c 210 .name = "pxa2xx-uart",
211 .id = 0,
212 .resource = pxa_resource_ffuart,
213 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
214};
215
cc155c6f
RK		 216void __init pxa_set_ffuart_info(void *info)
217{
218 pxa_register_device(&pxa_device_ffuart, info);
219}
220
8f58de7c 221static struct resource pxa_resource_btuart[] = {
222 {
02f65262
EM		 223 .start = 0x40200000,
224 .end = 0x40200023,
8f58de7c 225 .flags = IORESOURCE_MEM,
226 }, {
227 .start = IRQ_BTUART,
228 .end = IRQ_BTUART,
229 .flags = IORESOURCE_IRQ,
230 }
231};
232
233struct platform_device pxa_device_btuart = {
234 .name = "pxa2xx-uart",
235 .id = 1,
236 .resource = pxa_resource_btuart,
237 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
238};
239
cc155c6f
RK		 240void __init pxa_set_btuart_info(void *info)
241{
242 pxa_register_device(&pxa_device_btuart, info);
243}
244
8f58de7c 245static struct resource pxa_resource_stuart[] = {
246 {
02f65262
EM		 247 .start = 0x40700000,
248 .end = 0x40700023,
8f58de7c 249 .flags = IORESOURCE_MEM,
250 }, {
251 .start = IRQ_STUART,
252 .end = IRQ_STUART,
253 .flags = IORESOURCE_IRQ,
254 }
255};
256
257struct platform_device pxa_device_stuart = {
258 .name = "pxa2xx-uart",
259 .id = 2,
260 .resource = pxa_resource_stuart,
261 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
262};
263
cc155c6f
RK		 264void __init pxa_set_stuart_info(void *info)
265{
266 pxa_register_device(&pxa_device_stuart, info);
267}
268
8f58de7c 269static struct resource pxa_resource_hwuart[] = {
270 {
02f65262
EM		 271 .start = 0x41600000,
272 .end = 0x4160002F,
8f58de7c 273 .flags = IORESOURCE_MEM,
274 }, {
275 .start = IRQ_HWUART,
276 .end = IRQ_HWUART,
277 .flags = IORESOURCE_IRQ,
278 }
279};
280
281struct platform_device pxa_device_hwuart = {
282 .name = "pxa2xx-uart",
283 .id = 3,
284 .resource = pxa_resource_hwuart,
285 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
286};
287
cc155c6f
RK		 288void __init pxa_set_hwuart_info(void *info)
289{
290 if (cpu_is_pxa255())
291 pxa_register_device(&pxa_device_hwuart, info);
292 else
293 pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
294}
295
8f58de7c 296static struct resource pxai2c_resources[] = {
297 {
298 .start = 0x40301680,
299 .end = 0x403016a3,
300 .flags = IORESOURCE_MEM,
301 }, {
302 .start = IRQ_I2C,
303 .end = IRQ_I2C,
304 .flags = IORESOURCE_IRQ,
305 },
306};
307
308struct platform_device pxa_device_i2c = {
309 .name = "pxa2xx-i2c",
310 .id = 0,
311 .resource = pxai2c_resources,
312 .num_resources = ARRAY_SIZE(pxai2c_resources),
313};
314
315void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
316{
317 pxa_register_device(&pxa_device_i2c, info);
318}
319
99464293
EM		 320#ifdef CONFIG_PXA27x
321static struct resource pxa27x_resources_i2c_power[] = {
322 {
323 .start = 0x40f00180,
324 .end = 0x40f001a3,
325 .flags = IORESOURCE_MEM,
326 }, {
327 .start = IRQ_PWRI2C,
328 .end = IRQ_PWRI2C,
329 .flags = IORESOURCE_IRQ,
330 },
331};
332
333struct platform_device pxa27x_device_i2c_power = {
334 .name = "pxa2xx-i2c",
335 .id = 1,
336 .resource = pxa27x_resources_i2c_power,
337 .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
338};
339#endif
340
8f58de7c 341static struct resource pxai2s_resources[] = {
342 {
343 .start = 0x40400000,
344 .end = 0x40400083,
345 .flags = IORESOURCE_MEM,
346 }, {
347 .start = IRQ_I2S,
348 .end = IRQ_I2S,
349 .flags = IORESOURCE_IRQ,
350 },
351};
352
353struct platform_device pxa_device_i2s = {
354 .name = "pxa2xx-i2s",
355 .id = -1,
356 .resource = pxai2s_resources,
357 .num_resources = ARRAY_SIZE(pxai2s_resources),
358};
359
f0fba2ad
LG		 360struct platform_device pxa_device_asoc_ssp1 = {
361 .name = "pxa-ssp-dai",
362 .id = 0,
363};
364
365struct platform_device pxa_device_asoc_ssp2= {
366 .name = "pxa-ssp-dai",
367 .id = 1,
368};
369
370struct platform_device pxa_device_asoc_ssp3 = {
371 .name = "pxa-ssp-dai",
372 .id = 2,
373};
374
375struct platform_device pxa_device_asoc_ssp4 = {
376 .name = "pxa-ssp-dai",
377 .id = 3,
378};
379
380struct platform_device pxa_device_asoc_platform = {
381 .name = "pxa-pcm-audio",
382 .id = -1,
383};
384
8f58de7c 385static u64 pxaficp_dmamask = ~(u32)0;
386
121f3f9b
RH		 387static struct resource pxa_ir_resources[] = {
388 [0] = {
389 .start = IRQ_STUART,
390 .end = IRQ_STUART,
391 .flags = IORESOURCE_IRQ,
392 },
393 [1] = {
394 .start = IRQ_ICP,
395 .end = IRQ_ICP,
396 .flags = IORESOURCE_IRQ,
397 },
398};
399
8f58de7c 400struct platform_device pxa_device_ficp = {
401 .name = "pxa2xx-ir",
402 .id = -1,
121f3f9b
RH		 403 .num_resources = ARRAY_SIZE(pxa_ir_resources),
404 .resource = pxa_ir_resources,
8f58de7c 405 .dev = {
406 .dma_mask = &pxaficp_dmamask,
407 .coherent_dma_mask = 0xffffffff,
408 },
409};
410
411void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
412{
413 pxa_register_device(&pxa_device_ficp, info);
414}
415
72493146
RJ		 416static struct resource pxa_rtc_resources[] = {
417 [0] = {
418 .start = 0x40900000,
419 .end = 0x40900000 + 0x3b,
420 .flags = IORESOURCE_MEM,
421 },
422 [1] = {
423 .start = IRQ_RTC1Hz,
424 .end = IRQ_RTC1Hz,
3888c090 425 .name = "rtc 1Hz",
72493146
RJ		 426 .flags = IORESOURCE_IRQ,
427 },
428 [2] = {
429 .start = IRQ_RTCAlrm,
430 .end = IRQ_RTCAlrm,
3888c090 431 .name = "rtc alarm",
72493146
RJ		 432 .flags = IORESOURCE_IRQ,
433 },
434};
435
72493146
RJ		 436struct platform_device pxa_device_rtc = {
437 .name = "pxa-rtc",
438 .id = -1,
439 .num_resources = ARRAY_SIZE(pxa_rtc_resources),
440 .resource = pxa_rtc_resources,
441};
442
3888c090
HZ		 443static struct resource sa1100_rtc_resources[] = {
444 {
445 .start = IRQ_RTC1Hz,
446 .end = IRQ_RTC1Hz,
447 .name = "rtc 1Hz",
448 .flags = IORESOURCE_IRQ,
449 }, {
450 .start = IRQ_RTCAlrm,
451 .end = IRQ_RTCAlrm,
452 .name = "rtc alarm",
453 .flags = IORESOURCE_IRQ,
454 },
455};
456
457struct platform_device sa1100_device_rtc = {
458 .name = "sa1100-rtc",
459 .id = -1,
460 .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
461 .resource = sa1100_rtc_resources,
462};
463
9f19d638
MB		 464static struct resource pxa_ac97_resources[] = {
465 [0] = {
466 .start = 0x40500000,
467 .end = 0x40500000 + 0xfff,
468 .flags = IORESOURCE_MEM,
469 },
470 [1] = {
471 .start = IRQ_AC97,
472 .end = IRQ_AC97,
473 .flags = IORESOURCE_IRQ,
474 },
475};
476
477static u64 pxa_ac97_dmamask = 0xffffffffUL;
478
479struct platform_device pxa_device_ac97 = {
480 .name = "pxa2xx-ac97",
481 .id = -1,
482 .dev = {
483 .dma_mask = &pxa_ac97_dmamask,
484 .coherent_dma_mask = 0xffffffff,
485 },
486 .num_resources = ARRAY_SIZE(pxa_ac97_resources),
487 .resource = pxa_ac97_resources,
488};
489
490void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
491{
492 pxa_register_device(&pxa_device_ac97, ops);
493}
494
8f58de7c 495#ifdef CONFIG_PXA25x
496
75540c1a 497static struct resource pxa25x_resource_pwm0[] = {
498 [0] = {
499 .start = 0x40b00000,
500 .end = 0x40b0000f,
501 .flags = IORESOURCE_MEM,
502 },
503};
504
505struct platform_device pxa25x_device_pwm0 = {
506 .name = "pxa25x-pwm",
507 .id = 0,
508 .resource = pxa25x_resource_pwm0,
509 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
510};
511
512static struct resource pxa25x_resource_pwm1[] = {
513 [0] = {
514 .start = 0x40c00000,
515 .end = 0x40c0000f,
516 .flags = IORESOURCE_MEM,
517 },
518};
519
520struct platform_device pxa25x_device_pwm1 = {
521 .name = "pxa25x-pwm",
522 .id = 1,
523 .resource = pxa25x_resource_pwm1,
524 .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
525};
526
8f58de7c 527static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
528
529static struct resource pxa25x_resource_ssp[] = {
530 [0] = {
531 .start = 0x41000000,
532 .end = 0x4100001f,
533 .flags = IORESOURCE_MEM,
534 },
535 [1] = {
536 .start = IRQ_SSP,
537 .end = IRQ_SSP,
538 .flags = IORESOURCE_IRQ,
539 },
540 [2] = {
541 /* DRCMR for RX */
542 .start = 13,
543 .end = 13,
544 .flags = IORESOURCE_DMA,
545 },
546 [3] = {
547 /* DRCMR for TX */
548 .start = 14,
549 .end = 14,
550 .flags = IORESOURCE_DMA,
551 },
552};
553
554struct platform_device pxa25x_device_ssp = {
555 .name = "pxa25x-ssp",
556 .id = 0,
557 .dev = {
558 .dma_mask = &pxa25x_ssp_dma_mask,
559 .coherent_dma_mask = DMA_BIT_MASK(32),
560 },
561 .resource = pxa25x_resource_ssp,
562 .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
563};
564
565static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
566
567static struct resource pxa25x_resource_nssp[] = {
568 [0] = {
569 .start = 0x41400000,
570 .end = 0x4140002f,
571 .flags = IORESOURCE_MEM,
572 },
573 [1] = {
574 .start = IRQ_NSSP,
575 .end = IRQ_NSSP,
576 .flags = IORESOURCE_IRQ,
577 },
578 [2] = {
579 /* DRCMR for RX */
580 .start = 15,
581 .end = 15,
582 .flags = IORESOURCE_DMA,
583 },
584 [3] = {
585 /* DRCMR for TX */
586 .start = 16,
587 .end = 16,
588 .flags = IORESOURCE_DMA,
589 },
590};
591
592struct platform_device pxa25x_device_nssp = {
593 .name = "pxa25x-nssp",
594 .id = 1,
595 .dev = {
596 .dma_mask = &pxa25x_nssp_dma_mask,
597 .coherent_dma_mask = DMA_BIT_MASK(32),
598 },
599 .resource = pxa25x_resource_nssp,
600 .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
601};
602
603static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
604
605static struct resource pxa25x_resource_assp[] = {
606 [0] = {
607 .start = 0x41500000,
608 .end = 0x4150002f,
609 .flags = IORESOURCE_MEM,
610 },
611 [1] = {
612 .start = IRQ_ASSP,
613 .end = IRQ_ASSP,
614 .flags = IORESOURCE_IRQ,
615 },
616 [2] = {
617 /* DRCMR for RX */
618 .start = 23,
619 .end = 23,
620 .flags = IORESOURCE_DMA,
621 },
622 [3] = {
623 /* DRCMR for TX */
624 .start = 24,
625 .end = 24,
626 .flags = IORESOURCE_DMA,
627 },
628};
629
630struct platform_device pxa25x_device_assp = {
631 /* ASSP is basically equivalent to NSSP */
632 .name = "pxa25x-nssp",
633 .id = 2,
634 .dev = {
635 .dma_mask = &pxa25x_assp_dma_mask,
636 .coherent_dma_mask = DMA_BIT_MASK(32),
637 },
638 .resource = pxa25x_resource_assp,
639 .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
640};
641#endif /* CONFIG_PXA25x */
642
643#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
a4553358 644static struct resource pxa27x_resource_camera[] = {
37320980 645 [0] = {
a4553358
HZ		 646 .start = 0x50000000,
647 .end = 0x50000fff,
37320980 648 .flags = IORESOURCE_MEM,
649 },
650 [1] = {
a4553358
HZ		 651 .start = IRQ_CAMERA,
652 .end = IRQ_CAMERA,
37320980 653 .flags = IORESOURCE_IRQ,
654 },
655};
656
a4553358
HZ		 657static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
658
659static struct platform_device pxa27x_device_camera = {
660 .name = "pxa27x-camera",
661 .id = 0, /* This is used to put cameras on this interface */
662 .dev = {
663 .dma_mask = &pxa27x_dma_mask_camera,
664 .coherent_dma_mask = 0xffffffff,
665 },
666 .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
667 .resource = pxa27x_resource_camera,
37320980 668};
669
a4553358 670void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
37320980 671{
a4553358 672 pxa_register_device(&pxa27x_device_camera, info);
37320980 673}
674
ec68e45b 675static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
676
677static struct resource pxa27x_resource_ohci[] = {
678 [0] = {
679 .start = 0x4C000000,
680 .end = 0x4C00ff6f,
681 .flags = IORESOURCE_MEM,
682 },
683 [1] = {
684 .start = IRQ_USBH1,
685 .end = IRQ_USBH1,
686 .flags = IORESOURCE_IRQ,
687 },
688};
689
690struct platform_device pxa27x_device_ohci = {
691 .name = "pxa27x-ohci",
692 .id = -1,
693 .dev = {
694 .dma_mask = &pxa27x_ohci_dma_mask,
695 .coherent_dma_mask = DMA_BIT_MASK(32),
696 },
697 .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
698 .resource = pxa27x_resource_ohci,
699};
700
701void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
702{
703 pxa_register_device(&pxa27x_device_ohci, info);
704}
a4553358
HZ		 705#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
706
49ea7fc0 707#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
a4553358
HZ		 708static struct resource pxa27x_resource_keypad[] = {
709 [0] = {
710 .start = 0x41500000,
711 .end = 0x4150004c,
712 .flags = IORESOURCE_MEM,
713 },
714 [1] = {
715 .start = IRQ_KEYPAD,
716 .end = IRQ_KEYPAD,
717 .flags = IORESOURCE_IRQ,
718 },
719};
720
721struct platform_device pxa27x_device_keypad = {
722 .name = "pxa27x-keypad",
723 .id = -1,
724 .resource = pxa27x_resource_keypad,
725 .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
726};
727
728void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
729{
730 pxa_register_device(&pxa27x_device_keypad, info);
731}
ec68e45b 732
8f58de7c 733static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
734
735static struct resource pxa27x_resource_ssp1[] = {
736 [0] = {
737 .start = 0x41000000,
738 .end = 0x4100003f,
739 .flags = IORESOURCE_MEM,
740 },
741 [1] = {
742 .start = IRQ_SSP,
743 .end = IRQ_SSP,
744 .flags = IORESOURCE_IRQ,
745 },
746 [2] = {
747 /* DRCMR for RX */
748 .start = 13,
749 .end = 13,
750 .flags = IORESOURCE_DMA,
751 },
752 [3] = {
753 /* DRCMR for TX */
754 .start = 14,
755 .end = 14,
756 .flags = IORESOURCE_DMA,
757 },
758};
759
760struct platform_device pxa27x_device_ssp1 = {
761 .name = "pxa27x-ssp",
762 .id = 0,
763 .dev = {
764 .dma_mask = &pxa27x_ssp1_dma_mask,
765 .coherent_dma_mask = DMA_BIT_MASK(32),
766 },
767 .resource = pxa27x_resource_ssp1,
768 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
769};
770
771static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
772
773static struct resource pxa27x_resource_ssp2[] = {
774 [0] = {
775 .start = 0x41700000,
776 .end = 0x4170003f,
777 .flags = IORESOURCE_MEM,
778 },
779 [1] = {
780 .start = IRQ_SSP2,
781 .end = IRQ_SSP2,
782 .flags = IORESOURCE_IRQ,
783 },
784 [2] = {
785 /* DRCMR for RX */
786 .start = 15,
787 .end = 15,
788 .flags = IORESOURCE_DMA,
789 },
790 [3] = {
791 /* DRCMR for TX */
792 .start = 16,
793 .end = 16,
794 .flags = IORESOURCE_DMA,
795 },
796};
797
798struct platform_device pxa27x_device_ssp2 = {
799 .name = "pxa27x-ssp",
800 .id = 1,
801 .dev = {
802 .dma_mask = &pxa27x_ssp2_dma_mask,
803 .coherent_dma_mask = DMA_BIT_MASK(32),
804 },
805 .resource = pxa27x_resource_ssp2,
806 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
807};
808
809static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
810
811static struct resource pxa27x_resource_ssp3[] = {
812 [0] = {
813 .start = 0x41900000,
814 .end = 0x4190003f,
815 .flags = IORESOURCE_MEM,
816 },
817 [1] = {
818 .start = IRQ_SSP3,
819 .end = IRQ_SSP3,
820 .flags = IORESOURCE_IRQ,
821 },
822 [2] = {
823 /* DRCMR for RX */
824 .start = 66,
825 .end = 66,
826 .flags = IORESOURCE_DMA,
827 },
828 [3] = {
829 /* DRCMR for TX */
830 .start = 67,
831 .end = 67,
832 .flags = IORESOURCE_DMA,
833 },
834};
835
836struct platform_device pxa27x_device_ssp3 = {
837 .name = "pxa27x-ssp",
838 .id = 2,
839 .dev = {
840 .dma_mask = &pxa27x_ssp3_dma_mask,
841 .coherent_dma_mask = DMA_BIT_MASK(32),
842 },
843 .resource = pxa27x_resource_ssp3,
844 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
845};
3f3acefb 846
75540c1a 847static struct resource pxa27x_resource_pwm0[] = {
848 [0] = {
849 .start = 0x40b00000,
850 .end = 0x40b0001f,
851 .flags = IORESOURCE_MEM,
852 },
853};
854
855struct platform_device pxa27x_device_pwm0 = {
856 .name = "pxa27x-pwm",
857 .id = 0,
858 .resource = pxa27x_resource_pwm0,
859 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
860};
861
862static struct resource pxa27x_resource_pwm1[] = {
863 [0] = {
864 .start = 0x40c00000,
865 .end = 0x40c0001f,
866 .flags = IORESOURCE_MEM,
867 },
868};
869
870struct platform_device pxa27x_device_pwm1 = {
871 .name = "pxa27x-pwm",
872 .id = 1,
873 .resource = pxa27x_resource_pwm1,
874 .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
875};
49ea7fc0 876#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
8f58de7c 877
878#ifdef CONFIG_PXA3xx
8d33b055
BW		 879static struct resource pxa3xx_resources_mci2[] = {
880 [0] = {
881 .start = 0x42000000,
882 .end = 0x42000fff,
883 .flags = IORESOURCE_MEM,
884 },
885 [1] = {
886 .start = IRQ_MMC2,
887 .end = IRQ_MMC2,
888 .flags = IORESOURCE_IRQ,
889 },
890 [2] = {
891 .start = 93,
892 .end = 93,
893 .flags = IORESOURCE_DMA,
894 },
895 [3] = {
896 .start = 94,
897 .end = 94,
898 .flags = IORESOURCE_DMA,
899 },
900};
901
902struct platform_device pxa3xx_device_mci2 = {
903 .name = "pxa2xx-mci",
904 .id = 1,
905 .dev = {
906 .dma_mask = &pxamci_dmamask,
907 .coherent_dma_mask = 0xffffffff,
908 },
909 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
910 .resource = pxa3xx_resources_mci2,
911};
912
913void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
914{
915 pxa_register_device(&pxa3xx_device_mci2, info);
916}
917
5a1f21b1
BW		 918static struct resource pxa3xx_resources_mci3[] = {
919 [0] = {
920 .start = 0x42500000,
921 .end = 0x42500fff,
922 .flags = IORESOURCE_MEM,
923 },
924 [1] = {
925 .start = IRQ_MMC3,
926 .end = IRQ_MMC3,
927 .flags = IORESOURCE_IRQ,
928 },
929 [2] = {
930 .start = 100,
931 .end = 100,
932 .flags = IORESOURCE_DMA,
933 },
934 [3] = {
935 .start = 101,
936 .end = 101,
937 .flags = IORESOURCE_DMA,
938 },
939};
940
941struct platform_device pxa3xx_device_mci3 = {
942 .name = "pxa2xx-mci",
943 .id = 2,
944 .dev = {
945 .dma_mask = &pxamci_dmamask,
946 .coherent_dma_mask = 0xffffffff,
947 },
948 .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
949 .resource = pxa3xx_resources_mci3,
950};
951
952void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
953{
954 pxa_register_device(&pxa3xx_device_mci3, info);
955}
956
a4553358
HZ		 957static struct resource pxa3xx_resources_gcu[] = {
958 {
959 .start = 0x54000000,
960 .end = 0x54000fff,
961 .flags = IORESOURCE_MEM,
962 },
963 {
964 .start = IRQ_GCU,
965 .end = IRQ_GCU,
966 .flags = IORESOURCE_IRQ,
967 },
968};
969
970static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
971
972struct platform_device pxa3xx_device_gcu = {
973 .name = "pxa3xx-gcu",
974 .id = -1,
975 .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
976 .resource = pxa3xx_resources_gcu,
977 .dev = {
978 .dma_mask = &pxa3xx_gcu_dmamask,
979 .coherent_dma_mask = 0xffffffff,
980 },
981};
982
983#endif /* CONFIG_PXA3xx */
984
49ea7fc0 985#if defined(CONFIG_PXA3xx)
a4553358
HZ		 986static struct resource pxa3xx_resources_i2c_power[] = {
987 {
988 .start = 0x40f500c0,
989 .end = 0x40f500d3,
990 .flags = IORESOURCE_MEM,
991 }, {
992 .start = IRQ_PWRI2C,
993 .end = IRQ_PWRI2C,
994 .flags = IORESOURCE_IRQ,
995 },
996};
997
998struct platform_device pxa3xx_device_i2c_power = {
999 .name = "pxa3xx-pwri2c",
1000 .id = 1,
1001 .resource = pxa3xx_resources_i2c_power,
1002 .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
1003};
1004
9ae819a8
EM		 1005static struct resource pxa3xx_resources_nand[] = {
1006 [0] = {
1007 .start = 0x43100000,
1008 .end = 0x43100053,
1009 .flags = IORESOURCE_MEM,
1010 },
1011 [1] = {
1012 .start = IRQ_NAND,
1013 .end = IRQ_NAND,
1014 .flags = IORESOURCE_IRQ,
1015 },
1016 [2] = {
1017 /* DRCMR for Data DMA */
1018 .start = 97,
1019 .end = 97,
1020 .flags = IORESOURCE_DMA,
1021 },
1022 [3] = {
1023 /* DRCMR for Command DMA */
1024 .start = 99,
1025 .end = 99,
1026 .flags = IORESOURCE_DMA,
1027 },
1028};
1029
1030static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
1031
1032struct platform_device pxa3xx_device_nand = {
1033 .name = "pxa3xx-nand",
1034 .id = -1,
1035 .dev = {
1036 .dma_mask = &pxa3xx_nand_dma_mask,
1037 .coherent_dma_mask = DMA_BIT_MASK(32),
1038 },
1039 .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
1040 .resource = pxa3xx_resources_nand,
1041};
1042
1043void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
1044{
1045 pxa_register_device(&pxa3xx_device_nand, info);
1046}
1ff2c33e 1047
a4553358
HZ		 1048static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
1049
1050static struct resource pxa3xx_resource_ssp4[] = {
1051 [0] = {
1052 .start = 0x41a00000,
1053 .end = 0x41a0003f,
1ff2c33e
DM		 1054 .flags = IORESOURCE_MEM,
1055 },
a4553358
HZ		 1056 [1] = {
1057 .start = IRQ_SSP4,
1058 .end = IRQ_SSP4,
1ff2c33e
DM		 1059 .flags = IORESOURCE_IRQ,
1060 },
a4553358
HZ		 1061 [2] = {
1062 /* DRCMR for RX */
1063 .start = 2,
1064 .end = 2,
1065 .flags = IORESOURCE_DMA,
1066 },
1067 [3] = {
1068 /* DRCMR for TX */
1069 .start = 3,
1070 .end = 3,
1071 .flags = IORESOURCE_DMA,
1072 },
1ff2c33e
DM		 1073};
1074
0da0e227
DM		 1075/*
1076 * PXA3xx SSP is basically equivalent to PXA27x.
1077 * However, we need to register the device by the correct name in order to
1078 * make the driver set the correct internal type, hence we provide specific
1079 * platform_devices for each of them.
1080 */
1081struct platform_device pxa3xx_device_ssp1 = {
1082 .name = "pxa3xx-ssp",
1083 .id = 0,
1084 .dev = {
1085 .dma_mask = &pxa27x_ssp1_dma_mask,
1086 .coherent_dma_mask = DMA_BIT_MASK(32),
1087 },
1088 .resource = pxa27x_resource_ssp1,
1089 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
1090};
1091
1092struct platform_device pxa3xx_device_ssp2 = {
1093 .name = "pxa3xx-ssp",
1094 .id = 1,
1095 .dev = {
1096 .dma_mask = &pxa27x_ssp2_dma_mask,
1097 .coherent_dma_mask = DMA_BIT_MASK(32),
1098 },
1099 .resource = pxa27x_resource_ssp2,
1100 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
1101};
1102
1103struct platform_device pxa3xx_device_ssp3 = {
1104 .name = "pxa3xx-ssp",
1105 .id = 2,
1106 .dev = {
1107 .dma_mask = &pxa27x_ssp3_dma_mask,
1108 .coherent_dma_mask = DMA_BIT_MASK(32),
1109 },
1110 .resource = pxa27x_resource_ssp3,
1111 .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
1112};
1113
a4553358 1114struct platform_device pxa3xx_device_ssp4 = {
0da0e227 1115 .name = "pxa3xx-ssp",
a4553358 1116 .id = 3,
1ff2c33e 1117 .dev = {
a4553358
HZ		 1118 .dma_mask = &pxa3xx_ssp4_dma_mask,
1119 .coherent_dma_mask = DMA_BIT_MASK(32),
1ff2c33e 1120 },
a4553358
HZ		 1121 .resource = pxa3xx_resource_ssp4,
1122 .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
1ff2c33e 1123};
49ea7fc0 1124#endif /* CONFIG_PXA3xx */
e172274c 1125
157d2644
HZ		 1126struct resource pxa_resource_gpio[] = {
1127 {
1128 .start = 0x40e00000,
1129 .end = 0x40e0ffff,
1130 .flags = IORESOURCE_MEM,
1131 }, {
1132 .start = IRQ_GPIO0,
1133 .end = IRQ_GPIO0,
1134 .name = "gpio0",
1135 .flags = IORESOURCE_IRQ,
1136 }, {
1137 .start = IRQ_GPIO1,
1138 .end = IRQ_GPIO1,
1139 .name = "gpio1",
1140 .flags = IORESOURCE_IRQ,
1141 }, {
1142 .start = IRQ_GPIO_2_x,
1143 .end = IRQ_GPIO_2_x,
1144 .name = "gpio_mux",
1145 .flags = IORESOURCE_IRQ,
1146 },
1147};
1148
2cab0292
HZ		 1149struct platform_device pxa25x_device_gpio = {
1150#ifdef CONFIG_CPU_PXA26x
1151 .name = "pxa26x-gpio",
1152#else
1153 .name = "pxa25x-gpio",
1154#endif
1155 .id = -1,
1156 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1157 .resource = pxa_resource_gpio,
1158};
1159
1160struct platform_device pxa27x_device_gpio = {
1161 .name = "pxa27x-gpio",
1162 .id = -1,
1163 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1164 .resource = pxa_resource_gpio,
1165};
1166
1167struct platform_device pxa3xx_device_gpio = {
1168 .name = "pxa3xx-gpio",
1169 .id = -1,
1170 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1171 .resource = pxa_resource_gpio,
1172};
1173
1174struct platform_device pxa93x_device_gpio = {
1175 .name = "pxa93x-gpio",
157d2644
HZ		 1176 .id = -1,
1177 .num_resources = ARRAY_SIZE(pxa_resource_gpio),
1178 .resource = pxa_resource_gpio,
1179};
1180
e172274c
GL		 1181/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
1182 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
1183void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
1184{
1185 struct platform_device *pd;
1186
1187 pd = platform_device_alloc("pxa2xx-spi", id);
1188 if (pd == NULL) {
1189 printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
1190 id);
1191 return;
1192 }
1193
1194 pd->dev.platform_data = info;
1195 platform_device_add(pd);
1196}
4be0856f
RJ		 1197
1198static struct mmp_dma_platdata pxa_dma_pdata = {
1199 .dma_channels = 0,
1200};
1201
1202static struct resource pxa_dma_resource[] = {
1203 [0] = {
1204 .start = 0x40000000,
1205 .end = 0x4000ffff,
1206 .flags = IORESOURCE_MEM,
1207 },
1208 [1] = {
1209 .start = IRQ_DMA,
1210 .end = IRQ_DMA,
1211 .flags = IORESOURCE_IRQ,
1212 },
1213};
1214
1215static u64 pxadma_dmamask = 0xffffffffUL;
1216
1217static struct platform_device pxa2xx_pxa_dma = {
1218 .name = "pxa-dma",
1219 .id = 0,
1220 .dev = {
1221 .dma_mask = &pxadma_dmamask,
1222 .coherent_dma_mask = 0xffffffff,
1223 },
1224 .num_resources = ARRAY_SIZE(pxa_dma_resource),
1225 .resource = pxa_dma_resource,
1226};
1227
1228void __init pxa2xx_set_dmac_info(int nb_channels)
1229{
1230 pxa_dma_pdata.dma_channels = nb_channels;
1231 pxa_register_device(&pxa2xx_pxa_dma, &pxa_dma_pdata);
1232}
Linux 6.x block layer and io_uring tree(s)