[linux-2.6-block.git] / arch / arm / mach-pxa / cm-x2xx.c

/*
 * linux/arch/arm/mach-pxa/cm-x2xx.c
 *
 * Copyright (C) 2008 CompuLab, Ltd.
 * Mike Rapoport <mike@compulab.co.il>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>
#include <linux/gpio.h>

#include <linux/dm9000.h>
#include <linux/leds.h>

#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>

#include <mach/pxa25x.h>
#undef GPIO24_SSP1_SFRM
#include <mach/pxa27x.h>
#include <mach/audio.h>
#include <linux/platform_data/video-pxafb.h>
#include <mach/smemc.h>

#include <asm/hardware/it8152.h>

#include "generic.h"
#include "cm-x2xx-pci.h"

extern void cmx255_init(void);
extern void cmx270_init(void);

/* reserve IRQs for IT8152 */
#define CMX2XX_NR_IRQS		(IRQ_BOARD_START + 40)

/* virtual addresses for statically mapped regions */
#define CMX2XX_VIRT_BASE	(void __iomem *)(0xe8000000)
#define CMX2XX_IT8152_VIRT	(CMX2XX_VIRT_BASE)

/* physical address if local-bus attached devices */
#define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22))
#define CMX270_DM9000_PHYS_BASE	(PXA_CS1_PHYS + (6 << 22))

/* leds */
#define CMX255_GPIO_RED		(27)
#define CMX255_GPIO_GREEN	(32)
#define CMX270_GPIO_RED		(93)
#define CMX270_GPIO_GREEN	(94)

/* GPIO IRQ usage */
#define GPIO22_ETHIRQ		(22)
#define GPIO10_ETHIRQ		(10)
#define CMX255_GPIO_IT8152_IRQ	(0)
#define CMX270_GPIO_IT8152_IRQ	(22)

#define CMX255_ETHIRQ		PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ)
#define CMX270_ETHIRQ		PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ)

#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
static struct resource cmx255_dm9000_resource[] = {
	[0] = {
		.start = CMX255_DM9000_PHYS_BASE,
		.end   = CMX255_DM9000_PHYS_BASE + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = CMX255_DM9000_PHYS_BASE + 4,
		.end   = CMX255_DM9000_PHYS_BASE + 4 + 500,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = CMX255_ETHIRQ,
		.end   = CMX255_ETHIRQ,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	}
};

static struct resource cmx270_dm9000_resource[] = {
	[0] = {
		.start = CMX270_DM9000_PHYS_BASE,
		.end   = CMX270_DM9000_PHYS_BASE + 3,
		.flags = IORESOURCE_MEM,
	},
	[1] = {
		.start = CMX270_DM9000_PHYS_BASE + 8,
		.end   = CMX270_DM9000_PHYS_BASE + 8 + 500,
		.flags = IORESOURCE_MEM,
	},
	[2] = {
		.start = CMX270_ETHIRQ,
		.end   = CMX270_ETHIRQ,
		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
	}
};

static struct dm9000_plat_data cmx270_dm9000_platdata = {
	.flags		= DM9000_PLATF_32BITONLY | DM9000_PLATF_NO_EEPROM,
};

static struct platform_device cmx2xx_dm9000_device = {
	.name		= "dm9000",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(cmx270_dm9000_resource),
	.dev		= {
		.platform_data = &cmx270_dm9000_platdata,
	}
};

static void __init cmx2xx_init_dm9000(void)
{
	if (cpu_is_pxa25x())
		cmx2xx_dm9000_device.resource = cmx255_dm9000_resource;
	else
		cmx2xx_dm9000_device.resource = cmx270_dm9000_resource;
	platform_device_register(&cmx2xx_dm9000_device);
}
#else
static inline void cmx2xx_init_dm9000(void) {}
#endif

/* UCB1400 touchscreen controller */
#if defined(CONFIG_TOUCHSCREEN_UCB1400) || defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
static struct platform_device cmx2xx_ts_device = {
	.name		= "ucb1400_core",
	.id		= -1,
};

static void __init cmx2xx_init_touchscreen(void)
{
	platform_device_register(&cmx2xx_ts_device);
}
#else
static inline void cmx2xx_init_touchscreen(void) {}
#endif

/* CM-X270 LEDs */
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
static struct gpio_led cmx2xx_leds[] = {
	[0] = {
		.name = "cm-x2xx:red",
		.default_trigger = "nand-disk",
		.active_low = 1,
	},
	[1] = {
		.name = "cm-x2xx:green",
		.default_trigger = "heartbeat",
		.active_low = 1,
	},
};

static struct gpio_led_platform_data cmx2xx_gpio_led_pdata = {
	.num_leds = ARRAY_SIZE(cmx2xx_leds),
	.leds = cmx2xx_leds,
};

static struct platform_device cmx2xx_led_device = {
	.name		= "leds-gpio",
	.id		= -1,
	.dev		= {
		.platform_data = &cmx2xx_gpio_led_pdata,
	},
};

static void __init cmx2xx_init_leds(void)
{
	if (cpu_is_pxa25x()) {
		cmx2xx_leds[0].gpio = CMX255_GPIO_RED;
		cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN;
	} else {
		cmx2xx_leds[0].gpio = CMX270_GPIO_RED;
		cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN;
	}
	platform_device_register(&cmx2xx_led_device);
}
#else
static inline void cmx2xx_init_leds(void) {}
#endif

#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
/*
  Display definitions
  keep these for backwards compatibility, although symbolic names (as
  e.g. in lpd270.c) looks better
*/
#define MTYPE_STN320x240	0
#define MTYPE_TFT640x480	1
#define MTYPE_CRT640x480	2
#define MTYPE_CRT800x600	3
#define MTYPE_TFT320x240	6
#define MTYPE_STN640x480	7

static struct pxafb_mode_info generic_stn_320x240_mode = {
	.pixclock	= 76923,
	.bpp		= 8,
	.xres		= 320,
	.yres		= 240,
	.hsync_len	= 3,
	.vsync_len	= 2,
	.left_margin	= 3,
	.upper_margin	= 0,
	.right_margin	= 3,
	.lower_margin	= 0,
	.sync		= (FB_SYNC_HOR_HIGH_ACT |
			   FB_SYNC_VERT_HIGH_ACT),
	.cmap_greyscale = 0,
};

static struct pxafb_mach_info generic_stn_320x240 = {
	.modes		= &generic_stn_320x240_mode,
	.num_modes	= 1,
	.lcd_conn	= LCD_COLOR_STN_8BPP | LCD_PCLK_EDGE_FALL |\
			  LCD_AC_BIAS_FREQ(0xff),
	.cmap_inverse	= 0,
	.cmap_static	= 0,
};

static struct pxafb_mode_info generic_tft_640x480_mode = {
	.pixclock	= 38461,
	.bpp		= 8,
	.xres		= 640,
	.yres		= 480,
	.hsync_len	= 60,
	.vsync_len	= 2,
	.left_margin	= 70,
	.upper_margin	= 10,
	.right_margin	= 70,
	.lower_margin	= 5,
	.sync		= 0,
	.cmap_greyscale = 0,
};

static struct pxafb_mach_info generic_tft_640x480 = {
	.modes		= &generic_tft_640x480_mode,
	.num_modes	= 1,
	.lcd_conn	= LCD_COLOR_TFT_8BPP | LCD_PCLK_EDGE_FALL |\
			  LCD_AC_BIAS_FREQ(0xff),
	.cmap_inverse	= 0,
	.cmap_static	= 0,
};

static struct pxafb_mode_info generic_crt_640x480_mode = {
	.pixclock	= 38461,
	.bpp		= 8,
	.xres		= 640,
	.yres		= 480,
	.hsync_len	= 63,
	.vsync_len	= 2,
	.left_margin	= 81,
	.upper_margin	= 33,
	.right_margin	= 16,
	.lower_margin	= 10,
	.sync		= (FB_SYNC_HOR_HIGH_ACT |
			   FB_SYNC_VERT_HIGH_ACT),
	.cmap_greyscale = 0,
};

static struct pxafb_mach_info generic_crt_640x480 = {
	.modes		= &generic_crt_640x480_mode,
	.num_modes	= 1,
	.lcd_conn	= LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
	.cmap_inverse	= 0,
	.cmap_static	= 0,
};

static struct pxafb_mode_info generic_crt_800x600_mode = {
	.pixclock	= 28846,
	.bpp		= 8,
	.xres		= 800,
	.yres	  	= 600,
	.hsync_len	= 63,
	.vsync_len	= 2,
	.left_margin	= 26,
	.upper_margin	= 21,
	.right_margin	= 26,
	.lower_margin	= 11,
	.sync		= (FB_SYNC_HOR_HIGH_ACT |
			   FB_SYNC_VERT_HIGH_ACT),
	.cmap_greyscale = 0,
};

static struct pxafb_mach_info generic_crt_800x600 = {
	.modes		= &generic_crt_800x600_mode,
	.num_modes	= 1,
	.lcd_conn	= LCD_COLOR_TFT_8BPP | LCD_AC_BIAS_FREQ(0xff),
	.cmap_inverse	= 0,
	.cmap_static	= 0,
};

static struct pxafb_mode_info generic_tft_320x240_mode = {
	.pixclock	= 134615,
	.bpp		= 16,
	.xres		= 320,
	.yres		= 240,
	.hsync_len	= 63,
	.vsync_len	= 7,
	.left_margin	= 75,
	.upper_margin	= 0,
	.right_margin	= 15,
	.lower_margin	= 15,
	.sync		= 0,
	.cmap_greyscale = 0,
};

static struct pxafb_mach_info generic_tft_320x240 = {
	.modes		= &generic_tft_320x240_mode,
	.num_modes	= 1,
	.lcd_conn	= LCD_COLOR_TFT_16BPP | LCD_AC_BIAS_FREQ(0xff),
	.cmap_inverse	= 0,
	.cmap_static	= 0,
};

static struct pxafb_mode_info generic_stn_640x480_mode = {
	.pixclock	= 57692,
	.bpp		= 8,
	.xres		= 640,
	.yres		= 480,
	.hsync_len	= 4,
	.vsync_len	= 2,
	.left_margin	= 10,
	.upper_margin	= 5,
	.right_margin	= 10,
	.lower_margin	= 5,
	.sync		= (FB_SYNC_HOR_HIGH_ACT |
			   FB_SYNC_VERT_HIGH_ACT),
	.cmap_greyscale = 0,
};

static struct pxafb_mach_info generic_stn_640x480 = {
	.modes		= &generic_stn_640x480_mode,
	.num_modes	= 1,
	.lcd_conn	= LCD_COLOR_STN_8BPP | LCD_AC_BIAS_FREQ(0xff),
	.cmap_inverse	= 0,
	.cmap_static	= 0,
};

static struct pxafb_mach_info *cmx2xx_display = &generic_crt_640x480;

static int __init cmx2xx_set_display(char *str)
{
	int disp_type = simple_strtol(str, NULL, 0);
	switch (disp_type) {
	case MTYPE_STN320x240:
		cmx2xx_display = &generic_stn_320x240;
		break;
	case MTYPE_TFT640x480:
		cmx2xx_display = &generic_tft_640x480;
		break;
	case MTYPE_CRT640x480:
		cmx2xx_display = &generic_crt_640x480;
		break;
	case MTYPE_CRT800x600:
		cmx2xx_display = &generic_crt_800x600;
		break;
	case MTYPE_TFT320x240:
		cmx2xx_display = &generic_tft_320x240;
		break;
	case MTYPE_STN640x480:
		cmx2xx_display = &generic_stn_640x480;
		break;
	default: /* fallback to CRT 640x480 */
		cmx2xx_display = &generic_crt_640x480;
		break;
	}
	return 1;
}

/*
   This should be done really early to get proper configuration for
   frame buffer.
   Indeed, pxafb parameters can be used istead, but CM-X2XX bootloader
   has limitied line length for kernel command line, and also it will
   break compatibitlty with proprietary releases already in field.
*/
__setup("monitor=", cmx2xx_set_display);

static void __init cmx2xx_init_display(void)
{
	pxa_set_fb_info(NULL, cmx2xx_display);
}
#else
static inline void cmx2xx_init_display(void) {}
#endif

#ifdef CONFIG_PM
static unsigned long sleep_save_msc[10];

static int cmx2xx_suspend(void)
{
	cmx2xx_pci_suspend();

	/* save MSC registers */
	sleep_save_msc[0] = __raw_readl(MSC0);
	sleep_save_msc[1] = __raw_readl(MSC1);
	sleep_save_msc[2] = __raw_readl(MSC2);

	/* setup power saving mode registers */
	PCFR = 0x0;
	PSLR = 0xff400000;
	PMCR  = 0x00000005;
	PWER  = 0x80000000;
	PFER  = 0x00000000;
	PRER  = 0x00000000;
	PGSR0 = 0xC0018800;
	PGSR1 = 0x004F0002;
	PGSR2 = 0x6021C000;
	PGSR3 = 0x00020000;

	return 0;
}

static void cmx2xx_resume(void)
{
	cmx2xx_pci_resume();

	/* restore MSC registers */
	__raw_writel(sleep_save_msc[0], MSC0);
	__raw_writel(sleep_save_msc[1], MSC1);
	__raw_writel(sleep_save_msc[2], MSC2);
}

static struct syscore_ops cmx2xx_pm_syscore_ops = {
	.resume = cmx2xx_resume,
	.suspend = cmx2xx_suspend,
};

static int __init cmx2xx_pm_init(void)
{
	register_syscore_ops(&cmx2xx_pm_syscore_ops);

	return 0;
}
#else
static int __init cmx2xx_pm_init(void) { return 0; }
#endif

#if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE)
static void __init cmx2xx_init_ac97(void)
{
	pxa_set_ac97_info(NULL);
}
#else
static inline void cmx2xx_init_ac97(void) {}
#endif

static void __init cmx2xx_init(void)
{
	pxa_set_ffuart_info(NULL);
	pxa_set_btuart_info(NULL);
	pxa_set_stuart_info(NULL);

	cmx2xx_pm_init();

	if (cpu_is_pxa25x())
		cmx255_init();
	else
		cmx270_init();

	cmx2xx_init_dm9000();
	cmx2xx_init_display();
	cmx2xx_init_ac97();
	cmx2xx_init_touchscreen();
	cmx2xx_init_leds();
}

static void __init cmx2xx_init_irq(void)
{
	if (cpu_is_pxa25x()) {
		pxa25x_init_irq();
		cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);
	} else {
		pxa27x_init_irq();
		cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ);
	}
}

#ifdef CONFIG_PCI
/* Map PCI companion statically */
static struct map_desc cmx2xx_io_desc[] __initdata = {
	[0] = { /* PCI bridge */
		.virtual	= (unsigned long)CMX2XX_IT8152_VIRT,
		.pfn		= __phys_to_pfn(PXA_CS4_PHYS),
		.length		= SZ_64M,
		.type		= MT_DEVICE
	},
};

static void __init cmx2xx_map_io(void)
{
	if (cpu_is_pxa25x())
		pxa25x_map_io();

	if (cpu_is_pxa27x())
		pxa27x_map_io();

	iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));

	it8152_base_address = CMX2XX_IT8152_VIRT;
}
#else
static void __init cmx2xx_map_io(void)
{
	if (cpu_is_pxa25x())
		pxa25x_map_io();

	if (cpu_is_pxa27x())
		pxa27x_map_io();
}
#endif

MACHINE_START(ARMCORE, "Compulab CM-X2XX")
	.atag_offset	= 0x100,
	.map_io		= cmx2xx_map_io,
	.nr_irqs	= CMX2XX_NR_IRQS,
	.init_irq	= cmx2xx_init_irq,
	/* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */
	.handle_irq	= pxa25x_handle_irq,
	.init_time	= pxa_timer_init,
	.init_machine	= cmx2xx_init,
#ifdef CONFIG_PCI
	.dma_zone_size	= SZ_64M,
#endif
	.restart	= pxa_restart,
MACHINE_END
Commit	Line	Data
3696a8a4	1	/*
da591937	2	* linux/arch/arm/mach-pxa/cm-x2xx.c
3696a8a4	3	*
4adc5fb6	4	* Copyright (C) 2008 CompuLab, Ltd.
3696a8a4 MR	5	* Mike Rapoport <mike@compulab.co.il>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
3696a8a4	12	#include <linux/platform_device.h>
2eaa03b5	13	#include <linux/syscore_ops.h>
2f01a973 MR	14	#include <linux/irq.h>
2f01a973 MR	15	#include <linux/gpio.h>
3696a8a4 MR	16
3696a8a4 MR	17	#include <linux/dm9000.h>
2f01a973	18	#include <linux/leds.h>
3696a8a4 MR	19
	20	#include <asm/mach/arch.h>
	21	#include <asm/mach-types.h>
	22	#include <asm/mach/map.h>
	23
ca0e687c	24	#include <mach/pxa25x.h>
e0347c52	25	#undef GPIO24_SSP1_SFRM
ca0e687c	26	#include <mach/pxa27x.h>
a09e64fb	27	#include <mach/audio.h>
293b2da1	28	#include <linux/platform_data/video-pxafb.h>
ad68bb9f	29	#include <mach/smemc.h>
3696a8a4 MR	30
	31	#include <asm/hardware/it8152.h>
	32
	33	#include "generic.h"
7d76e3f1	34	#include "cm-x2xx-pci.h"
3696a8a4	35
a7f3f030	36	extern void cmx255_init(void);
4adc5fb6 MR	37	extern void cmx270_init(void);
4adc5fb6 MR	38
6ac6b817 HZ	39	/* reserve IRQs for IT8152 */
	40	#define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40)
	41
2f01a973	42	/* virtual addresses for statically mapped regions */
97b09da4	43	#define CMX2XX_VIRT_BASE (void __iomem *)(0xe8000000)
da591937	44	#define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE)
2f01a973	45
4adc5fb6	46	/* physical address if local-bus attached devices */
a7f3f030	47	#define CMX255_DM9000_PHYS_BASE (PXA_CS1_PHYS + (8 << 22))
da591937 MR	48	#define CMX270_DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
	49
	50	/* leds */
a7f3f030 MR	51	#define CMX255_GPIO_RED (27)
a7f3f030 MR	52	#define CMX255_GPIO_GREEN (32)
da591937 MR	53	#define CMX270_GPIO_RED (93)
da591937 MR	54	#define CMX270_GPIO_GREEN (94)
3696a8a4	55
2f01a973	56	/* GPIO IRQ usage */
a7f3f030	57	#define GPIO22_ETHIRQ (22)
2f01a973	58	#define GPIO10_ETHIRQ (10)
a7f3f030	59	#define CMX255_GPIO_IT8152_IRQ (0)
da591937	60	#define CMX270_GPIO_IT8152_IRQ (22)
2f01a973	61
6384fdad HZ	62	#define CMX255_ETHIRQ PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ)
6384fdad HZ	63	#define CMX270_ETHIRQ PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ)
2f01a973 MR	64
2f01a973 MR	65	#if defined(CONFIG_DM9000) \|\| defined(CONFIG_DM9000_MODULE)
a7f3f030 MR	66	static struct resource cmx255_dm9000_resource[] = {
	67	[0] = {
	68	.start = CMX255_DM9000_PHYS_BASE,
	69	.end = CMX255_DM9000_PHYS_BASE + 3,
	70	.flags = IORESOURCE_MEM,
	71	},
	72	[1] = {
	73	.start = CMX255_DM9000_PHYS_BASE + 4,
	74	.end = CMX255_DM9000_PHYS_BASE + 4 + 500,
	75	.flags = IORESOURCE_MEM,
	76	},
	77	[2] = {
	78	.start = CMX255_ETHIRQ,
	79	.end = CMX255_ETHIRQ,
	80	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
	81	}
	82	};
	83
2f01a973	84	static struct resource cmx270_dm9000_resource[] = {
3696a8a4	85	[0] = {
da591937 MR	86	.start = CMX270_DM9000_PHYS_BASE,
da591937 MR	87	.end = CMX270_DM9000_PHYS_BASE + 3,
3696a8a4 MR	88	.flags = IORESOURCE_MEM,
	89	},
	90	[1] = {
da591937 MR	91	.start = CMX270_DM9000_PHYS_BASE + 8,
da591937 MR	92	.end = CMX270_DM9000_PHYS_BASE + 8 + 500,
3696a8a4 MR	93	.flags = IORESOURCE_MEM,
	94	},
	95	[2] = {
	96	.start = CMX270_ETHIRQ,
	97	.end = CMX270_ETHIRQ,
2f01a973	98	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_HIGHEDGE,
3696a8a4 MR	99	}
	100	};
	101
2f01a973	102	static struct dm9000_plat_data cmx270_dm9000_platdata = {
bff22c9b	103	.flags = DM9000_PLATF_32BITONLY \| DM9000_PLATF_NO_EEPROM,
3696a8a4 MR	104	};
3696a8a4 MR	105
da591937	106	static struct platform_device cmx2xx_dm9000_device = {
3696a8a4 MR	107	.name = "dm9000",
3696a8a4 MR	108	.id = 0,
2f01a973	109	.num_resources = ARRAY_SIZE(cmx270_dm9000_resource),
3696a8a4	110	.dev = {
2f01a973	111	.platform_data = &cmx270_dm9000_platdata,
3696a8a4 MR	112	}
	113	};
	114
da591937	115	static void __init cmx2xx_init_dm9000(void)
2f01a973	116	{
a7f3f030 MR	117	if (cpu_is_pxa25x())
	118	cmx2xx_dm9000_device.resource = cmx255_dm9000_resource;
	119	else
	120	cmx2xx_dm9000_device.resource = cmx270_dm9000_resource;
da591937	121	platform_device_register(&cmx2xx_dm9000_device);
2f01a973 MR	122	}
2f01a973 MR	123	#else
da591937	124	static inline void cmx2xx_init_dm9000(void) {}
2f01a973 MR	125	#endif
	126
	127	/* UCB1400 touchscreen controller */
	128	#if defined(CONFIG_TOUCHSCREEN_UCB1400) \|\| defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
da591937	129	static struct platform_device cmx2xx_ts_device = {
50f6bb0a	130	.name = "ucb1400_core",
3696a8a4 MR	131	.id = -1,
	132	};
	133
da591937	134	static void __init cmx2xx_init_touchscreen(void)
2f01a973	135	{
da591937	136	platform_device_register(&cmx2xx_ts_device);
2f01a973 MR	137	}
2f01a973 MR	138	#else
da591937	139	static inline void cmx2xx_init_touchscreen(void) {}
2f01a973 MR	140	#endif
2f01a973 MR	141
2f01a973 MR	142	/* CM-X270 LEDs */
2f01a973 MR	143	#if defined(CONFIG_LEDS_GPIO) \|\| defined(CONFIG_LEDS_GPIO_MODULE)
da591937	144	static struct gpio_led cmx2xx_leds[] = {
2f01a973	145	[0] = {
da591937	146	.name = "cm-x2xx:red",
2f01a973	147	.default_trigger = "nand-disk",
2f01a973 MR	148	.active_low = 1,
	149	},
	150	[1] = {
da591937	151	.name = "cm-x2xx:green",
2f01a973	152	.default_trigger = "heartbeat",
2f01a973 MR	153	.active_low = 1,
	154	},
	155	};
	156
da591937 MR	157	static struct gpio_led_platform_data cmx2xx_gpio_led_pdata = {
	158	.num_leds = ARRAY_SIZE(cmx2xx_leds),
	159	.leds = cmx2xx_leds,
2f01a973 MR	160	};
2f01a973 MR	161
da591937	162	static struct platform_device cmx2xx_led_device = {
2f01a973	163	.name = "leds-gpio",
3696a8a4	164	.id = -1,
2f01a973	165	.dev = {
da591937	166	.platform_data = &cmx2xx_gpio_led_pdata,
2f01a973	167	},
3696a8a4 MR	168	};
3696a8a4 MR	169
da591937	170	static void __init cmx2xx_init_leds(void)
2f01a973	171	{
a7f3f030 MR	172	if (cpu_is_pxa25x()) {
	173	cmx2xx_leds[0].gpio = CMX255_GPIO_RED;
	174	cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN;
	175	} else {
	176	cmx2xx_leds[0].gpio = CMX270_GPIO_RED;
	177	cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN;
	178	}
da591937	179	platform_device_register(&cmx2xx_led_device);
2f01a973 MR	180	}
2f01a973 MR	181	#else
da591937	182	static inline void cmx2xx_init_leds(void) {}
2f01a973 MR	183	#endif
2f01a973 MR	184
2f01a973	185	#if defined(CONFIG_FB_PXA) \|\| defined(CONFIG_FB_PXA_MODULE)
3696a8a4 MR	186	/*
	187	Display definitions
	188	keep these for backwards compatibility, although symbolic names (as
	189	e.g. in lpd270.c) looks better
	190	*/
	191	#define MTYPE_STN320x240 0
	192	#define MTYPE_TFT640x480 1
	193	#define MTYPE_CRT640x480 2
	194	#define MTYPE_CRT800x600 3
	195	#define MTYPE_TFT320x240 6
	196	#define MTYPE_STN640x480 7
	197
	198	static struct pxafb_mode_info generic_stn_320x240_mode = {
	199	.pixclock = 76923,
	200	.bpp = 8,
	201	.xres = 320,
	202	.yres = 240,
	203	.hsync_len = 3,
	204	.vsync_len = 2,
	205	.left_margin = 3,
	206	.upper_margin = 0,
	207	.right_margin = 3,
	208	.lower_margin = 0,
	209	.sync = (FB_SYNC_HOR_HIGH_ACT \|
	210	FB_SYNC_VERT_HIGH_ACT),
	211	.cmap_greyscale = 0,
	212	};
	213
	214	static struct pxafb_mach_info generic_stn_320x240 = {
	215	.modes = &generic_stn_320x240_mode,
	216	.num_modes = 1,
9587319b EM	217	.lcd_conn = LCD_COLOR_STN_8BPP \| LCD_PCLK_EDGE_FALL \|\
9587319b EM	218	LCD_AC_BIAS_FREQ(0xff),
3696a8a4 MR	219	.cmap_inverse = 0,
	220	.cmap_static = 0,
	221	};
	222
	223	static struct pxafb_mode_info generic_tft_640x480_mode = {
	224	.pixclock = 38461,
	225	.bpp = 8,
	226	.xres = 640,
	227	.yres = 480,
	228	.hsync_len = 60,
	229	.vsync_len = 2,
	230	.left_margin = 70,
	231	.upper_margin = 10,
	232	.right_margin = 70,
	233	.lower_margin = 5,
	234	.sync = 0,
	235	.cmap_greyscale = 0,
	236	};
	237
	238	static struct pxafb_mach_info generic_tft_640x480 = {
	239	.modes = &generic_tft_640x480_mode,
	240	.num_modes = 1,
9587319b EM	241	.lcd_conn = LCD_COLOR_TFT_8BPP \| LCD_PCLK_EDGE_FALL \|\
9587319b EM	242	LCD_AC_BIAS_FREQ(0xff),
3696a8a4 MR	243	.cmap_inverse = 0,
	244	.cmap_static = 0,
	245	};
	246
	247	static struct pxafb_mode_info generic_crt_640x480_mode = {
	248	.pixclock = 38461,
	249	.bpp = 8,
	250	.xres = 640,
	251	.yres = 480,
	252	.hsync_len = 63,
	253	.vsync_len = 2,
	254	.left_margin = 81,
	255	.upper_margin = 33,
	256	.right_margin = 16,
	257	.lower_margin = 10,
	258	.sync = (FB_SYNC_HOR_HIGH_ACT \|
	259	FB_SYNC_VERT_HIGH_ACT),
	260	.cmap_greyscale = 0,
	261	};
	262
	263	static struct pxafb_mach_info generic_crt_640x480 = {
	264	.modes = &generic_crt_640x480_mode,
	265	.num_modes = 1,
9587319b	266	.lcd_conn = LCD_COLOR_TFT_8BPP \| LCD_AC_BIAS_FREQ(0xff),
3696a8a4 MR	267	.cmap_inverse = 0,
	268	.cmap_static = 0,
	269	};
	270
	271	static struct pxafb_mode_info generic_crt_800x600_mode = {
	272	.pixclock = 28846,
	273	.bpp = 8,
	274	.xres = 800,
	275	.yres = 600,
	276	.hsync_len = 63,
	277	.vsync_len = 2,
	278	.left_margin = 26,
	279	.upper_margin = 21,
	280	.right_margin = 26,
	281	.lower_margin = 11,
	282	.sync = (FB_SYNC_HOR_HIGH_ACT \|
	283	FB_SYNC_VERT_HIGH_ACT),
	284	.cmap_greyscale = 0,
	285	};
	286
	287	static struct pxafb_mach_info generic_crt_800x600 = {
	288	.modes = &generic_crt_800x600_mode,
	289	.num_modes = 1,
9587319b	290	.lcd_conn = LCD_COLOR_TFT_8BPP \| LCD_AC_BIAS_FREQ(0xff),
3696a8a4 MR	291	.cmap_inverse = 0,
	292	.cmap_static = 0,
	293	};
	294
	295	static struct pxafb_mode_info generic_tft_320x240_mode = {
	296	.pixclock = 134615,
	297	.bpp = 16,
	298	.xres = 320,
	299	.yres = 240,
	300	.hsync_len = 63,
	301	.vsync_len = 7,
	302	.left_margin = 75,
	303	.upper_margin = 0,
	304	.right_margin = 15,
	305	.lower_margin = 15,
	306	.sync = 0,
	307	.cmap_greyscale = 0,
	308	};
	309
	310	static struct pxafb_mach_info generic_tft_320x240 = {
	311	.modes = &generic_tft_320x240_mode,
	312	.num_modes = 1,
9587319b	313	.lcd_conn = LCD_COLOR_TFT_16BPP \| LCD_AC_BIAS_FREQ(0xff),
3696a8a4 MR	314	.cmap_inverse = 0,
	315	.cmap_static = 0,
	316	};
	317
	318	static struct pxafb_mode_info generic_stn_640x480_mode = {
	319	.pixclock = 57692,
	320	.bpp = 8,
	321	.xres = 640,
	322	.yres = 480,
	323	.hsync_len = 4,
	324	.vsync_len = 2,
	325	.left_margin = 10,
	326	.upper_margin = 5,
	327	.right_margin = 10,
	328	.lower_margin = 5,
	329	.sync = (FB_SYNC_HOR_HIGH_ACT \|
	330	FB_SYNC_VERT_HIGH_ACT),
	331	.cmap_greyscale = 0,
	332	};
	333
	334	static struct pxafb_mach_info generic_stn_640x480 = {
	335	.modes = &generic_stn_640x480_mode,
	336	.num_modes = 1,
9587319b	337	.lcd_conn = LCD_COLOR_STN_8BPP \| LCD_AC_BIAS_FREQ(0xff),
3696a8a4 MR	338	.cmap_inverse = 0,
	339	.cmap_static = 0,
	340	};
	341
da591937	342	static struct pxafb_mach_info *cmx2xx_display = &generic_crt_640x480;
3696a8a4	343
da591937	344	static int __init cmx2xx_set_display(char *str)
3696a8a4 MR	345	{
	346	int disp_type = simple_strtol(str, NULL, 0);
	347	switch (disp_type) {
	348	case MTYPE_STN320x240:
da591937	349	cmx2xx_display = &generic_stn_320x240;
3696a8a4 MR	350	break;
3696a8a4 MR	351	case MTYPE_TFT640x480:
da591937	352	cmx2xx_display = &generic_tft_640x480;
3696a8a4 MR	353	break;
3696a8a4 MR	354	case MTYPE_CRT640x480:
da591937	355	cmx2xx_display = &generic_crt_640x480;
3696a8a4 MR	356	break;
3696a8a4 MR	357	case MTYPE_CRT800x600:
da591937	358	cmx2xx_display = &generic_crt_800x600;
3696a8a4 MR	359	break;
3696a8a4 MR	360	case MTYPE_TFT320x240:
da591937	361	cmx2xx_display = &generic_tft_320x240;
3696a8a4 MR	362	break;
3696a8a4 MR	363	case MTYPE_STN640x480:
da591937	364	cmx2xx_display = &generic_stn_640x480;
3696a8a4 MR	365	break;
3696a8a4 MR	366	default: /* fallback to CRT 640x480 */
da591937	367	cmx2xx_display = &generic_crt_640x480;
3696a8a4 MR	368	break;
	369	}
	370	return 1;
	371	}
	372
	373	/*
	374	This should be done really early to get proper configuration for
	375	frame buffer.
da591937	376	Indeed, pxafb parameters can be used istead, but CM-X2XX bootloader
3696a8a4 MR	377	has limitied line length for kernel command line, and also it will
	378	break compatibitlty with proprietary releases already in field.
	379	*/
da591937	380	__setup("monitor=", cmx2xx_set_display);
3696a8a4	381
da591937	382	static void __init cmx2xx_init_display(void)
2f01a973	383	{
4321e1a1	384	pxa_set_fb_info(NULL, cmx2xx_display);
2f01a973 MR	385	}
2f01a973 MR	386	#else
da591937	387	static inline void cmx2xx_init_display(void) {}
2f01a973 MR	388	#endif
2f01a973 MR	389
3696a8a4 MR	390	#ifdef CONFIG_PM
	391	static unsigned long sleep_save_msc[10];
	392
2eaa03b5	393	static int cmx2xx_suspend(void)
3696a8a4	394	{
da591937	395	cmx2xx_pci_suspend();
3696a8a4 MR	396
3696a8a4 MR	397	/* save MSC registers */
ad68bb9f MV	398	sleep_save_msc[0] = __raw_readl(MSC0);
	399	sleep_save_msc[1] = __raw_readl(MSC1);
	400	sleep_save_msc[2] = __raw_readl(MSC2);
3696a8a4 MR	401
	402	/* setup power saving mode registers */
	403	PCFR = 0x0;
	404	PSLR = 0xff400000;
	405	PMCR = 0x00000005;
	406	PWER = 0x80000000;
	407	PFER = 0x00000000;
	408	PRER = 0x00000000;
	409	PGSR0 = 0xC0018800;
	410	PGSR1 = 0x004F0002;
	411	PGSR2 = 0x6021C000;
	412	PGSR3 = 0x00020000;
	413
	414	return 0;
	415	}
	416
2eaa03b5	417	static void cmx2xx_resume(void)
3696a8a4	418	{
da591937	419	cmx2xx_pci_resume();
3696a8a4 MR	420
3696a8a4 MR	421	/* restore MSC registers */
ad68bb9f MV	422	__raw_writel(sleep_save_msc[0], MSC0);
	423	__raw_writel(sleep_save_msc[1], MSC1);
	424	__raw_writel(sleep_save_msc[2], MSC2);
3696a8a4 MR	425	}
3696a8a4 MR	426
2eaa03b5	427	static struct syscore_ops cmx2xx_pm_syscore_ops = {
da591937 MR	428	.resume = cmx2xx_resume,
da591937 MR	429	.suspend = cmx2xx_suspend,
3696a8a4 MR	430	};
3696a8a4 MR	431
da591937	432	static int __init cmx2xx_pm_init(void)
3696a8a4	433	{
2eaa03b5 RW	434	register_syscore_ops(&cmx2xx_pm_syscore_ops);
	435
	436	return 0;
3696a8a4 MR	437	}
3696a8a4 MR	438	#else
da591937	439	static int __init cmx2xx_pm_init(void) { return 0; }
3696a8a4 MR	440	#endif
3696a8a4 MR	441
2f01a973	442	#if defined(CONFIG_SND_PXA2XX_AC97) \|\| defined(CONFIG_SND_PXA2XX_AC97_MODULE)
da591937	443	static void __init cmx2xx_init_ac97(void)
3696a8a4	444	{
9f19d638	445	pxa_set_ac97_info(NULL);
2f01a973 MR	446	}
2f01a973 MR	447	#else
da591937	448	static inline void cmx2xx_init_ac97(void) {}
2f01a973	449	#endif
3696a8a4	450
da591937 MR	451	static void __init cmx2xx_init(void)
da591937 MR	452	{
cc155c6f RK	453	pxa_set_ffuart_info(NULL);
	454	pxa_set_btuart_info(NULL);
	455	pxa_set_stuart_info(NULL);
	456
da591937 MR	457	cmx2xx_pm_init();
da591937 MR	458
a7f3f030 MR	459	if (cpu_is_pxa25x())
	460	cmx255_init();
	461	else
	462	cmx270_init();
da591937 MR	463
	464	cmx2xx_init_dm9000();
	465	cmx2xx_init_display();
	466	cmx2xx_init_ac97();
	467	cmx2xx_init_touchscreen();
	468	cmx2xx_init_leds();
	469	}
	470
	471	static void __init cmx2xx_init_irq(void)
3696a8a4	472	{
a7f3f030 MR	473	if (cpu_is_pxa25x()) {
	474	pxa25x_init_irq();
	475	cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ);
	476	} else {
	477	pxa27x_init_irq();
	478	cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ);
	479	}
2f01a973	480	}
3696a8a4	481
2f01a973 MR	482	#ifdef CONFIG_PCI
2f01a973 MR	483	/* Map PCI companion statically */
da591937	484	static struct map_desc cmx2xx_io_desc[] __initdata = {
2f01a973	485	[0] = { /* PCI bridge */
97b09da4	486	.virtual = (unsigned long)CMX2XX_IT8152_VIRT,
2f01a973 MR	487	.pfn = __phys_to_pfn(PXA_CS4_PHYS),
	488	.length = SZ_64M,
	489	.type = MT_DEVICE
	490	},
	491	};
3696a8a4	492
da591937	493	static void __init cmx2xx_map_io(void)
2f01a973	494	{
851982c1 MV	495	if (cpu_is_pxa25x())
	496	pxa25x_map_io();
	497
	498	if (cpu_is_pxa27x())
	499	pxa27x_map_io();
	500
da591937	501	iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
3696a8a4	502
da591937	503	it8152_base_address = CMX2XX_IT8152_VIRT;
3696a8a4	504	}
2f01a973	505	#else
da591937	506	static void __init cmx2xx_map_io(void)
3696a8a4	507	{
851982c1 MV	508	if (cpu_is_pxa25x())
	509	pxa25x_map_io();
	510
	511	if (cpu_is_pxa27x())
	512	pxa27x_map_io();
3696a8a4	513	}
2f01a973	514	#endif
3696a8a4	515
da591937	516	MACHINE_START(ARMCORE, "Compulab CM-X2XX")
7375aba6	517	.atag_offset = 0x100,
da591937	518	.map_io = cmx2xx_map_io,
6ac6b817	519	.nr_irqs = CMX2XX_NR_IRQS,
da591937	520	.init_irq = cmx2xx_init_irq,
8a97ae2f EM	521	/* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */
8a97ae2f EM	522	.handle_irq = pxa25x_handle_irq,
6bb27d73	523	.init_time = pxa_timer_init,
da591937	524	.init_machine = cmx2xx_init,
805e88dc NP	525	#ifdef CONFIG_PCI
	526	.dma_zone_size = SZ_64M,
	527	#endif
271a74fc	528	.restart = pxa_restart,
3696a8a4	529	MACHINE_END