Commit | Line | Data |
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9dd0b194 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-orion5x/include/mach/irqs.h |
9dd0b194 LB |
3 | * |
4 | * IRQ definitions for Orion SoC | |
5 | * | |
6 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_IRQS_H | |
14 | #define __ASM_ARCH_IRQS_H | |
15 | ||
9dd0b194 LB |
16 | /* |
17 | * Orion Main Interrupt Controller | |
18 | */ | |
5be9fc23 BC |
19 | #define IRQ_ORION5X_BRIDGE (1 + 0) |
20 | #define IRQ_ORION5X_DOORBELL_H2C (1 + 1) | |
21 | #define IRQ_ORION5X_DOORBELL_C2H (1 + 2) | |
22 | #define IRQ_ORION5X_UART0 (1 + 3) | |
23 | #define IRQ_ORION5X_UART1 (1 + 4) | |
24 | #define IRQ_ORION5X_I2C (1 + 5) | |
25 | #define IRQ_ORION5X_GPIO_0_7 (1 + 6) | |
26 | #define IRQ_ORION5X_GPIO_8_15 (1 + 7) | |
27 | #define IRQ_ORION5X_GPIO_16_23 (1 + 8) | |
28 | #define IRQ_ORION5X_GPIO_24_31 (1 + 9) | |
29 | #define IRQ_ORION5X_PCIE0_ERR (1 + 10) | |
30 | #define IRQ_ORION5X_PCIE0_INT (1 + 11) | |
31 | #define IRQ_ORION5X_USB1_CTRL (1 + 12) | |
32 | #define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) | |
33 | #define IRQ_ORION5X_PCI_ERR (1 + 15) | |
34 | #define IRQ_ORION5X_USB_BR_ERR (1 + 16) | |
35 | #define IRQ_ORION5X_USB0_CTRL (1 + 17) | |
36 | #define IRQ_ORION5X_ETH_RX (1 + 18) | |
37 | #define IRQ_ORION5X_ETH_TX (1 + 19) | |
38 | #define IRQ_ORION5X_ETH_MISC (1 + 20) | |
39 | #define IRQ_ORION5X_ETH_SUM (1 + 21) | |
40 | #define IRQ_ORION5X_ETH_ERR (1 + 22) | |
41 | #define IRQ_ORION5X_IDMA_ERR (1 + 23) | |
42 | #define IRQ_ORION5X_IDMA_0 (1 + 24) | |
43 | #define IRQ_ORION5X_IDMA_1 (1 + 25) | |
44 | #define IRQ_ORION5X_IDMA_2 (1 + 26) | |
45 | #define IRQ_ORION5X_IDMA_3 (1 + 27) | |
46 | #define IRQ_ORION5X_CESA (1 + 28) | |
47 | #define IRQ_ORION5X_SATA (1 + 29) | |
48 | #define IRQ_ORION5X_XOR0 (1 + 30) | |
49 | #define IRQ_ORION5X_XOR1 (1 + 31) | |
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50 | |
51 | /* | |
52 | * Orion General Purpose Pins | |
53 | */ | |
5be9fc23 | 54 | #define IRQ_ORION5X_GPIO_START 33 |
9569dae7 | 55 | #define NR_GPIO_IRQS 32 |
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56 | |
57 | #define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) | |
58 | ||
59 | ||
60 | #endif |