projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAP3: PM: Wait for SDRC ready iso a blind delay
[linux-2.6-block.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
2f5939c3
RN		 8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8bd22949
KH		 11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
28
ce491cf8
TL		 29#include <plat/sram.h>
30#include <plat/clockdomain.h>
31#include <plat/powerdomain.h>
32#include <plat/control.h>
33#include <plat/serial.h>
61255ab9 34#include <plat/sdrc.h>
2f5939c3
RN		 35#include <plat/prcm.h>
36#include <plat/gpmc.h>
f2d11858 37#include <plat/dma.h>
8bd22949 38
57f277b0
RN		 39#include <asm/tlbflush.h>
40
8bd22949
KH		 41#include "cm.h"
42#include "cm-regbits-34xx.h"
43#include "prm-regbits-34xx.h"
44
45#include "prm.h"
46#include "pm.h"
13a6fe0f
TK		 47#include "sdrc.h"
48
49#define SDRC_POWER_AUTOCOUNT_SHIFT 8
50#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
51#define SDRC_POWER_CLKCTRL_SHIFT 4
52#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
53#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
8bd22949 54
2f5939c3
RN		 55/* Scratchpad offsets */
56#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
57#define OMAP343X_TABLE_VALUE_OFFSET 0x30
58#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
59
8bd22949
KH		 60struct power_state {
61 struct powerdomain *pwrdm;
62 u32 next_state;
10f90ed2 63#ifdef CONFIG_SUSPEND
8bd22949 64 u32 saved_state;
10f90ed2 65#endif
8bd22949
KH		 66 struct list_head node;
67};
68
69static LIST_HEAD(pwrst_list);
70
71static void (*_omap_sram_idle)(u32 *addr, int save_state);
72
27d59a4a
TK		 73static int (*_omap_save_secure_sram)(u32 *addr);
74
fa3c2a4f
RN		 75static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
76static struct powerdomain *core_pwrdm, *per_pwrdm;
77
78static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
8bd22949 79
2f5939c3
RN		 80static inline void omap3_per_save_context(void)
81{
82 omap_gpio_save_context();
83}
84
85static inline void omap3_per_restore_context(void)
86{
87 omap_gpio_restore_context();
88}
89
90static void omap3_core_save_context(void)
91{
92 u32 control_padconf_off;
93
94 /* Save the padconf registers */
95 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
96 control_padconf_off |= START_PADCONF_SAVE;
97 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
98 /* wait for the save to complete */
99 while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
100 & PADCONF_SAVE_DONE)
101 ;
102 /* Save the Interrupt controller context */
103 omap_intc_save_context();
104 /* Save the GPMC context */
105 omap3_gpmc_save_context();
106 /* Save the system control module context, padconf already save above*/
107 omap3_control_save_context();
f2d11858 108 omap_dma_global_context_save();
2f5939c3
RN		 109}
110
111static void omap3_core_restore_context(void)
112{
113 /* Restore the control module context, padconf restored by h/w */
114 omap3_control_restore_context();
115 /* Restore the GPMC context */
116 omap3_gpmc_restore_context();
117 /* Restore the interrupt controller context */
118 omap_intc_restore_context();
f2d11858 119 omap_dma_global_context_restore();
2f5939c3
RN		 120}
121
9d97140b
TK		 122/*
123 * FIXME: This function should be called before entering off-mode after
124 * OMAP3 secure services have been accessed. Currently it is only called
125 * once during boot sequence, but this works as we are not using secure
126 * services.
127 */
27d59a4a
TK		 128static void omap3_save_secure_ram_context(u32 target_mpu_state)
129{
130 u32 ret;
131
132 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a
TK		 133 /*
134 * MPU next state must be set to POWER_ON temporarily,
135 * otherwise the WFI executed inside the ROM code
136 * will hang the system.
137 */
138 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
139 ret = _omap_save_secure_sram((u32 *)
140 __pa(omap3_secure_ram_storage));
141 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
142 /* Following is for error tracking, it should not happen */
143 if (ret) {
144 printk(KERN_ERR "save_secure_sram() returns %08x\n",
145 ret);
146 while (1)
147 ;
148 }
149 }
150}
151
77da2d91
JH		 152/*
153 * PRCM Interrupt Handler Helper Function
154 *
155 * The purpose of this function is to clear any wake-up events latched
156 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
157 * may occur whilst attempting to clear a PM_WKST_x register and thus
158 * set another bit in this register. A while loop is used to ensure
159 * that any peripheral wake-up events occurring while attempting to
160 * clear the PM_WKST_x are detected and cleared.
161 */
8cb0ac99 162static int prcm_clear_mod_irqs(s16 module, u8 regs)
8bd22949 163{
71a80775 164 u32 wkst, fclk, iclk, clken;
77da2d91
JH		 165 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
166 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
167 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
5d805978
PW		 168 u16 grpsel_off = (regs == 3) ?
169 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
8cb0ac99 170 int c = 0;
8bd22949 171
77da2d91 172 wkst = prm_read_mod_reg(module, wkst_off);
5d805978 173 wkst &= prm_read_mod_reg(module, grpsel_off);
8bd22949 174 if (wkst) {
77da2d91
JH		 175 iclk = cm_read_mod_reg(module, iclk_off);
176 fclk = cm_read_mod_reg(module, fclk_off);
177 while (wkst) {
71a80775
VP		 178 clken = wkst;
179 cm_set_mod_reg_bits(clken, module, iclk_off);
180 /*
181 * For USBHOST, we don't know whether HOST1 or
182 * HOST2 woke us up, so enable both f-clocks
183 */
184 if (module == OMAP3430ES2_USBHOST_MOD)
185 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
186 cm_set_mod_reg_bits(clken, module, fclk_off);
77da2d91
JH		 187 prm_write_mod_reg(wkst, module, wkst_off);
188 wkst = prm_read_mod_reg(module, wkst_off);
8cb0ac99 189 c++;
77da2d91
JH		 190 }
191 cm_write_mod_reg(iclk, module, iclk_off);
192 cm_write_mod_reg(fclk, module, fclk_off);
8bd22949 193 }
8cb0ac99
PW		 194
195 return c;
196}
197
198static int _prcm_int_handle_wakeup(void)
199{
200 int c;
201
202 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
203 c += prcm_clear_mod_irqs(CORE_MOD, 1);
204 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
205 if (omap_rev() > OMAP3430_REV_ES1_0) {
206 c += prcm_clear_mod_irqs(CORE_MOD, 3);
207 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
208 }
209
210 return c;
77da2d91 211}
8bd22949 212
77da2d91
JH		 213/*
214 * PRCM Interrupt Handler
215 *
216 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
217 * interrupts from the PRCM for the MPU. These bits must be cleared in
218 * order to clear the PRCM interrupt. The PRCM interrupt handler is
219 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
220 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
221 * register indicates that a wake-up event is pending for the MPU and
222 * this bit can only be cleared if the all the wake-up events latched
223 * in the various PM_WKST_x registers have been cleared. The interrupt
224 * handler is implemented using a do-while loop so that if a wake-up
225 * event occurred during the processing of the prcm interrupt handler
226 * (setting a bit in the corresponding PM_WKST_x register and thus
227 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
228 * this would be handled.
229 */
230static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
231{
232 u32 irqstatus_mpu;
8cb0ac99 233 int c = 0;
77da2d91
JH		 234
235 do {
77da2d91
JH		 236 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
237 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
8cb0ac99
PW		 238
239 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
240 c = _prcm_int_handle_wakeup();
241
242 /*
243 * Is the MPU PRCM interrupt handler racing with the
244 * IVA2 PRCM interrupt handler ?
245 */
246 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
247 "but no wakeup sources are marked\n");
248 } else {
249 /* XXX we need to expand our PRCM interrupt handler */
250 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
251 "no code to handle it (%08x)\n", irqstatus_mpu);
252 }
253
77da2d91
JH		 254 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
255 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
8bd22949 256
77da2d91 257 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
8bd22949
KH		 258
259 return IRQ_HANDLED;
260}
261
57f277b0
RN		 262static void restore_control_register(u32 val)
263{
264 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
265}
266
267/* Function to restore the table entry that was modified for enabling MMU */
268static void restore_table_entry(void)
269{
270 u32 *scratchpad_address;
271 u32 previous_value, control_reg_value;
272 u32 *address;
273
274 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
275
276 /* Get address of entry that was modified */
277 address = (u32 *)__raw_readl(scratchpad_address +
278 OMAP343X_TABLE_ADDRESS_OFFSET);
279 /* Get the previous value which needs to be restored */
280 previous_value = __raw_readl(scratchpad_address +
281 OMAP343X_TABLE_VALUE_OFFSET);
282 address = __va(address);
283 *address = previous_value;
284 flush_tlb_all();
285 control_reg_value = __raw_readl(scratchpad_address
286 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
287 /* This will enable caches and prediction */
288 restore_control_register(control_reg_value);
289}
290
8bd22949
KH		 291static void omap_sram_idle(void)
292{
293 /* Variable to tell what needs to be saved and restored
294 * in omap_sram_idle*/
295 /* save_state = 0 => Nothing to save and restored */
296 /* save_state = 1 => Only L1 and logic lost */
297 /* save_state = 2 => Only L2 lost */
298 /* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f
RN		 299 int save_state = 0;
300 int mpu_next_state = PWRDM_POWER_ON;
301 int per_next_state = PWRDM_POWER_ON;
302 int core_next_state = PWRDM_POWER_ON;
2f5939c3 303 int core_prev_state, per_prev_state;
13a6fe0f 304 u32 sdrc_pwr = 0;
8bd22949
KH		 305
306 if (!_omap_sram_idle)
307 return;
308
fa3c2a4f
RN		 309 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
310 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
311 pwrdm_clear_all_prev_pwrst(core_pwrdm);
312 pwrdm_clear_all_prev_pwrst(per_pwrdm);
313
8bd22949
KH		 314 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
315 switch (mpu_next_state) {
fa3c2a4f 316 case PWRDM_POWER_ON:
8bd22949
KH		 317 case PWRDM_POWER_RET:
318 /* No need to save context */
319 save_state = 0;
320 break;
61255ab9
RN		 321 case PWRDM_POWER_OFF:
322 save_state = 3;
323 break;
8bd22949
KH		 324 default:
325 /* Invalid state */
326 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
327 return;
328 }
fe617af7
PDS		 329 pwrdm_pre_transition();
330
fa3c2a4f
RN		 331 /* NEON control */
332 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
333 set_pwrdm_state(neon_pwrdm, mpu_next_state);
334
335 /* CORE & PER */
336 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
337 if (core_next_state < PWRDM_POWER_ON) {
338 omap2_gpio_prepare_for_retention();
339 omap_uart_prepare_idle(0);
340 omap_uart_prepare_idle(1);
341 /* PER changes only with core */
342 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
2f5939c3 343 if (per_next_state < PWRDM_POWER_ON) {
fa3c2a4f 344 omap_uart_prepare_idle(2);
2f5939c3
RN		 345 if (per_next_state == PWRDM_POWER_OFF)
346 omap3_per_save_context();
347 }
348 if (core_next_state == PWRDM_POWER_OFF) {
349 omap3_core_save_context();
350 omap3_prcm_save_context();
351 }
fa3c2a4f
RN		 352 /* Enable IO-PAD wakeup */
353 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
354 }
8bd22949 355
13a6fe0f
TK		 356 /*
357 * Force SDRAM controller to self-refresh mode after timeout on
358 * autocount. This is needed on ES3.0 to avoid SDRAM controller
359 * hang-ups.
360 */
361 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
362 omap_type() != OMAP2_DEVICE_TYPE_GP &&
363 core_next_state == PWRDM_POWER_OFF) {
364 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
365 sdrc_write_reg((sdrc_pwr &
366 ~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) |
367 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
368 SDRC_SELF_REFRESH_ON_AUTOCOUNT, SDRC_POWER);
369 }
370
61255ab9
RN		 371 /*
372 * omap3_arm_context is the location where ARM registers
373 * get saved. The restore path then reads from this
374 * location and restores them back.
375 */
376 _omap_sram_idle(omap3_arm_context, save_state);
8bd22949
KH		 377 cpu_init();
378
13a6fe0f
TK		 379 /* Restore normal SDRAM settings */
380 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
381 omap_type() != OMAP2_DEVICE_TYPE_GP &&
382 core_next_state == PWRDM_POWER_OFF)
383 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
384
57f277b0
RN		 385 /* Restore table entry modified during MMU restoration */
386 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
387 restore_table_entry();
388
fa3c2a4f
RN		 389 if (core_next_state < PWRDM_POWER_ON) {
390 if (per_next_state < PWRDM_POWER_ON)
391 omap_uart_resume_idle(2);
392 omap_uart_resume_idle(1);
393 omap_uart_resume_idle(0);
394
395 /* Disable IO-PAD wakeup */
396 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
2f5939c3
RN		 397 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
398 if (core_prev_state == PWRDM_POWER_OFF) {
399 omap3_core_restore_context();
400 omap3_prcm_restore_context();
401 omap3_sram_restore_context();
8a917d2f 402 omap2_sms_restore_context();
2f5939c3
RN		 403 }
404 if (per_next_state < PWRDM_POWER_ON) {
405 per_prev_state =
406 pwrdm_read_prev_pwrst(per_pwrdm);
407 if (per_prev_state == PWRDM_POWER_OFF)
408 omap3_per_restore_context();
409 }
fa3c2a4f
RN		 410 omap2_gpio_resume_after_retention();
411 }
fe617af7
PDS		 412
413 pwrdm_post_transition();
414
8bd22949
KH		 415}
416
417/*
418 * Check if functional clocks are enabled before entering
419 * sleep. This function could be behind CONFIG_PM_DEBUG
420 * when all drivers are configuring their sysconfig registers
421 * properly and using their clocks properly.
422 */
423static int omap3_fclks_active(void)
424{
425 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
426 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
427
428 fck_core1 = cm_read_mod_reg(CORE_MOD,
429 CM_FCLKEN1);
430 if (omap_rev() > OMAP3430_REV_ES1_0) {
431 fck_core3 = cm_read_mod_reg(CORE_MOD,
432 OMAP3430ES2_CM_FCLKEN3);
433 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
434 CM_FCLKEN);
435 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
436 CM_FCLKEN);
437 } else
438 fck_sgx = cm_read_mod_reg(GFX_MOD,
439 OMAP3430ES2_CM_FCLKEN3);
440 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
441 CM_FCLKEN);
442 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
443 CM_FCLKEN);
444 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
445 CM_FCLKEN);
4af4016c
KH		 446
447 /* Ignore UART clocks. These are handled by UART core (serial.c) */
448 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
449 fck_per &= ~OMAP3430_EN_UART3;
450
8bd22949
KH		 451 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
452 fck_cam | fck_per | fck_usbhost)
453 return 1;
454 return 0;
455}
456
457static int omap3_can_sleep(void)
458{
4af4016c
KH		 459 if (!omap_uart_can_sleep())
460 return 0;
8bd22949
KH		 461 if (omap3_fclks_active())
462 return 0;
463 return 1;
464}
465
466/* This sets pwrdm state (other than mpu & core. Currently only ON &
467 * RET are supported. Function is assuming that clkdm doesn't have
468 * hw_sup mode enabled. */
469static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
470{
471 u32 cur_state;
472 int sleep_switch = 0;
473 int ret = 0;
474
475 if (pwrdm == NULL || IS_ERR(pwrdm))
476 return -EINVAL;
477
478 while (!(pwrdm->pwrsts & (1 << state))) {
479 if (state == PWRDM_POWER_OFF)
480 return ret;
481 state--;
482 }
483
484 cur_state = pwrdm_read_next_pwrst(pwrdm);
485 if (cur_state == state)
486 return ret;
487
488 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
489 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
490 sleep_switch = 1;
491 pwrdm_wait_transition(pwrdm);
492 }
493
494 ret = pwrdm_set_next_pwrst(pwrdm, state);
495 if (ret) {
496 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
497 pwrdm->name);
498 goto err;
499 }
500
501 if (sleep_switch) {
502 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
503 pwrdm_wait_transition(pwrdm);
fe617af7 504 pwrdm_state_switch(pwrdm);
8bd22949
KH		 505 }
506
507err:
508 return ret;
509}
510
511static void omap3_pm_idle(void)
512{
513 local_irq_disable();
514 local_fiq_disable();
515
516 if (!omap3_can_sleep())
517 goto out;
518
519 if (omap_irq_pending())
520 goto out;
521
522 omap_sram_idle();
523
524out:
525 local_fiq_enable();
526 local_irq_enable();
527}
528
10f90ed2 529#ifdef CONFIG_SUSPEND
2466211e
TK		 530static suspend_state_t suspend_state;
531
8bd22949
KH		 532static int omap3_pm_prepare(void)
533{
534 disable_hlt();
535 return 0;
536}
537
538static int omap3_pm_suspend(void)
539{
540 struct power_state *pwrst;
541 int state, ret = 0;
542
543 /* Read current next_pwrsts */
544 list_for_each_entry(pwrst, &pwrst_list, node)
545 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
546 /* Set ones wanted by suspend */
547 list_for_each_entry(pwrst, &pwrst_list, node) {
548 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
549 goto restore;
550 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
551 goto restore;
552 }
553
4af4016c 554 omap_uart_prepare_suspend();
8bd22949
KH		 555 omap_sram_idle();
556
557restore:
558 /* Restore next_pwrsts */
559 list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949
KH		 560 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
561 if (state > pwrst->next_state) {
562 printk(KERN_INFO "Powerdomain (%s) didn't enter "
563 "target state %d\n",
564 pwrst->pwrdm->name, pwrst->next_state);
565 ret = -1;
566 }
6c5f8039 567 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949
KH		 568 }
569 if (ret)
570 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
571 else
572 printk(KERN_INFO "Successfully put all powerdomains "
573 "to target state\n");
574
575 return ret;
576}
577
2466211e 578static int omap3_pm_enter(suspend_state_t unused)
8bd22949
KH		 579{
580 int ret = 0;
581
2466211e 582 switch (suspend_state) {
8bd22949
KH		 583 case PM_SUSPEND_STANDBY:
584 case PM_SUSPEND_MEM:
585 ret = omap3_pm_suspend();
586 break;
587 default:
588 ret = -EINVAL;
589 }
590
591 return ret;
592}
593
594static void omap3_pm_finish(void)
595{
596 enable_hlt();
597}
598
2466211e
TK		 599/* Hooks to enable / disable UART interrupts during suspend */
600static int omap3_pm_begin(suspend_state_t state)
601{
602 suspend_state = state;
603 omap_uart_enable_irqs(0);
604 return 0;
605}
606
607static void omap3_pm_end(void)
608{
609 suspend_state = PM_SUSPEND_ON;
610 omap_uart_enable_irqs(1);
611 return;
612}
613
8bd22949 614static struct platform_suspend_ops omap_pm_ops = {
2466211e
TK		 615 .begin = omap3_pm_begin,
616 .end = omap3_pm_end,
8bd22949
KH		 617 .prepare = omap3_pm_prepare,
618 .enter = omap3_pm_enter,
619 .finish = omap3_pm_finish,
620 .valid = suspend_valid_only_mem,
621};
10f90ed2 622#endif /* CONFIG_SUSPEND */
8bd22949 623
1155e426
KH		 624
625/**
626 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
627 * retention
628 *
629 * In cases where IVA2 is activated by bootcode, it may prevent
630 * full-chip retention or off-mode because it is not idle. This
631 * function forces the IVA2 into idle state so it can go
632 * into retention/off and thus allow full-chip retention/off.
633 *
634 **/
635static void __init omap3_iva_idle(void)
636{
637 /* ensure IVA2 clock is disabled */
638 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
639
640 /* if no clock activity, nothing else to do */
641 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
642 OMAP3430_CLKACTIVITY_IVA2_MASK))
643 return;
644
645 /* Reset IVA2 */
646 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
647 OMAP3430_RST2_IVA2 |
648 OMAP3430_RST3_IVA2,
649 OMAP3430_IVA2_MOD, RM_RSTCTRL);
650
651 /* Enable IVA2 clock */
652 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
653 OMAP3430_IVA2_MOD, CM_FCLKEN);
654
655 /* Set IVA2 boot mode to 'idle' */
656 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
657 OMAP343X_CONTROL_IVA2_BOOTMOD);
658
659 /* Un-reset IVA2 */
660 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
661
662 /* Disable IVA2 clock */
663 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
664
665 /* Reset IVA2 */
666 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
667 OMAP3430_RST2_IVA2 |
668 OMAP3430_RST3_IVA2,
669 OMAP3430_IVA2_MOD, RM_RSTCTRL);
670}
671
8111b221 672static void __init omap3_d2d_idle(void)
8bd22949 673{
8111b221
KH		 674 u16 mask, padconf;
675
676 /* In a stand alone OMAP3430 where there is not a stacked
677 * modem for the D2D Idle Ack and D2D MStandby must be pulled
678 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
679 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
680 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
681 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
682 padconf |= mask;
683 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
684
685 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
686 padconf |= mask;
687 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
688
8bd22949
KH		 689 /* reset modem */
690 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
691 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
692 CORE_MOD, RM_RSTCTRL);
693 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
8111b221 694}
8bd22949 695
8111b221
KH		 696static void __init prcm_setup_regs(void)
697{
8bd22949
KH		 698 /* XXX Reset all wkdeps. This should be done when initializing
699 * powerdomains */
700 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
701 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
702 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
703 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
704 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
705 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
706 if (omap_rev() > OMAP3430_REV_ES1_0) {
707 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
708 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
709 } else
710 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
711
712 /*
713 * Enable interface clock autoidle for all modules.
714 * Note that in the long run this should be done by clockfw
715 */
716 cm_write_mod_reg(
8111b221 717 OMAP3430_AUTO_MODEM |
8bd22949
KH		 718 OMAP3430ES2_AUTO_MMC3 |
719 OMAP3430ES2_AUTO_ICR |
720 OMAP3430_AUTO_AES2 |
721 OMAP3430_AUTO_SHA12 |
722 OMAP3430_AUTO_DES2 |
723 OMAP3430_AUTO_MMC2 |
724 OMAP3430_AUTO_MMC1 |
725 OMAP3430_AUTO_MSPRO |
726 OMAP3430_AUTO_HDQ |
727 OMAP3430_AUTO_MCSPI4 |
728 OMAP3430_AUTO_MCSPI3 |
729 OMAP3430_AUTO_MCSPI2 |
730 OMAP3430_AUTO_MCSPI1 |
731 OMAP3430_AUTO_I2C3 |
732 OMAP3430_AUTO_I2C2 |
733 OMAP3430_AUTO_I2C1 |
734 OMAP3430_AUTO_UART2 |
735 OMAP3430_AUTO_UART1 |
736 OMAP3430_AUTO_GPT11 |
737 OMAP3430_AUTO_GPT10 |
738 OMAP3430_AUTO_MCBSP5 |
739 OMAP3430_AUTO_MCBSP1 |
740 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
741 OMAP3430_AUTO_MAILBOXES |
742 OMAP3430_AUTO_OMAPCTRL |
743 OMAP3430ES1_AUTO_FSHOSTUSB |
744 OMAP3430_AUTO_HSOTGUSB |
8111b221 745 OMAP3430_AUTO_SAD2D |
8bd22949
KH		 746 OMAP3430_AUTO_SSI,
747 CORE_MOD, CM_AUTOIDLE1);
748
749 cm_write_mod_reg(
750 OMAP3430_AUTO_PKA |
751 OMAP3430_AUTO_AES1 |
752 OMAP3430_AUTO_RNG |
753 OMAP3430_AUTO_SHA11 |
754 OMAP3430_AUTO_DES1,
755 CORE_MOD, CM_AUTOIDLE2);
756
757 if (omap_rev() > OMAP3430_REV_ES1_0) {
758 cm_write_mod_reg(
8111b221 759 OMAP3430_AUTO_MAD2D |
8bd22949
KH		 760 OMAP3430ES2_AUTO_USBTLL,
761 CORE_MOD, CM_AUTOIDLE3);
762 }
763
764 cm_write_mod_reg(
765 OMAP3430_AUTO_WDT2 |
766 OMAP3430_AUTO_WDT1 |
767 OMAP3430_AUTO_GPIO1 |
768 OMAP3430_AUTO_32KSYNC |
769 OMAP3430_AUTO_GPT12 |
770 OMAP3430_AUTO_GPT1 ,
771 WKUP_MOD, CM_AUTOIDLE);
772
773 cm_write_mod_reg(
774 OMAP3430_AUTO_DSS,
775 OMAP3430_DSS_MOD,
776 CM_AUTOIDLE);
777
778 cm_write_mod_reg(
779 OMAP3430_AUTO_CAM,
780 OMAP3430_CAM_MOD,
781 CM_AUTOIDLE);
782
783 cm_write_mod_reg(
784 OMAP3430_AUTO_GPIO6 |
785 OMAP3430_AUTO_GPIO5 |
786 OMAP3430_AUTO_GPIO4 |
787 OMAP3430_AUTO_GPIO3 |
788 OMAP3430_AUTO_GPIO2 |
789 OMAP3430_AUTO_WDT3 |
790 OMAP3430_AUTO_UART3 |
791 OMAP3430_AUTO_GPT9 |
792 OMAP3430_AUTO_GPT8 |
793 OMAP3430_AUTO_GPT7 |
794 OMAP3430_AUTO_GPT6 |
795 OMAP3430_AUTO_GPT5 |
796 OMAP3430_AUTO_GPT4 |
797 OMAP3430_AUTO_GPT3 |
798 OMAP3430_AUTO_GPT2 |
799 OMAP3430_AUTO_MCBSP4 |
800 OMAP3430_AUTO_MCBSP3 |
801 OMAP3430_AUTO_MCBSP2,
802 OMAP3430_PER_MOD,
803 CM_AUTOIDLE);
804
805 if (omap_rev() > OMAP3430_REV_ES1_0) {
806 cm_write_mod_reg(
807 OMAP3430ES2_AUTO_USBHOST,
808 OMAP3430ES2_USBHOST_MOD,
809 CM_AUTOIDLE);
810 }
811
812 /*
813 * Set all plls to autoidle. This is needed until autoidle is
814 * enabled by clockfw
815 */
816 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
817 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
818 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
819 MPU_MOD,
820 CM_AUTOIDLE2);
821 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
822 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
823 PLL_MOD,
824 CM_AUTOIDLE);
825 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
826 PLL_MOD,
827 CM_AUTOIDLE2);
828
829 /*
830 * Enable control of expternal oscillator through
831 * sys_clkreq. In the long run clock framework should
832 * take care of this.
833 */
834 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
835 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
836 OMAP3430_GR_MOD,
837 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
838
839 /* setup wakup source */
840 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
841 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
842 WKUP_MOD, PM_WKEN);
843 /* No need to write EN_IO, that is always enabled */
844 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
845 OMAP3430_EN_GPT12,
846 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
847 /* For some reason IO doesn't generate wakeup event even if
848 * it is selected to mpu wakeup goup */
849 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
850 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
1155e426 851
b427f92f 852 /* Enable wakeups in PER */
eb350f74
KH		 853 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
854 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
b427f92f
KH		 855 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
856 OMAP3430_PER_MOD, PM_WKEN);
eb350f74
KH		 857 /* and allow them to wake up MPU */
858 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
859 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
b427f92f 860 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
eb350f74
KH		 861 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
862
d3fd3290
KH		 863 /* Don't attach IVA interrupts */
864 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
865 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
866 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
867 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
868
b1340d17
KH		 869 /* Clear any pending 'reset' flags */
870 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
871 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
872 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
873 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
874 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
875 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
876 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
877
014c46db
KH		 878 /* Clear any pending PRCM interrupts */
879 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
880
040fed05
KH		 881 /* Don't attach IVA interrupts */
882 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
883 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
884 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
885 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
886
3a07ae30
KH		 887 /* Clear any pending 'reset' flags */
888 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
889 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
890 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
891 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
892 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
893 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
894 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
895
3a6667ac
KH		 896 /* Clear any pending PRCM interrupts */
897 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
898
1155e426 899 omap3_iva_idle();
8111b221 900 omap3_d2d_idle();
8bd22949
KH		 901}
902
68d4778c
TK		 903int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
904{
905 struct power_state *pwrst;
906
907 list_for_each_entry(pwrst, &pwrst_list, node) {
908 if (pwrst->pwrdm == pwrdm)
909 return pwrst->next_state;
910 }
911 return -EINVAL;
912}
913
914int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
915{
916 struct power_state *pwrst;
917
918 list_for_each_entry(pwrst, &pwrst_list, node) {
919 if (pwrst->pwrdm == pwrdm) {
920 pwrst->next_state = state;
921 return 0;
922 }
923 }
924 return -EINVAL;
925}
926
a23456e9 927static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
8bd22949
KH		 928{
929 struct power_state *pwrst;
930
931 if (!pwrdm->pwrsts)
932 return 0;
933
d3d381c6 934 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949
KH		 935 if (!pwrst)
936 return -ENOMEM;
937 pwrst->pwrdm = pwrdm;
938 pwrst->next_state = PWRDM_POWER_RET;
939 list_add(&pwrst->node, &pwrst_list);
940
941 if (pwrdm_has_hdwr_sar(pwrdm))
942 pwrdm_enable_hdwr_sar(pwrdm);
943
944 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
945}
946
947/*
948 * Enable hw supervised mode for all clockdomains if it's
949 * supported. Initiate sleep transition for other clockdomains, if
950 * they are not used
951 */
a23456e9 952static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
8bd22949
KH		 953{
954 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
955 omap2_clkdm_allow_idle(clkdm);
956 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
957 atomic_read(&clkdm->usecount) == 0)
958 omap2_clkdm_sleep(clkdm);
959 return 0;
960}
961
3231fc88
RN		 962void omap_push_sram_idle(void)
963{
964 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
965 omap34xx_cpu_suspend_sz);
27d59a4a
TK		 966 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
967 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
968 save_secure_ram_context_sz);
3231fc88
RN		 969}
970
7cc515f7 971static int __init omap3_pm_init(void)
8bd22949
KH		 972{
973 struct power_state *pwrst, *tmp;
974 int ret;
975
976 if (!cpu_is_omap34xx())
977 return -ENODEV;
978
979 printk(KERN_ERR "Power Management for TI OMAP3.\n");
980
981 /* XXX prcm_setup_regs needs to be before enabling hw
982 * supervised mode for powerdomains */
983 prcm_setup_regs();
984
985 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
986 (irq_handler_t)prcm_interrupt_handler,
987 IRQF_DISABLED, "prcm", NULL);
988 if (ret) {
989 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
990 INT_34XX_PRCM_MPU_IRQ);
991 goto err1;
992 }
993
a23456e9 994 ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949
KH		 995 if (ret) {
996 printk(KERN_ERR "Failed to setup powerdomains\n");
997 goto err2;
998 }
999
a23456e9 1000 (void) clkdm_for_each(clkdms_setup, NULL);
8bd22949
KH		 1001
1002 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1003 if (mpu_pwrdm == NULL) {
1004 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1005 goto err2;
1006 }
1007
fa3c2a4f
RN		 1008 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1009 per_pwrdm = pwrdm_lookup("per_pwrdm");
1010 core_pwrdm = pwrdm_lookup("core_pwrdm");
1011
3231fc88 1012 omap_push_sram_idle();
10f90ed2 1013#ifdef CONFIG_SUSPEND
8bd22949 1014 suspend_set_ops(&omap_pm_ops);
10f90ed2 1015#endif /* CONFIG_SUSPEND */
8bd22949
KH		 1016
1017 pm_idle = omap3_pm_idle;
1018
fa3c2a4f
RN		 1019 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1020 /*
1021 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1022 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1023 * waking up PER with every CORE wakeup - see
1024 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1025 */
1026 pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1027
27d59a4a
TK		 1028 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1029 omap3_secure_ram_storage =
1030 kmalloc(0x803F, GFP_KERNEL);
1031 if (!omap3_secure_ram_storage)
1032 printk(KERN_ERR "Memory allocation failed when"
1033 "allocating for secure sram context\n");
9d97140b
TK		 1034
1035 local_irq_disable();
1036 local_fiq_disable();
1037
1038 omap_dma_global_context_save();
1039 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1040 omap_dma_global_context_restore();
1041
1042 local_irq_enable();
1043 local_fiq_enable();
27d59a4a 1044 }
27d59a4a 1045
9d97140b 1046 omap3_save_scratchpad_contents();
8bd22949
KH		 1047err1:
1048 return ret;
1049err2:
1050 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1051 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1052 list_del(&pwrst->node);
1053 kfree(pwrst);
1054 }
1055 return ret;
1056}
1057
1058late_initcall(omap3_pm_init);
Linux 6.x block layer and io_uring tree(s)